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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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DMAENGINE: Support for ST-Ericssons DMA40 block v3
This is a straightforward driver for the ST-Ericsson DMA40 DMA controller found in U8500, implemented akin to the existing COH 901 318 driver. Signed-off-by: Linus Walleij <[email protected]> Acked-by: Srinidh Kasagar <[email protected]> Cc: [email protected] Cc: Alessandro Rubini <[email protected]> Signed-off-by: Andrew Morton <[email protected]> Signed-off-by: Dan Williams <[email protected]>
This commit is contained in:
Linus Walleij
Dan Williams
parent
6a3cd3ea48
commit
8d318a50b3
6 changed files with 3651 additions and 0 deletions
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@ -141,6 +141,13 @@ config COH901318
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help
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Enable support for ST-Ericsson COH 901 318 DMA.
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config STE_DMA40
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bool "ST-Ericsson DMA40 support"
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depends on ARCH_U8500
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select DMA_ENGINE
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help
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Support for ST-Ericsson DMA40 controller
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config AMCC_PPC440SPE_ADMA
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tristate "AMCC PPC440SPe ADMA support"
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depends on 440SPe || 440SP
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@ -21,3 +21,4 @@ obj-$(CONFIG_SH_DMAE) += shdma.o
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obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o
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obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += ppc4xx/
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obj-$(CONFIG_TIMB_DMA) += timb_dma.o
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obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
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2596
drivers/dma/ste_dma40.c
Normal file
2596
drivers/dma/ste_dma40.c
Normal file
File diff suppressed because it is too large
Load diff
454
drivers/dma/ste_dma40_ll.c
Normal file
454
drivers/dma/ste_dma40_ll.c
Normal file
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@ -0,0 +1,454 @@
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/*
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* driver/dma/ste_dma40_ll.c
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*
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* Copyright (C) ST-Ericsson 2007-2010
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* License terms: GNU General Public License (GPL) version 2
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* Author: Per Friden <per.friden@stericsson.com>
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* Author: Jonas Aaberg <jonas.aberg@stericsson.com>
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*/
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#include <linux/kernel.h>
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#include <plat/ste_dma40.h>
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#include "ste_dma40_ll.h"
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/* Sets up proper LCSP1 and LCSP3 register for a logical channel */
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void d40_log_cfg(struct stedma40_chan_cfg *cfg,
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u32 *lcsp1, u32 *lcsp3)
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{
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u32 l3 = 0; /* dst */
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u32 l1 = 0; /* src */
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/* src is mem? -> increase address pos */
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if (cfg->dir == STEDMA40_MEM_TO_PERIPH ||
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cfg->dir == STEDMA40_MEM_TO_MEM)
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l1 |= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;
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/* dst is mem? -> increase address pos */
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if (cfg->dir == STEDMA40_PERIPH_TO_MEM ||
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cfg->dir == STEDMA40_MEM_TO_MEM)
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l3 |= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;
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/* src is hw? -> master port 1 */
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if (cfg->dir == STEDMA40_PERIPH_TO_MEM ||
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cfg->dir == STEDMA40_PERIPH_TO_PERIPH)
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l1 |= 1 << D40_MEM_LCSP1_SCFG_MST_POS;
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/* dst is hw? -> master port 1 */
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if (cfg->dir == STEDMA40_MEM_TO_PERIPH ||
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cfg->dir == STEDMA40_PERIPH_TO_PERIPH)
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l3 |= 1 << D40_MEM_LCSP3_DCFG_MST_POS;
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l3 |= 1 << D40_MEM_LCSP3_DCFG_TIM_POS;
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l3 |= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
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l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
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l3 |= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS;
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l3 |= 1 << D40_MEM_LCSP3_DTCP_POS;
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l1 |= 1 << D40_MEM_LCSP1_SCFG_EIM_POS;
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l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
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l1 |= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS;
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l1 |= 1 << D40_MEM_LCSP1_STCP_POS;
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*lcsp1 = l1;
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*lcsp3 = l3;
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}
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/* Sets up SRC and DST CFG register for both logical and physical channels */
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void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
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u32 *src_cfg, u32 *dst_cfg, bool is_log)
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{
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u32 src = 0;
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u32 dst = 0;
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if (!is_log) {
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/* Physical channel */
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if ((cfg->dir == STEDMA40_PERIPH_TO_MEM) ||
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(cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
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/* Set master port to 1 */
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src |= 1 << D40_SREG_CFG_MST_POS;
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src |= D40_TYPE_TO_EVENT(cfg->src_dev_type);
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if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
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src |= 1 << D40_SREG_CFG_PHY_TM_POS;
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else
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src |= 3 << D40_SREG_CFG_PHY_TM_POS;
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}
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if ((cfg->dir == STEDMA40_MEM_TO_PERIPH) ||
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(cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
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/* Set master port to 1 */
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dst |= 1 << D40_SREG_CFG_MST_POS;
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dst |= D40_TYPE_TO_EVENT(cfg->dst_dev_type);
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if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
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dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
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else
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dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
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}
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/* Interrupt on end of transfer for destination */
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dst |= 1 << D40_SREG_CFG_TIM_POS;
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/* Generate interrupt on error */
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src |= 1 << D40_SREG_CFG_EIM_POS;
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dst |= 1 << D40_SREG_CFG_EIM_POS;
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/* PSIZE */
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if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
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src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
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src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
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}
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if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
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dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
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dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
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}
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/* Element size */
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src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
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dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
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} else {
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/* Logical channel */
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dst |= 1 << D40_SREG_CFG_LOG_GIM_POS;
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src |= 1 << D40_SREG_CFG_LOG_GIM_POS;
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}
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if (cfg->channel_type & STEDMA40_HIGH_PRIORITY_CHANNEL) {
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src |= 1 << D40_SREG_CFG_PRI_POS;
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dst |= 1 << D40_SREG_CFG_PRI_POS;
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}
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src |= cfg->src_info.endianess << D40_SREG_CFG_LBE_POS;
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dst |= cfg->dst_info.endianess << D40_SREG_CFG_LBE_POS;
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*src_cfg = src;
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*dst_cfg = dst;
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}
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int d40_phy_fill_lli(struct d40_phy_lli *lli,
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dma_addr_t data,
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u32 data_size,
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int psize,
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dma_addr_t next_lli,
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u32 reg_cfg,
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bool term_int,
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u32 data_width,
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bool is_device)
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{
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int num_elems;
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if (psize == STEDMA40_PSIZE_PHY_1)
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num_elems = 1;
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else
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num_elems = 2 << psize;
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/*
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* Size is 16bit. data_width is 8, 16, 32 or 64 bit
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* Block large than 64 KiB must be split.
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*/
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if (data_size > (0xffff << data_width))
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return -EINVAL;
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/* Must be aligned */
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if (!IS_ALIGNED(data, 0x1 << data_width))
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return -EINVAL;
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/* Transfer size can't be smaller than (num_elms * elem_size) */
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if (data_size < num_elems * (0x1 << data_width))
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return -EINVAL;
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/* The number of elements. IE now many chunks */
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lli->reg_elt = (data_size >> data_width) << D40_SREG_ELEM_PHY_ECNT_POS;
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/*
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* Distance to next element sized entry.
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* Usually the size of the element unless you want gaps.
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*/
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if (!is_device)
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lli->reg_elt |= (0x1 << data_width) <<
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D40_SREG_ELEM_PHY_EIDX_POS;
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/* Where the data is */
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lli->reg_ptr = data;
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lli->reg_cfg = reg_cfg;
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/* If this scatter list entry is the last one, no next link */
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if (next_lli == 0)
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lli->reg_lnk = 0x1 << D40_SREG_LNK_PHY_TCP_POS;
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else
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lli->reg_lnk = next_lli;
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/* Set/clear interrupt generation on this link item.*/
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if (term_int)
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lli->reg_cfg |= 0x1 << D40_SREG_CFG_TIM_POS;
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else
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lli->reg_cfg &= ~(0x1 << D40_SREG_CFG_TIM_POS);
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/* Post link */
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lli->reg_lnk |= 0 << D40_SREG_LNK_PHY_PRE_POS;
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return 0;
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}
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int d40_phy_sg_to_lli(struct scatterlist *sg,
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int sg_len,
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dma_addr_t target,
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struct d40_phy_lli *lli,
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dma_addr_t lli_phys,
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u32 reg_cfg,
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u32 data_width,
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int psize,
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bool term_int)
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{
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int total_size = 0;
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int i;
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struct scatterlist *current_sg = sg;
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dma_addr_t next_lli_phys;
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dma_addr_t dst;
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int err = 0;
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for_each_sg(sg, current_sg, sg_len, i) {
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total_size += sg_dma_len(current_sg);
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/* If this scatter list entry is the last one, no next link */
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if (sg_len - 1 == i)
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next_lli_phys = 0;
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else
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next_lli_phys = ALIGN(lli_phys + (i + 1) *
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sizeof(struct d40_phy_lli),
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D40_LLI_ALIGN);
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if (target)
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dst = target;
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else
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dst = sg_phys(current_sg);
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err = d40_phy_fill_lli(&lli[i],
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dst,
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sg_dma_len(current_sg),
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psize,
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next_lli_phys,
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reg_cfg,
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!next_lli_phys,
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data_width,
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target == dst);
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if (err)
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goto err;
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}
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return total_size;
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err:
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return err;
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}
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void d40_phy_lli_write(void __iomem *virtbase,
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u32 phy_chan_num,
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struct d40_phy_lli *lli_dst,
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struct d40_phy_lli *lli_src)
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{
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writel(lli_src->reg_cfg, virtbase + D40_DREG_PCBASE +
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phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSCFG);
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writel(lli_src->reg_elt, virtbase + D40_DREG_PCBASE +
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phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSELT);
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writel(lli_src->reg_ptr, virtbase + D40_DREG_PCBASE +
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phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSPTR);
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writel(lli_src->reg_lnk, virtbase + D40_DREG_PCBASE +
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phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSLNK);
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writel(lli_dst->reg_cfg, virtbase + D40_DREG_PCBASE +
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phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDCFG);
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writel(lli_dst->reg_elt, virtbase + D40_DREG_PCBASE +
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phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDELT);
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writel(lli_dst->reg_ptr, virtbase + D40_DREG_PCBASE +
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phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDPTR);
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writel(lli_dst->reg_lnk, virtbase + D40_DREG_PCBASE +
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phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDLNK);
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}
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/* DMA logical lli operations */
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void d40_log_fill_lli(struct d40_log_lli *lli,
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dma_addr_t data, u32 data_size,
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u32 lli_next_off, u32 reg_cfg,
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u32 data_width,
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bool term_int, bool addr_inc)
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{
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lli->lcsp13 = reg_cfg;
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/* The number of elements to transfer */
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lli->lcsp02 = ((data_size >> data_width) <<
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D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;
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/* 16 LSBs address of the current element */
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lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK;
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/* 16 MSBs address of the current element */
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lli->lcsp13 |= data & D40_MEM_LCSP1_SPTR_MASK;
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if (addr_inc)
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lli->lcsp13 |= D40_MEM_LCSP1_SCFG_INCR_MASK;
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lli->lcsp13 |= D40_MEM_LCSP3_DTCP_MASK;
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/* If this scatter list entry is the last one, no next link */
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lli->lcsp13 |= (lli_next_off << D40_MEM_LCSP1_SLOS_POS) &
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D40_MEM_LCSP1_SLOS_MASK;
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if (term_int)
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lli->lcsp13 |= D40_MEM_LCSP1_SCFG_TIM_MASK;
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else
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lli->lcsp13 &= ~D40_MEM_LCSP1_SCFG_TIM_MASK;
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}
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int d40_log_sg_to_dev(struct d40_lcla_elem *lcla,
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struct scatterlist *sg,
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int sg_len,
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struct d40_log_lli_bidir *lli,
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struct d40_def_lcsp *lcsp,
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u32 src_data_width,
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u32 dst_data_width,
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enum dma_data_direction direction,
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bool term_int, dma_addr_t dev_addr, int max_len,
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int llis_per_log)
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{
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int total_size = 0;
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struct scatterlist *current_sg = sg;
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int i;
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u32 next_lli_off_dst;
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u32 next_lli_off_src;
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next_lli_off_src = 0;
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next_lli_off_dst = 0;
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for_each_sg(sg, current_sg, sg_len, i) {
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total_size += sg_dma_len(current_sg);
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/*
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* If this scatter list entry is the last one or
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* max length, terminate link.
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*/
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if (sg_len - 1 == i || ((i+1) % max_len == 0)) {
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next_lli_off_src = 0;
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next_lli_off_dst = 0;
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} else {
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if (next_lli_off_dst == 0 &&
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next_lli_off_src == 0) {
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/* The first lli will be at next_lli_off */
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next_lli_off_dst = (lcla->dst_id *
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llis_per_log + 1);
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next_lli_off_src = (lcla->src_id *
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llis_per_log + 1);
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} else {
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next_lli_off_dst++;
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next_lli_off_src++;
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}
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}
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if (direction == DMA_TO_DEVICE) {
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d40_log_fill_lli(&lli->src[i],
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sg_phys(current_sg),
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sg_dma_len(current_sg),
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next_lli_off_src,
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lcsp->lcsp1, src_data_width,
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term_int && !next_lli_off_src,
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true);
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d40_log_fill_lli(&lli->dst[i],
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dev_addr,
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sg_dma_len(current_sg),
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next_lli_off_dst,
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lcsp->lcsp3, dst_data_width,
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/* No next == terminal interrupt */
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term_int && !next_lli_off_dst,
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false);
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} else {
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d40_log_fill_lli(&lli->dst[i],
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sg_phys(current_sg),
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sg_dma_len(current_sg),
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next_lli_off_dst,
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lcsp->lcsp3, dst_data_width,
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/* No next == terminal interrupt */
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term_int && !next_lli_off_dst,
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true);
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d40_log_fill_lli(&lli->src[i],
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dev_addr,
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sg_dma_len(current_sg),
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next_lli_off_src,
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lcsp->lcsp1, src_data_width,
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term_int && !next_lli_off_src,
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false);
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}
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}
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return total_size;
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}
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int d40_log_sg_to_lli(int lcla_id,
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struct scatterlist *sg,
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int sg_len,
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struct d40_log_lli *lli_sg,
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u32 lcsp13, /* src or dst*/
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u32 data_width,
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bool term_int, int max_len, int llis_per_log)
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{
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int total_size = 0;
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struct scatterlist *current_sg = sg;
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int i;
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u32 next_lli_off = 0;
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|
||||
for_each_sg(sg, current_sg, sg_len, i) {
|
||||
total_size += sg_dma_len(current_sg);
|
||||
|
||||
/*
|
||||
* If this scatter list entry is the last one or
|
||||
* max length, terminate link.
|
||||
*/
|
||||
if (sg_len - 1 == i || ((i+1) % max_len == 0))
|
||||
next_lli_off = 0;
|
||||
else {
|
||||
if (next_lli_off == 0)
|
||||
/* The first lli will be at next_lli_off */
|
||||
next_lli_off = lcla_id * llis_per_log + 1;
|
||||
else
|
||||
next_lli_off++;
|
||||
}
|
||||
|
||||
d40_log_fill_lli(&lli_sg[i],
|
||||
sg_phys(current_sg),
|
||||
sg_dma_len(current_sg),
|
||||
next_lli_off,
|
||||
lcsp13, data_width,
|
||||
term_int && !next_lli_off,
|
||||
true);
|
||||
}
|
||||
return total_size;
|
||||
}
|
||||
|
||||
void d40_log_lli_write(struct d40_log_lli_full *lcpa,
|
||||
struct d40_log_lli *lcla_src,
|
||||
struct d40_log_lli *lcla_dst,
|
||||
struct d40_log_lli *lli_dst,
|
||||
struct d40_log_lli *lli_src,
|
||||
int llis_per_log)
|
||||
{
|
||||
u32 slos = 0;
|
||||
u32 dlos = 0;
|
||||
int i;
|
||||
|
||||
lcpa->lcsp0 = lli_src->lcsp02;
|
||||
lcpa->lcsp1 = lli_src->lcsp13;
|
||||
lcpa->lcsp2 = lli_dst->lcsp02;
|
||||
lcpa->lcsp3 = lli_dst->lcsp13;
|
||||
|
||||
slos = lli_src->lcsp13 & D40_MEM_LCSP1_SLOS_MASK;
|
||||
dlos = lli_dst->lcsp13 & D40_MEM_LCSP3_DLOS_MASK;
|
||||
|
||||
for (i = 0; (i < llis_per_log) && slos && dlos; i++) {
|
||||
writel(lli_src[i+1].lcsp02, &lcla_src[i].lcsp02);
|
||||
writel(lli_src[i+1].lcsp13, &lcla_src[i].lcsp13);
|
||||
writel(lli_dst[i+1].lcsp02, &lcla_dst[i].lcsp02);
|
||||
writel(lli_dst[i+1].lcsp13, &lcla_dst[i].lcsp13);
|
||||
|
||||
slos = lli_src[i+1].lcsp13 & D40_MEM_LCSP1_SLOS_MASK;
|
||||
dlos = lli_dst[i+1].lcsp13 & D40_MEM_LCSP3_DLOS_MASK;
|
||||
}
|
||||
}
|
||||
354
drivers/dma/ste_dma40_ll.h
Normal file
354
drivers/dma/ste_dma40_ll.h
Normal file
|
|
@ -0,0 +1,354 @@
|
|||
/*
|
||||
* driver/dma/ste_dma40_ll.h
|
||||
*
|
||||
* Copyright (C) ST-Ericsson 2007-2010
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
* Author: Per Friden <per.friden@stericsson.com>
|
||||
* Author: Jonas Aaberg <jonas.aberg@stericsson.com>
|
||||
*/
|
||||
#ifndef STE_DMA40_LL_H
|
||||
#define STE_DMA40_LL_H
|
||||
|
||||
#define D40_DREG_PCBASE 0x400
|
||||
#define D40_DREG_PCDELTA (8 * 4)
|
||||
#define D40_LLI_ALIGN 16 /* LLI alignment must be 16 bytes. */
|
||||
|
||||
#define D40_TYPE_TO_GROUP(type) (type / 16)
|
||||
#define D40_TYPE_TO_EVENT(type) (type % 16)
|
||||
|
||||
/* Most bits of the CFG register are the same in log as in phy mode */
|
||||
#define D40_SREG_CFG_MST_POS 15
|
||||
#define D40_SREG_CFG_TIM_POS 14
|
||||
#define D40_SREG_CFG_EIM_POS 13
|
||||
#define D40_SREG_CFG_LOG_INCR_POS 12
|
||||
#define D40_SREG_CFG_PHY_PEN_POS 12
|
||||
#define D40_SREG_CFG_PSIZE_POS 10
|
||||
#define D40_SREG_CFG_ESIZE_POS 8
|
||||
#define D40_SREG_CFG_PRI_POS 7
|
||||
#define D40_SREG_CFG_LBE_POS 6
|
||||
#define D40_SREG_CFG_LOG_GIM_POS 5
|
||||
#define D40_SREG_CFG_LOG_MFU_POS 4
|
||||
#define D40_SREG_CFG_PHY_TM_POS 4
|
||||
#define D40_SREG_CFG_PHY_EVTL_POS 0
|
||||
|
||||
|
||||
/* Standard channel parameters - basic mode (element register) */
|
||||
#define D40_SREG_ELEM_PHY_ECNT_POS 16
|
||||
#define D40_SREG_ELEM_PHY_EIDX_POS 0
|
||||
|
||||
#define D40_SREG_ELEM_PHY_ECNT_MASK (0xFFFF << D40_SREG_ELEM_PHY_ECNT_POS)
|
||||
|
||||
/* Standard channel parameters - basic mode (Link register) */
|
||||
#define D40_SREG_LNK_PHY_TCP_POS 0
|
||||
#define D40_SREG_LNK_PHY_LMP_POS 1
|
||||
#define D40_SREG_LNK_PHY_PRE_POS 2
|
||||
/*
|
||||
* Source destination link address. Contains the
|
||||
* 29-bit byte word aligned address of the reload area.
|
||||
*/
|
||||
#define D40_SREG_LNK_PHYS_LNK_MASK 0xFFFFFFF8UL
|
||||
|
||||
/* Standard basic channel logical mode */
|
||||
|
||||
/* Element register */
|
||||
#define D40_SREG_ELEM_LOG_ECNT_POS 16
|
||||
#define D40_SREG_ELEM_LOG_LIDX_POS 8
|
||||
#define D40_SREG_ELEM_LOG_LOS_POS 1
|
||||
#define D40_SREG_ELEM_LOG_TCP_POS 0
|
||||
|
||||
#define D40_SREG_ELEM_LOG_LIDX_MASK (0xFF << D40_SREG_ELEM_LOG_LIDX_POS)
|
||||
|
||||
/* Link register */
|
||||
#define D40_DEACTIVATE_EVENTLINE 0x0
|
||||
#define D40_ACTIVATE_EVENTLINE 0x1
|
||||
#define D40_EVENTLINE_POS(i) (2 * i)
|
||||
#define D40_EVENTLINE_MASK(i) (0x3 << D40_EVENTLINE_POS(i))
|
||||
|
||||
/* Standard basic channel logical params in memory */
|
||||
|
||||
/* LCSP0 */
|
||||
#define D40_MEM_LCSP0_ECNT_POS 16
|
||||
#define D40_MEM_LCSP0_SPTR_POS 0
|
||||
|
||||
#define D40_MEM_LCSP0_ECNT_MASK (0xFFFF << D40_MEM_LCSP0_ECNT_POS)
|
||||
#define D40_MEM_LCSP0_SPTR_MASK (0xFFFF << D40_MEM_LCSP0_SPTR_POS)
|
||||
|
||||
/* LCSP1 */
|
||||
#define D40_MEM_LCSP1_SPTR_POS 16
|
||||
#define D40_MEM_LCSP1_SCFG_MST_POS 15
|
||||
#define D40_MEM_LCSP1_SCFG_TIM_POS 14
|
||||
#define D40_MEM_LCSP1_SCFG_EIM_POS 13
|
||||
#define D40_MEM_LCSP1_SCFG_INCR_POS 12
|
||||
#define D40_MEM_LCSP1_SCFG_PSIZE_POS 10
|
||||
#define D40_MEM_LCSP1_SCFG_ESIZE_POS 8
|
||||
#define D40_MEM_LCSP1_SLOS_POS 1
|
||||
#define D40_MEM_LCSP1_STCP_POS 0
|
||||
|
||||
#define D40_MEM_LCSP1_SPTR_MASK (0xFFFF << D40_MEM_LCSP1_SPTR_POS)
|
||||
#define D40_MEM_LCSP1_SCFG_TIM_MASK (0x1 << D40_MEM_LCSP1_SCFG_TIM_POS)
|
||||
#define D40_MEM_LCSP1_SCFG_INCR_MASK (0x1 << D40_MEM_LCSP1_SCFG_INCR_POS)
|
||||
#define D40_MEM_LCSP1_SCFG_PSIZE_MASK (0x3 << D40_MEM_LCSP1_SCFG_PSIZE_POS)
|
||||
#define D40_MEM_LCSP1_SLOS_MASK (0x7F << D40_MEM_LCSP1_SLOS_POS)
|
||||
#define D40_MEM_LCSP1_STCP_MASK (0x1 << D40_MEM_LCSP1_STCP_POS)
|
||||
|
||||
/* LCSP2 */
|
||||
#define D40_MEM_LCSP2_ECNT_POS 16
|
||||
|
||||
#define D40_MEM_LCSP2_ECNT_MASK (0xFFFF << D40_MEM_LCSP2_ECNT_POS)
|
||||
|
||||
/* LCSP3 */
|
||||
#define D40_MEM_LCSP3_DCFG_MST_POS 15
|
||||
#define D40_MEM_LCSP3_DCFG_TIM_POS 14
|
||||
#define D40_MEM_LCSP3_DCFG_EIM_POS 13
|
||||
#define D40_MEM_LCSP3_DCFG_INCR_POS 12
|
||||
#define D40_MEM_LCSP3_DCFG_PSIZE_POS 10
|
||||
#define D40_MEM_LCSP3_DCFG_ESIZE_POS 8
|
||||
#define D40_MEM_LCSP3_DLOS_POS 1
|
||||
#define D40_MEM_LCSP3_DTCP_POS 0
|
||||
|
||||
#define D40_MEM_LCSP3_DLOS_MASK (0x7F << D40_MEM_LCSP3_DLOS_POS)
|
||||
#define D40_MEM_LCSP3_DTCP_MASK (0x1 << D40_MEM_LCSP3_DTCP_POS)
|
||||
|
||||
|
||||
/* Standard channel parameter register offsets */
|
||||
#define D40_CHAN_REG_SSCFG 0x00
|
||||
#define D40_CHAN_REG_SSELT 0x04
|
||||
#define D40_CHAN_REG_SSPTR 0x08
|
||||
#define D40_CHAN_REG_SSLNK 0x0C
|
||||
#define D40_CHAN_REG_SDCFG 0x10
|
||||
#define D40_CHAN_REG_SDELT 0x14
|
||||
#define D40_CHAN_REG_SDPTR 0x18
|
||||
#define D40_CHAN_REG_SDLNK 0x1C
|
||||
|
||||
/* DMA Register Offsets */
|
||||
#define D40_DREG_GCC 0x000
|
||||
#define D40_DREG_PRTYP 0x004
|
||||
#define D40_DREG_PRSME 0x008
|
||||
#define D40_DREG_PRSMO 0x00C
|
||||
#define D40_DREG_PRMSE 0x010
|
||||
#define D40_DREG_PRMSO 0x014
|
||||
#define D40_DREG_PRMOE 0x018
|
||||
#define D40_DREG_PRMOO 0x01C
|
||||
#define D40_DREG_LCPA 0x020
|
||||
#define D40_DREG_LCLA 0x024
|
||||
#define D40_DREG_ACTIVE 0x050
|
||||
#define D40_DREG_ACTIVO 0x054
|
||||
#define D40_DREG_FSEB1 0x058
|
||||
#define D40_DREG_FSEB2 0x05C
|
||||
#define D40_DREG_PCMIS 0x060
|
||||
#define D40_DREG_PCICR 0x064
|
||||
#define D40_DREG_PCTIS 0x068
|
||||
#define D40_DREG_PCEIS 0x06C
|
||||
#define D40_DREG_LCMIS0 0x080
|
||||
#define D40_DREG_LCMIS1 0x084
|
||||
#define D40_DREG_LCMIS2 0x088
|
||||
#define D40_DREG_LCMIS3 0x08C
|
||||
#define D40_DREG_LCICR0 0x090
|
||||
#define D40_DREG_LCICR1 0x094
|
||||
#define D40_DREG_LCICR2 0x098
|
||||
#define D40_DREG_LCICR3 0x09C
|
||||
#define D40_DREG_LCTIS0 0x0A0
|
||||
#define D40_DREG_LCTIS1 0x0A4
|
||||
#define D40_DREG_LCTIS2 0x0A8
|
||||
#define D40_DREG_LCTIS3 0x0AC
|
||||
#define D40_DREG_LCEIS0 0x0B0
|
||||
#define D40_DREG_LCEIS1 0x0B4
|
||||
#define D40_DREG_LCEIS2 0x0B8
|
||||
#define D40_DREG_LCEIS3 0x0BC
|
||||
#define D40_DREG_STFU 0xFC8
|
||||
#define D40_DREG_ICFG 0xFCC
|
||||
#define D40_DREG_PERIPHID0 0xFE0
|
||||
#define D40_DREG_PERIPHID1 0xFE4
|
||||
#define D40_DREG_PERIPHID2 0xFE8
|
||||
#define D40_DREG_PERIPHID3 0xFEC
|
||||
#define D40_DREG_CELLID0 0xFF0
|
||||
#define D40_DREG_CELLID1 0xFF4
|
||||
#define D40_DREG_CELLID2 0xFF8
|
||||
#define D40_DREG_CELLID3 0xFFC
|
||||
|
||||
/* LLI related structures */
|
||||
|
||||
/**
|
||||
* struct d40_phy_lli - The basic configration register for each physical
|
||||
* channel.
|
||||
*
|
||||
* @reg_cfg: The configuration register.
|
||||
* @reg_elt: The element register.
|
||||
* @reg_ptr: The pointer register.
|
||||
* @reg_lnk: The link register.
|
||||
*
|
||||
* These registers are set up for both physical and logical transfers
|
||||
* Note that the bit in each register means differently in logical and
|
||||
* physical(standard) mode.
|
||||
*
|
||||
* This struct must be 16 bytes aligned, and only contain physical registers
|
||||
* since it will be directly accessed by the DMA.
|
||||
*/
|
||||
struct d40_phy_lli {
|
||||
u32 reg_cfg;
|
||||
u32 reg_elt;
|
||||
u32 reg_ptr;
|
||||
u32 reg_lnk;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct d40_phy_lli_bidir - struct for a transfer.
|
||||
*
|
||||
* @src: Register settings for src channel.
|
||||
* @dst: Register settings for dst channel.
|
||||
* @dst_addr: Physical destination address.
|
||||
* @src_addr: Physical source address.
|
||||
*
|
||||
* All DMA transfers have a source and a destination.
|
||||
*/
|
||||
|
||||
struct d40_phy_lli_bidir {
|
||||
struct d40_phy_lli *src;
|
||||
struct d40_phy_lli *dst;
|
||||
dma_addr_t dst_addr;
|
||||
dma_addr_t src_addr;
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* struct d40_log_lli - logical lli configuration
|
||||
*
|
||||
* @lcsp02: Either maps to register lcsp0 if src or lcsp2 if dst.
|
||||
* @lcsp13: Either maps to register lcsp1 if src or lcsp3 if dst.
|
||||
*
|
||||
* This struct must be 8 bytes aligned since it will be accessed directy by
|
||||
* the DMA. Never add any none hw mapped registers to this struct.
|
||||
*/
|
||||
|
||||
struct d40_log_lli {
|
||||
u32 lcsp02;
|
||||
u32 lcsp13;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct d40_log_lli_bidir - For both src and dst
|
||||
*
|
||||
* @src: pointer to src lli configuration.
|
||||
* @dst: pointer to dst lli configuration.
|
||||
*
|
||||
* You always have a src and a dst when doing DMA transfers.
|
||||
*/
|
||||
|
||||
struct d40_log_lli_bidir {
|
||||
struct d40_log_lli *src;
|
||||
struct d40_log_lli *dst;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct d40_log_lli_full - LCPA layout
|
||||
*
|
||||
* @lcsp0: Logical Channel Standard Param 0 - Src.
|
||||
* @lcsp1: Logical Channel Standard Param 1 - Src.
|
||||
* @lcsp2: Logical Channel Standard Param 2 - Dst.
|
||||
* @lcsp3: Logical Channel Standard Param 3 - Dst.
|
||||
*
|
||||
* This struct maps to LCPA physical memory layout. Must map to
|
||||
* the hw.
|
||||
*/
|
||||
struct d40_log_lli_full {
|
||||
u32 lcsp0;
|
||||
u32 lcsp1;
|
||||
u32 lcsp2;
|
||||
u32 lcsp3;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct d40_def_lcsp - Default LCSP1 and LCSP3 settings
|
||||
*
|
||||
* @lcsp3: The default configuration for dst.
|
||||
* @lcsp1: The default configuration for src.
|
||||
*/
|
||||
struct d40_def_lcsp {
|
||||
u32 lcsp3;
|
||||
u32 lcsp1;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct d40_lcla_elem - Info for one LCA element.
|
||||
*
|
||||
* @src_id: logical channel src id
|
||||
* @dst_id: logical channel dst id
|
||||
* @src: LCPA formated src parameters
|
||||
* @dst: LCPA formated dst parameters
|
||||
*
|
||||
*/
|
||||
struct d40_lcla_elem {
|
||||
int src_id;
|
||||
int dst_id;
|
||||
struct d40_log_lli *src;
|
||||
struct d40_log_lli *dst;
|
||||
};
|
||||
|
||||
/* Physical channels */
|
||||
|
||||
void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
|
||||
u32 *src_cfg, u32 *dst_cfg, bool is_log);
|
||||
|
||||
void d40_log_cfg(struct stedma40_chan_cfg *cfg,
|
||||
u32 *lcsp1, u32 *lcsp2);
|
||||
|
||||
int d40_phy_sg_to_lli(struct scatterlist *sg,
|
||||
int sg_len,
|
||||
dma_addr_t target,
|
||||
struct d40_phy_lli *lli,
|
||||
dma_addr_t lli_phys,
|
||||
u32 reg_cfg,
|
||||
u32 data_width,
|
||||
int psize,
|
||||
bool term_int);
|
||||
|
||||
int d40_phy_fill_lli(struct d40_phy_lli *lli,
|
||||
dma_addr_t data,
|
||||
u32 data_size,
|
||||
int psize,
|
||||
dma_addr_t next_lli,
|
||||
u32 reg_cfg,
|
||||
bool term_int,
|
||||
u32 data_width,
|
||||
bool is_device);
|
||||
|
||||
void d40_phy_lli_write(void __iomem *virtbase,
|
||||
u32 phy_chan_num,
|
||||
struct d40_phy_lli *lli_dst,
|
||||
struct d40_phy_lli *lli_src);
|
||||
|
||||
/* Logical channels */
|
||||
|
||||
void d40_log_fill_lli(struct d40_log_lli *lli,
|
||||
dma_addr_t data, u32 data_size,
|
||||
u32 lli_next_off, u32 reg_cfg,
|
||||
u32 data_width,
|
||||
bool term_int, bool addr_inc);
|
||||
|
||||
int d40_log_sg_to_dev(struct d40_lcla_elem *lcla,
|
||||
struct scatterlist *sg,
|
||||
int sg_len,
|
||||
struct d40_log_lli_bidir *lli,
|
||||
struct d40_def_lcsp *lcsp,
|
||||
u32 src_data_width,
|
||||
u32 dst_data_width,
|
||||
enum dma_data_direction direction,
|
||||
bool term_int, dma_addr_t dev_addr, int max_len,
|
||||
int llis_per_log);
|
||||
|
||||
void d40_log_lli_write(struct d40_log_lli_full *lcpa,
|
||||
struct d40_log_lli *lcla_src,
|
||||
struct d40_log_lli *lcla_dst,
|
||||
struct d40_log_lli *lli_dst,
|
||||
struct d40_log_lli *lli_src,
|
||||
int llis_per_log);
|
||||
|
||||
int d40_log_sg_to_lli(int lcla_id,
|
||||
struct scatterlist *sg,
|
||||
int sg_len,
|
||||
struct d40_log_lli *lli_sg,
|
||||
u32 lcsp13, /* src or dst*/
|
||||
u32 data_width,
|
||||
bool term_int, int max_len, int llis_per_log);
|
||||
|
||||
#endif /* STE_DMA40_LLI_H */
|
||||
Loading…
Reference in a new issue