diff --git a/bindings/arm/coresight.txt b/bindings/arm/coresight.txt index f5ad2bb1e981..1fadc1b562cc 100644 --- a/bindings/arm/coresight.txt +++ b/bindings/arm/coresight.txt @@ -137,9 +137,10 @@ its hardware characteristcs. * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely use the SG mode on this system. -* Optional property for CATU : +* Optional property for CATU and APSS : * interrupts : Exactly one SPI may be listed for reporting the address - error + error for CATU and four interrupts for TGU to get trigger from four + type of events. * Required property for TPDAs: @@ -480,6 +481,10 @@ Example: tgu-conditions = <4>; tgu-regs = <4>; tgu-timer-counters = <8>; + interrupts = , + , + , + ; coresight-name = "coresight-tgu-ipcb"; diff --git a/bindings/arm/msm/hh_watchdog.yaml b/bindings/arm/msm/hh_watchdog.yaml new file mode 100644 index 000000000000..469eab1c846c --- /dev/null +++ b/bindings/arm/msm/hh_watchdog.yaml @@ -0,0 +1,39 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/msm/hh_watchdog.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QTI HH Watchdog + +maintainers: + +description: |+ + Watchdog timer is configured with a bark and a bite time. + If the watchdog is not "pet" at regular intervals, the system + is assumed to have become non responsive and needs to be reset. + A warning in the form of a bark timeout leads to a bark interrupt + and a kernel panic. If the watchdog timer is still not reset, + a bite timeout occurs, which leads to a reset of the VM via + the hypervisor. The driver needs the petting time, and the bark + timeout to be programmed into the watchdog, as well as the bark irq. + + The device tree parameters for the watchdog are: + +properties: + compatible: + Usage: required + Value type: + Definition: Must be "qcom,hh-watchdog" + + interrupts: + Usage: required + Value type: + Definition: should contain the bark irq number + +example: + - | + wdog_hh: qcom,wdt_hh { + compatible = "qcom,hh-watchdog"; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; + }; +... diff --git a/bindings/arm/msm/imem.yaml b/bindings/arm/msm/imem.yaml index 171c12de31ac..d2b35b030fc3 100644 --- a/bindings/arm/msm/imem.yaml +++ b/bindings/arm/msm/imem.yaml @@ -69,6 +69,9 @@ patternProperties: - const: qcom,msm-imem-diag-dload description: USB Diag download mode region + - const: qcom,msm-imem-pil-disable-timeout + description: Offset to set PIL debug cookie + reg: description: Start address and the size of the region diff --git a/bindings/arm/msm/lpm-levels.txt b/bindings/arm/msm/lpm-levels.txt index fa5709dd7c4a..421ba2a366d0 100644 --- a/bindings/arm/msm/lpm-levels.txt +++ b/bindings/arm/msm/lpm-levels.txt @@ -29,6 +29,7 @@ Required properties: Optional properties: - reg: The address range + - reg-names: Specifies the address field names. - qcom,disable-prediction: This property is used to indicate the LPM governor will not use LPM prediction for this cluster. - qcom,clstr-tmr-add: This property is used as correction timer for @@ -86,6 +87,8 @@ that share the parameters.It contains the following properties. Optional properties: - qcom,disable-prediction: This property is used to indicate the LPM governor is to disable sleep prediction to this cpu. + - label: Identifies the cluster name. The name is used when parsing the + RIMPS addresses. - qcom,ref-stddev: This property is used as reference standard deviation in lpm prediction algorithm. This value should be between 100 to 1000. Higher value would result in more predictions and thereby resulting in diff --git a/bindings/arm/msm/msm_watchdog.yaml b/bindings/arm/msm/msm_watchdog.yaml index 8309dacc5508..186d67e1c931 100644 --- a/bindings/arm/msm/msm_watchdog.yaml +++ b/bindings/arm/msm/msm_watchdog.yaml @@ -44,35 +44,6 @@ properties: Value type: Definition: should contain bark and bite irq numbers - qcom,pet-time: - Usage: required - Value type: - Definition: Non zero time interval at which watchdog should be pet in ms. - - qcom,bark-time: - Usage: required - Value type: - Definition: Non zero timeout value for a watchdog bark in ms. - - qcom,userspace-watchdog: - Usage: optional - Value type: - Definition: Allow enabling the userspace-watchdog feature. This feature - requires userspace to pet the watchdog every qcom,pet-time interval - in addition to the existing kernel-level checks. - This feature is supported through device sysfs files. - - qcom,ipi-ping: - Usage: optional - Value type: - Definition: send keep alive ping to other cpus if present - - qcom,wakeup-enable: - Usage: optional - Value type: - Definition: enable non secure watchdog to freeze / unfreeze - automatically across suspend / resume path. - example: - | wdog: qcom,wdt@17c10000{ @@ -81,9 +52,5 @@ example: reg-names = "wdt-base"; interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, <0 1 IRQ_TYPE_LEVEL_HIGH>; - qcom,bark-time = <11000>; - qcom,pet-time = <9360>; - qcom,ipi-ping; - qcom,wakeup-enable; }; ... diff --git a/bindings/arm/msm/qcom,llcc.txt b/bindings/arm/msm/qcom,llcc.txt index 4e9c4d83be5b..9d722dcf4c72 100644 --- a/bindings/arm/msm/qcom,llcc.txt +++ b/bindings/arm/msm/qcom,llcc.txt @@ -12,7 +12,7 @@ Properties: Usage: required Value type: Definition: must be "qcom,sdm845-llcc" or "qcom,lahaina-llcc" - or "qcom,shima-llcc". + or "qcom,shima-llcc" or "qcom,sdxlemur-llcc" "qcom,llcc-v2" must be appended for V2 hardware. - reg: diff --git a/bindings/cpufreq/cpufreq-qcom-hw.txt b/bindings/cpufreq/cpufreq-qcom-hw.txt index 5a3f126df530..251ea7dcca40 100644 --- a/bindings/cpufreq/cpufreq-qcom-hw.txt +++ b/bindings/cpufreq/cpufreq-qcom-hw.txt @@ -42,6 +42,14 @@ Properties: Definition: Indicate to check for Enable of FW before registering with cpufreq. +- qcom,perf-lock-support + Usage: Optional + Value type: bool + Definition: Indicate to check for performance lock support in FW. + In case this property is present, the reg & reg-names + should have the "pdmem-domainX" to indicate the + corresponding bases. + * Property qcom,freq-domain Devices supporting freq-domain must set their "qcom,freq-domain" property with phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node. diff --git a/bindings/interconnect/qcom,cpucp-l3.txt b/bindings/interconnect/qcom,cpucp-l3.txt new file mode 100644 index 000000000000..9fc668ce80de --- /dev/null +++ b/bindings/interconnect/qcom,cpucp-l3.txt @@ -0,0 +1,35 @@ +Qualcomm Technologies, Inc. CPUCP L3 interconnect driver binding +----------------------------------------------------------- + +The CPUCP L3 Interconnect provider supports the scaling of L3 cache +performance states of the CPU subsystem. + +Required properties : +- compatible : shall contain only one of the following: + "qcom,holi-cpucp-l3-shared", + "qcom,holi-cpucp-l3-cpu"; +- reg : Address and length of the register set for the device +- clock-names: should contain "xo", "alternate" +- clocks: list of phandle and clock specifier pairs corresponding to + entries in the clock-names property. +- #interconnect-cells : should contain 1 + +Examples: + +cpucp_l3_shared: l3_shared@fd90000 { + reg = <0x0fd90000 0x3000>; + compatible = "qcom,holi-cpucp-l3-shared"; + #interconnect-cells = <1>; + clock-names = "xo", "alternate"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPLL0>; +}; + +cpucp_l3_cpu: l3_cpu@fd90000{ + reg = <0x0fd90000 0x3000>; + compatible = "qcom,holi-cpucp-l3-cpu"; + #interconnect-cells = <1>; + clock-names = "xo", "alternate"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPLL0>; +}; diff --git a/bindings/interconnect/qcom,epss-l3.txt b/bindings/interconnect/qcom,epss-l3.txt index 1ce85c18cdea..8bd41c0a753e 100644 --- a/bindings/interconnect/qcom,epss-l3.txt +++ b/bindings/interconnect/qcom,epss-l3.txt @@ -8,7 +8,6 @@ Required properties : - compatible : shall contain only one of the following: "qcom,lahaina-epss-l3-shared", "qcom,lahaina-epss-l3-cpu", - "qcom,holi-epss-l3-cpu", "qcom,shima-epss-l3-cpu", "qcom,shima-epss-l3-shared"; - reg : Address and length of the register set for the device diff --git a/bindings/interconnect/qcom,holi.txt b/bindings/interconnect/qcom,holi.txt index fd3e2dc116d8..262c285a12f0 100644 --- a/bindings/interconnect/qcom,holi.txt +++ b/bindings/interconnect/qcom,holi.txt @@ -15,6 +15,12 @@ reg : specifies the physical base address and size of registers clocks : list of phandles and specifiers to all interconnect bus clocks clock-names : clock names should include both "bus" and "bus_a" +The following are optional properties: + +qcom,util-factor : Parameter that represents the DDR utilization factor + to be used in aggregation scheme. It is represented as + actual util-factor * 100. + Examples: soc { @@ -22,6 +28,7 @@ soc { system_noc: interconnect@1880000 { reg = <0x1880000 0x5f080>; compatible = "qcom,holi-system_noc"; + qcom,util-factor = <142>; #interconnect-cells = <1>; clock-names = "bus", "bus_a"; clocks = <&rpmcc RPM_SMD_SNOC_CLK>, diff --git a/bindings/pinctrl/qcom,pmic-gpio.txt b/bindings/pinctrl/qcom,pmic-gpio.txt index 5642ef00c17c..d506c20b8a13 100644 --- a/bindings/pinctrl/qcom,pmic-gpio.txt +++ b/bindings/pinctrl/qcom,pmic-gpio.txt @@ -32,6 +32,7 @@ PMIC's from Qualcomm. "qcom,pm7250b-gpio" "qcom,pm6350-gpio" "qcom,pm6150l-gpio" + "qcom,pmx65-gpio" And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio" if the device is on an spmi bus or an ssbi bus respectively @@ -118,6 +119,7 @@ to specify in a pin configuration subnode: gpio1-gpio12 for pm7250b gpio1-gpio9 for pm6350 gpio1-gpio12 for pm6150l + gpio1-gpio16 for pmx65 - function: Usage: required diff --git a/bindings/power/supply/qcom/qpnp-qg.txt b/bindings/power/supply/qcom/qpnp-qg.txt index f095303c1e2f..45be8ad5cecc 100644 --- a/bindings/power/supply/qcom/qpnp-qg.txt +++ b/bindings/power/supply/qcom/qpnp-qg.txt @@ -19,13 +19,20 @@ First Level Node - QGAUGE device - compatible Usage: required Value type: - Definition: Should be "qcom,qpnp-qg" or "qcom,qpnp-qg-lite". + Definition: Should be "qcom,qpnp-qg-lite" for PM2250. + Should be "qcom,pm6150-qg" for PM6150. + Should be "qcom,pmi632-qg" for PMI632. + Should be "qcom,pm7250b-qg" for PM7250B. -- qcom,pmic-revid +- io-channels Usage: required - Value type: - Definition: Should specify the phandle of PMIC revid module. This is - used to identify the PMIC subtype. + Value type: + Definition: IIO channel specifiers for each name in io-channel-names. + +- io-channel-names + Usage: required + Value type: + Definition: Names of the IIO channels that are used by QG device. - qcom,qg-vadc Usage: required @@ -473,13 +480,17 @@ Example ======== pmi632_qg: qpnp,qg { - compatible = "qcom,qpnp-qg"; - qcom,pmic-revid = <&pmi632_revid>; + compatible = "qcom,pm7250b-qg"; qcom,qg-vadc = <&pmi632_vadc>; qcom,vbatt-empty-mv = <3200>; qcom,vbatt-low-mv = <3500>; qcom,vbatt-cutoff-mv = <3400>; qcom,qg-iterm-ma = <100>; + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>; + io-channel-names = "recharge_soc", + "charge_done"; qcom,qgauge@4800 { status = "okay"; diff --git a/bindings/power/supply/qcom/qpnp-smb5.txt b/bindings/power/supply/qcom/qpnp-smb5.txt index 75db4740d612..3b20b0c427d2 100644 --- a/bindings/power/supply/qcom/qpnp-smb5.txt +++ b/bindings/power/supply/qcom/qpnp-smb5.txt @@ -19,13 +19,19 @@ Charger specific properties: - compatible Usage: required Value type: - Definition: "qcom,qpnp-smb5". + Definition: "qcom,pm8150-smb5" for SMB5 on PM8150. + "qcom,pm7250b-smb5" for SMB5 on PM7250B. + "qcom,pm6150-smb5" for SMB5 on PM6150. + "qcom,pmi632-smb5" for SMB5 on PMI632. -- qcom,pmic-revid - Usage: required - Value type: phandle - Definition: Should specify the phandle of PMI's revid module. This is used to - identify the PMI subtype. +- #io-channel-cells: + Usage: required + Value type: + Definition: Number of cells in an IIO specifier. + Needed to indicate other clients can query charger for + IIO channels. + For details about IIO bindings see: + Documentation/devicetree/bindings/iio/iio-bindings.txt - qcom,sec-charger-config Usage: optional @@ -419,8 +425,7 @@ pm8150b_charger: qcom,qpnp-smb5 { compatible = "qcom,qpnp-smb5"; #address-cells = <1>; #size-cells = <1>; - - qcom,pmic-revid = <&pm8150b_revid>; + #io-channel-cells = <1>; dpdm-supply = <&qusb_phy0>; @@ -428,10 +433,16 @@ pm8150b_charger: qcom,qpnp-smb5 { io-channels = <&pm8150b_vadc ADC_USB_IN_V_16>, <&pm8150b_vadc ADC_USB_IN_I>, - <&pm8150b_vadc ADC_CHG_TEMP>; + <&pm8150b_vadc ADC_CHG_TEMP>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>; io-channel-names = "usb_in_voltage", "usb_in_current", - "chg_temp"; + "chg_temp", + "resistance_id", + "charge_counter", + "charge_full"; qcom,chgr@1000 { reg = <0x1000 0x100>; diff --git a/bindings/soc/qcom/qcom,pmic-pon-log.txt b/bindings/soc/qcom/qcom,pmic-pon-log.txt new file mode 100644 index 000000000000..49dbcc5a5ec0 --- /dev/null +++ b/bindings/soc/qcom/qcom,pmic-pon-log.txt @@ -0,0 +1,28 @@ +Qualcomm Technologies, Inc. PMIC PON Log + +Certain Qualcomm Technologies, Inc. PMIC devices capture power-on, power-off, +and fault information in a binary log found within SDAM peripherals. The PMIC +PON Log device accesses this log and parses it into a human readable format. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,pmic-pon-log" + +- nvmem: + Usage: required + Value type: + Definition: phandle of the PMIC nvmem device containing the PON log + +- nvmem-names: + Usage: required + Value type: + Definition: must be "pon_log" + +Example: + +pmic-pon-log { + compatible = "qcom,pmic-pon-log"; + nvmem = <&pmk8350_sdam_5>; + nvmem-names = "pon_log"; +}; diff --git a/bindings/usb/qcom,dwc3.txt b/bindings/usb/qcom,dwc3.txt index 108a3e6518dc..cb695aa3fba4 100644 --- a/bindings/usb/qcom,dwc3.txt +++ b/bindings/usb/qcom,dwc3.txt @@ -23,9 +23,6 @@ Optional clocks: Not present on "qcom,msm8996-dwc3" compatible. "cfg_noc" System Config NOC clock. Not present on "qcom,msm8996-dwc3" compatible. - "core_csr" Allows to set/clear FORCE_MEM_CORE_ON with USB core - clock to retain USB controller CSR across system deep - sleep. - assigned-clocks: Should be: MOCK_UTMI_CLK MASTER_CLK diff --git a/bindings/usb/qpnp-pdphy.txt b/bindings/usb/qpnp-pdphy.txt new file mode 100644 index 000000000000..ebbb6d5b4770 --- /dev/null +++ b/bindings/usb/qpnp-pdphy.txt @@ -0,0 +1,71 @@ +Qualcomm Technologies, Inc. QPNP PD PHY - USB Power Delivery Physical layer + +Required properties: +- compatible: Must be "qcom,qpnp-pdphy" +- reg: The base address for this peripheral +- vdd-pdphy-supply: phandle to the VDD supply regulator node +- interrupts: Specifies the interrupt associated with the peripheral. +- interrupt-names: Specifies the interrupt names for the peripheral. Every + available interrupt needs to have an associated name + with it to indentify its purpose. + + The following interrupts are required: + + 0: sig-tx + Triggers when a signal (HardReset or CableReset) + has been sent. + 1: sig-rx + Triggers when a signal has been received. + 2: msg-tx + Triggers when a message has been sent and the + related GoodCRC has been received. + 3: msg-rx + Triggers when a message has been received and + the related GoodCRC was sent successfully. + 4: msg-tx-failed + Triggers when a message failed all its + transmission attempts, either due to a non-idle + bus or missing GoodCRC reply. + 5: msg-tx-discarded + Triggers when a message is received while a + transmission request was in place. The request + itself is discarded. + 6: msg-rx-discarded + Triggers when a message was received but had to + be discarded due to the RX buffer still in use + by SW. + +Optional properties: +- vbus-supply: Regulator that enables VBUS source output +- vconn-supply: Regulator that enables VCONN source output. This will + be supplied on the USB CC line that is not used for + communication when Ra resistance is detected. +- qcom,default-sink-caps: List of 32-bit values representing the nominal sink + capabilities in voltage (millivolts) and current + (milliamps) pairs. + +Example: + qcom,qpnp-pdphy@1700 { + compatible = "qcom,qpnp-pdphy"; + reg = <0x1700 0x100>; + vdd-pdphy-supply = <&pm8998_l24>; + interrupts = <0x2 0x17 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x4 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x5 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x6 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "sig-tx", + "sig-rx", + "msg-tx", + "msg-rx", + "msg-tx-failed", + "msg-tx-discarded", + "msg-rx-discarded"; + + qcom,default-sink-caps = <5000 3000>, /* 5V @ 3A */ + <9000 3000>, /* 9V @ 3A */ + <12000 2250>; /* 12V @ 2.25A */ + }; diff --git a/qcom/Makefile b/qcom/Makefile index a2a27d6845c3..a8abb1f7cdcd 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -141,7 +141,9 @@ endif ifeq ($(CONFIG_ARCH_LAHAINA), y) ifeq ($(CONFIG_ARCH_QTI_VM), y) -dtb-$(CONFIG_ARCH_QTI_VM) += trustedvm.dtb +dtb-$(CONFIG_ARCH_QTI_VM) += lahaina-vm-mtp.dtb \ + lahaina-vm-cdp.dtb \ + lahaina-vm-qrd.dtb endif endif @@ -149,6 +151,15 @@ dtb-$(CONFIG_ARCH_SDXLEMUR) += sdxlemur-rumi.dtb \ sdxlemur-cdp.dtb \ sdxlemur-mtp.dtb +ifeq ($(CONFIG_ARCH_SHIMA), y) +ifeq ($(CONFIG_ARCH_QTI_VM), y) +dtb-$(CONFIG_ARCH_QTI_VM) += shima-vm-rumi.dtb \ + shima-vm-atp.dtb \ + shima-vm-idp.dtb \ + shima-vm-qrd.dtb +endif +endif + always := $(dtb-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/qcom/holi-atp.dtsi b/qcom/holi-atp.dtsi index 73ea0bcb4b86..ab7daf265da5 100644 --- a/qcom/holi-atp.dtsi +++ b/qcom/holi-atp.dtsi @@ -3,6 +3,7 @@ #include "holi-pmic-overlay.dtsi" #include "display/holi-sde-display-atp.dtsi" #include "holi-thermal-overlay.dtsi" +#include &sdhc_1 { status = "ok"; @@ -80,6 +81,9 @@ qcom,sn-ven = <&tlmm 6 0x00>; qcom,sn-firm = <&tlmm 8 0x00>; qcom,sn-clkreq = <&tlmm 7 0x00>; + qcom,sn-vdd-1p8-supply = <&L11A>; + qcom,sn-vdd-1p8-voltage = <1800000 1800000>; + qcom,sn-vdd-1p8-current = <157000>; interrupt-parent = <&tlmm>; interrupts = <9 0>; interrupt-names = "nfc_irq"; @@ -125,6 +129,88 @@ status = "ok"; }; +&pm7250b_charger { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, + <&pm7250b_qg PSY_IIO_TEMP>, + <&pm7250b_qg PSY_IIO_CAPACITY>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, + <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, + <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, + <&pm7250b_qg PSY_IIO_CC_SOC>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now"; + qcom,batteryless-platform; + qcom,sec-charger-config = <0>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; +}; + +&pm7250b_qg { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, + <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done"; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; +}; + &qupv3_se8_i2c { status = "okay"; qcom,i2c-touch-active="synaptics,tcm-i2c"; @@ -158,3 +244,53 @@ &dsi_rm69299_visionox_amoled_cmd>; }; }; + +&pm7250b_charger { + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L3A>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, + <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_PR_SWAP>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_MODE>, + <&pm7250b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; + +&usb0 { + extcon = <&pm7250b_pdphy>, <&eud>; +}; diff --git a/qcom/holi-audio-overlay.dtsi b/qcom/holi-audio-overlay.dtsi index 63ff9a5c50e8..93fd6e0ce027 100644 --- a/qcom/holi-audio-overlay.dtsi +++ b/qcom/holi-audio-overlay.dtsi @@ -33,6 +33,7 @@ qcom,va-swr-gpios = <&va_swr_gpios>; swr0: va_swr_master { compatible = "qcom,swr-mstr"; + qcom,is_wcd937x = <1>; #address-cells = <2>; #size-cells = <0>; clock-names = "lpass_audio_hw_vote"; diff --git a/qcom/holi-cdp.dtsi b/qcom/holi-cdp.dtsi index 80790f30e271..d7e950570492 100644 --- a/qcom/holi-cdp.dtsi +++ b/qcom/holi-cdp.dtsi @@ -4,6 +4,7 @@ #include "holi-pmic-overlay.dtsi" #include "display/holi-sde-display-cdp.dtsi" #include "holi-thermal-overlay.dtsi" +#include &sdhc_1 { status = "ok"; @@ -81,6 +82,9 @@ qcom,sn-ven = <&tlmm 6 0x00>; qcom,sn-firm = <&tlmm 8 0x00>; qcom,sn-clkreq = <&tlmm 7 0x00>; + qcom,sn-vdd-1p8-supply = <&L11A>; + qcom,sn-vdd-1p8-voltage = <1800000 1800000>; + qcom,sn-vdd-1p8-current = <157000>; interrupt-parent = <&tlmm>; interrupts = <9 0>; interrupt-names = "nfc_irq"; @@ -114,6 +118,88 @@ status = "ok"; }; +&pm7250b_charger { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, + <&pm7250b_qg PSY_IIO_TEMP>, + <&pm7250b_qg PSY_IIO_CAPACITY>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, + <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, + <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, + <&pm7250b_qg PSY_IIO_CC_SOC>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now"; + qcom,batteryless-platform; + qcom,sec-charger-config = <0>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; +}; + +&pm7250b_qg { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, + <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done"; + qcom,qg-iterm-ma = <100>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; +}; + &qupv3_se8_i2c { status = "okay"; qcom,i2c-touch-active="synaptics,tcm-i2c"; @@ -149,3 +235,53 @@ }; #include "camera/holi-camera-sensor-cdp.dtsi" + +&pm7250b_charger { + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L3A>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, + <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_PR_SWAP>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_MODE>, + <&pm7250b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; + +&usb0 { + extcon = <&pm7250b_pdphy>, <&eud>; +}; diff --git a/qcom/holi-coresight.dtsi b/qcom/holi-coresight.dtsi index 201a31415979..f6db99b519d2 100644 --- a/qcom/holi-coresight.dtsi +++ b/qcom/holi-coresight.dtsi @@ -45,9 +45,9 @@ reg-names = "tgu-base"; tgu-steps = <3>; tgu-conditions = <4>; - tgu-regs = <4>; + tgu-regs = <8>; tgu-timer-counters = <8>; - + interrupts = <0 23 1>, <0 24 1>, <0 25 1>, <0 26 1>; coresight-name = "coresight-tgu-apss"; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; @@ -1958,7 +1958,7 @@ clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; - + coresight-ctis = <&cti0 &cti6>; in-ports { port { tmc_etf_in_funnel_merge: endpoint { diff --git a/qcom/holi-ion.dtsi b/qcom/holi-ion.dtsi index 7e4e15b2811e..88962f965c93 100644 --- a/qcom/holi-ion.dtsi +++ b/qcom/holi-ion.dtsi @@ -16,6 +16,15 @@ qcom,ion-heap-type = "SYSTEM_SECURE"; }; + qcom,ion-heap@14 { /* SECURE CARVEOUT HEAP */ + reg = ; + qcom,ion-heap-type = "SECURE_CARVEOUT"; + cdsp { + memory-region = <&cdsp_secure_heap_mem>; + token = <0x20000000>; + }; + }; + qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */ reg = ; memory-region = <&secure_display_memory>; diff --git a/qcom/holi-mtp-usbc.dtsi b/qcom/holi-mtp-usbc.dtsi index 6ebc5c228887..ede4c9f9c84b 100644 --- a/qcom/holi-mtp-usbc.dtsi +++ b/qcom/holi-mtp-usbc.dtsi @@ -2,6 +2,7 @@ #include #include #include "holi-pmic-overlay.dtsi" +#include &sdhc_1 { status = "ok"; @@ -92,8 +93,159 @@ linux,can-disable; }; }; + + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + #include "qg-batterydata-atl466271_3300mAh.dtsi" + #include "qg-batterydata-atl436186020H_3780mAh.dtsi" + }; +}; + +&pm7250b_charger { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, + <&pm7250b_qg PSY_IIO_TEMP>, + <&pm7250b_qg PSY_IIO_CAPACITY>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, + <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, + <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, + <&pm7250b_qg PSY_IIO_CC_SOC>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now"; + qcom,battery-data = <&mtp_batterydata>; + qcom,sec-charger-config = <1>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; + qcom,fcc-stepping-enable; + qcom,fcc-step-delay-ms = <100>; + qcom,fcc-step-size-ua = <100000>; + qcom,smb-internal-pull-kohm = <0>; + qcom,en-skin-therm-mitigation; + qcom,hvdcp3-standalone-config; +}; + +&pm7250b_qg { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, + <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done"; + qcom,battery-data = <&mtp_batterydata>; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; + qcom,tcss-enable; + qcom,fvss-enable; + qcom,fvss-vbatt-mv = <3300>; + qcom,bass-enable; + qcom,use-cp-iin-sns; }; &pm6150a_amoled { status = "ok"; }; + +&pm7250b_charger { + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L3A>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, + <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_PR_SWAP>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_MODE>, + <&pm7250b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; + +&usb0 { + extcon = <&pm7250b_pdphy>, <&eud>; +}; diff --git a/qcom/holi-mtp.dtsi b/qcom/holi-mtp.dtsi index 6f26219570d6..23e65b9e01d7 100644 --- a/qcom/holi-mtp.dtsi +++ b/qcom/holi-mtp.dtsi @@ -4,6 +4,7 @@ #include "holi-pmic-overlay.dtsi" #include "display/holi-sde-display-mtp.dtsi" #include "holi-thermal-overlay.dtsi" +#include &sdhc_1 { status = "ok"; @@ -81,6 +82,9 @@ qcom,sn-ven = <&tlmm 6 0x00>; qcom,sn-firm = <&tlmm 8 0x00>; qcom,sn-clkreq = <&tlmm 7 0x00>; + qcom,sn-vdd-1p8-supply = <&L11A>; + qcom,sn-vdd-1p8-voltage = <1800000 1800000>; + qcom,sn-vdd-1p8-current = <157000>; interrupt-parent = <&tlmm>; interrupts = <9 0>; interrupt-names = "nfc_irq"; @@ -108,6 +112,13 @@ linux,can-disable; }; }; + + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + #include "qg-batterydata-atl466271_3300mAh.dtsi" + #include "qg-batterydata-atl436186020H_3780mAh.dtsi" + }; }; &pm6150a_amoled { @@ -148,4 +159,148 @@ }; }; +&pm7250b_charger { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, + <&pm7250b_qg PSY_IIO_TEMP>, + <&pm7250b_qg PSY_IIO_CAPACITY>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, + <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, + <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, + <&pm7250b_qg PSY_IIO_CC_SOC>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now"; + qcom,battery-data = <&mtp_batterydata>; + qcom,sec-charger-config = <1>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; + qcom,fcc-stepping-enable; + qcom,fcc-step-delay-ms = <100>; + qcom,fcc-step-size-ua = <100000>; + qcom,smb-internal-pull-kohm = <0>; + qcom,en-skin-therm-mitigation; + qcom,hvdcp3-standalone-config; +}; + +&pm7250b_qg { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, + <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done"; + qcom,battery-data = <&mtp_batterydata>; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; + qcom,tcss-enable; + qcom,fvss-enable; + qcom,fvss-vbatt-mv = <3300>; + qcom,bass-enable; + qcom,use-cp-iin-sns; +}; + #include "camera/holi-camera-sensor-mtp.dtsi" + +&pm7250b_charger { + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L3A>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, + <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_PR_SWAP>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_MODE>, + <&pm7250b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; + +&usb0 { + extcon = <&pm7250b_pdphy>, <&eud>; +}; diff --git a/qcom/holi-pm.dtsi b/qcom/holi-pm.dtsi index 4ed3dba882d1..1beb1fb123fd 100644 --- a/qcom/holi-pm.dtsi +++ b/qcom/holi-pm.dtsi @@ -2,6 +2,7 @@ qcom,lpm-levels { compatible = "qcom,lpm-levels"; reg = <0xfd91060 0x20>, <0xfd92060 0x20>; + reg-names = "pwr", "perf"; #address-cells = <1>; #size-cells = <0>; @@ -45,6 +46,7 @@ #size-cells = <0>; qcom,psci-mode-shift = <0>; qcom,psci-mode-mask = <0xf>; + label = "pwr"; qcom,ref-stddev = <500>; qcom,tmr-add = <1000>; qcom,ref-premature-cnt = <1>; @@ -98,6 +100,7 @@ #size-cells = <0>; qcom,psci-mode-shift = <0>; qcom,psci-mode-mask = <0xf>; + label = "perf"; qcom,ref-stddev = <100>; qcom,tmr-add = <100>; qcom,ref-premature-cnt = <3>; diff --git a/qcom/holi-pmic-overlay.dtsi b/qcom/holi-pmic-overlay.dtsi index 215e805d6527..fdea52c3dee0 100644 --- a/qcom/holi-pmic-overlay.dtsi +++ b/qcom/holi-pmic-overlay.dtsi @@ -1,5 +1,6 @@ #include #include +#include #include "pm6350.dtsi" #include "pm7250b.dtsi" @@ -244,6 +245,20 @@ }; }; +&flash_led { + status = "ok"; + io-channels = <&pm7250b_qg PSY_IIO_RESISTANCE>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_charger PSY_IIO_FLASH_TRIGGER>, + <&pm7250b_charger PSY_IIO_FLASH_ACTIVE>; + io-channel-names = "rbatt", + "voltage_ocv", + "current_now", + "flash_trigger", + "flash_active"; +}; + &thermal_zones { chg-skin-therm-usr { polling-delay-passive = <0>; diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index 27910adb00bc..ff21d1605104 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -5,6 +5,7 @@ #include "holi-thermal-overlay.dtsi" #include "camera/holi-camera-sensor-qrd.dtsi" #include "display/holi-sde-display-qrd.dtsi" +#include &sdhc_1 { status = "ok"; @@ -82,6 +83,9 @@ qcom,sn-ven = <&tlmm 6 0x00>; qcom,sn-firm = <&tlmm 8 0x00>; qcom,sn-clkreq = <&tlmm 7 0x00>; + qcom,sn-vdd-1p8-supply = <&L11A>; + qcom,sn-vdd-1p8-voltage = <1800000 1800000>; + qcom,sn-vdd-1p8-current = <157000>; interrupt-parent = <&tlmm>; interrupts = <9 0>; interrupt-names = "nfc_irq"; @@ -217,8 +221,160 @@ linux,can-disable; }; }; + + qrd_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-atl436186020H_3780mAh.dtsi" + #include "qg-batterydata-atl466271_3300mAh.dtsi" + }; }; &pm6150a_amoled { status = "ok"; }; + +&pm7250b_charger { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, + <&pm7250b_qg PSY_IIO_TEMP>, + <&pm7250b_qg PSY_IIO_CAPACITY>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, + <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, + <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, + <&pm7250b_qg PSY_IIO_CC_SOC>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now"; + qcom,battery-data = <&qrd_batterydata>; + qcom,sec-charger-config = <1>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; + qcom,fcc-stepping-enable; + qcom,fcc-step-delay-ms = <100>; + qcom,fcc-step-size-ua = <100000>; + qcom,smb-internal-pull-kohm = <0>; + qcom,en-skin-therm-mitigation; + qcom,thermal-mitigation = <10000000 9500000 9000000 8500000 8000000 + 7500000 7000000 6500000 6000000 5500000 5000000 4500000 + 4000000 3500000 3000000 2500000 2000000 1500000 1000000 + 500000>; +}; + +&pm7250b_qg { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, + <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done"; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; + qcom,tcss-enable; + qcom,fvss-enable; + qcom,fvss-vbatt-mv = <3300>; + qcom,bass-enable; + qcom,use-cp-iin-sns; +}; + +&pm7250b_charger { + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L3A>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, + <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_PR_SWAP>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_MODE>, + <&pm7250b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; + +&usb0 { + extcon = <&pm7250b_pdphy>, <&eud>; +}; diff --git a/qcom/holi-qupv3.dtsi b/qcom/holi-qupv3.dtsi index a24f54a1d308..530d54e635a3 100644 --- a/qcom/holi-qupv3.dtsi +++ b/qcom/holi-qupv3.dtsi @@ -318,6 +318,7 @@ dmas = <&gpi_dma1 0 4 3 64 0>, <&gpi_dma1 1 4 3 64 0>; dma-names = "tx", "rx"; + qcom,shared; qcom,wrapper-core = <&qupv3_1>; status = "disabled"; }; diff --git a/qcom/holi-regulators.dtsi b/qcom/holi-regulators.dtsi index 7badbe0dc954..7d2ca92fd40e 100644 --- a/qcom/holi-regulators.dtsi +++ b/qcom/holi-regulators.dtsi @@ -6,7 +6,7 @@ S1A: pm6350_s1: regulator-s1 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1200000>; - qcom,init-voltage = <1000000>; + qcom,init-voltage = <1128000>; status = "okay"; }; }; @@ -16,7 +16,7 @@ S2A: pm6350_s2: regulator-s2 { regulator-min-microvolt = <1503000>; regulator-max-microvolt = <2048000>; - qcom,init-voltage = <1503000>; + qcom,init-voltage = <2040000>; status = "okay"; }; }; @@ -50,7 +50,7 @@ qcom,use-voltage-level; }; - gfx_cdev: gfx-reg-cdev { + gfx_cdev: gfx-cdev { compatible = "qcom,regulator-cooling-device"; regulator-cdev-supply = <&VDD_GFX_LEVEL_AO>; regulator-levels = ; regulator-max-microvolt = <1980000>; - qcom,init-voltage = <1620000>; + qcom,init-voltage = <1800000>; status = "okay"; }; }; @@ -151,7 +151,7 @@ L3A: pm6350_l3: regulator-l3 { regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3300000>; - qcom,init-voltage = <2700000>; + qcom,init-voltage = <3080000>; status = "okay"; }; }; @@ -161,7 +161,7 @@ L4A: pm6350_l4: regulator-l4 { regulator-min-microvolt = <352000>; regulator-max-microvolt = <801000>; - qcom,init-voltage = <352000>; + qcom,init-voltage = <704000>; status = "okay"; }; }; @@ -198,10 +198,13 @@ rpm-regulator-ldoa8 { status = "okay"; + proxy-supply = <&pm6350_l8>; L8A: pm6350_l8: regulator-l8 { regulator-min-microvolt = <2500000>; regulator-max-microvolt = <3544000>; qcom,init-voltage = <2500000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <857000>; status = "okay"; }; }; @@ -231,7 +234,7 @@ L11A: pm6350_l11: regulator-l11 { regulator-min-microvolt = <1503000>; regulator-max-microvolt = <2000000>; - qcom,init-voltage = <1503000>; + qcom,init-voltage = <1800000>; status = "okay"; }; }; @@ -241,7 +244,7 @@ L12A: pm6350_l12: regulator-l12 { regulator-min-microvolt = <1620000>; regulator-max-microvolt = <1980000>; - qcom,init-voltage = <1620000>; + qcom,init-voltage = <1800000>; status = "okay"; }; }; @@ -251,7 +254,7 @@ L13A: pm6350_l13: regulator-l13 { regulator-min-microvolt = <570000>; regulator-max-microvolt = <650000>; - qcom,init-voltage = <570000>; + qcom,init-voltage = <600000>; status = "okay"; }; }; @@ -271,7 +274,7 @@ L15A: pm6350_l15: regulator-l15 { regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1305000>; - qcom,init-voltage = <1100000>; + qcom,init-voltage = <1200000>; status = "okay"; }; }; @@ -281,7 +284,7 @@ L16A: pm6350_l16: regulator-l16 { regulator-min-microvolt = <830000>; regulator-max-microvolt = <921000>; - qcom,init-voltage = <830000>; + qcom,init-voltage = <880000>; status = "okay"; }; }; @@ -309,7 +312,7 @@ L18A: pm6350_l18: regulator-l18 { regulator-min-microvolt = <788000>; regulator-max-microvolt = <1049000>; - qcom,init-voltage = <788000>; + qcom,init-voltage = <880000>; status = "okay"; }; }; @@ -349,7 +352,7 @@ L22A: pm6350_l22: regulator-l22 { regulator-min-microvolt = <1080000>; regulator-max-microvolt = <1305000>; - qcom,init-voltage = <1080000>; + qcom,init-voltage = <1232000>; status = "okay"; }; }; @@ -365,7 +368,7 @@ BOB: pm6150a_bob: regulator-pm6150a-bob { regulator-min-microvolt = <1650000>; regulator-max-microvolt = <5500000>; - qcom,init-voltage = <1650000>; + qcom,init-voltage = <3296000>; qcom,init-bob-mode = ; status = "okay"; }; @@ -373,7 +376,7 @@ BOB_AO: pm6150a_bob_ao: regulator-pm6150a-bob-ao { regulator-min-microvolt = <1650000>; regulator-max-microvolt = <5500000>; - qcom,init-voltage = <1650000>; + qcom,init-voltage = <3296000>; qcom,init-bob-mode = ; status = "okay"; }; @@ -443,17 +446,20 @@ S8E: pm6150a_s8: regulator-s8 { regulator-min-microvolt = <313000>; regulator-max-microvolt = <1395000>; - qcom,init-voltage = <313000>; + qcom,init-voltage = <1352000>; status = "okay"; }; }; rpm-regulator-ldoe1 { status = "okay"; + proxy-supply = <&pm6150a_l1>; L1E: pm6150a_l1: regulator-l1 { regulator-min-microvolt = <1650000>; regulator-max-microvolt = <1980000>; qcom,init-voltage = <1650000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <62000>; status = "okay"; }; }; @@ -503,7 +509,7 @@ L6E: pm6150a_l6: regulator-l6 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <3544000>; - qcom,init-voltage = <1700000>; + qcom,init-voltage = <2960000>; status = "okay"; }; }; @@ -513,7 +519,7 @@ L7E: pm6150a_l7: regulator-l7 { regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; - qcom,init-voltage = <2700000>; + qcom,init-voltage = <2960000>; status = "okay"; }; }; @@ -533,7 +539,7 @@ L9E: pm6150a_l9: regulator-l9 { regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; - qcom,init-voltage = <2700000>; + qcom,init-voltage = <2960000>; status = "okay"; }; }; @@ -565,5 +571,7 @@ reg = <0x162F000 0x60>; regulator-name = "refgen"; regulator-enable-ramp-delay = <5>; + proxy-supply = <&refgen>; + qcom,proxy-consumer-enable; }; }; diff --git a/qcom/holi-thermal-overlay.dtsi b/qcom/holi-thermal-overlay.dtsi index f9c2e39e0dec..1eaf50bcf0f6 100644 --- a/qcom/holi-thermal-overlay.dtsi +++ b/qcom/holi-thermal-overlay.dtsi @@ -4,6 +4,10 @@ #cooling-cells = <2>; }; +&pm7250b_charger { + #cooling-cells = <2>; +}; + &thermal_zones { socd { cooling-maps { @@ -19,6 +23,24 @@ }; }; + pm7250b_tz { + cooling-maps { + battery_cdev0 { + trip = <&pm7250b_trip0>; + cooling-device = + <&pm7250b_charger (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + + battery_cdev1 { + trip = <&pm7250b_trip1>; + cooling-device = + <&pm7250b_charger THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + pm6350_tz { cooling-maps { trip0_cpu0 { diff --git a/qcom/holi-usb.dtsi b/qcom/holi-usb.dtsi index 573bcff31175..beca47439f58 100644 --- a/qcom/holi-usb.dtsi +++ b/qcom/holi-usb.dtsi @@ -16,9 +16,9 @@ ranges; dma-ranges; - interrupts = , - , - ; + interrupts-extended = <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <&wakegic 12 IRQ_TYPE_LEVEL_HIGH>, + <&wakegic 93 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event_irq", "ss_phy_irq", "hs_phy_irq"; clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 75f25dc999a6..f9b21403897d 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2,7 +2,7 @@ #include #include #include -#include +#include #include #include #include @@ -335,6 +335,16 @@ size = <0 0x800000>; }; + splash_memory: splash_region@0x85200000 { + reg = <0x0 0x85200000 0x0 0x00c00000>; + label = "cont_splash_region"; + }; + + dfps_data_memory: dfps_data_region@85e00000 { + reg = <0x0 0x85e00000 0x0 0x00100000>; + label = "dfps_data_region"; + }; + /* global autoconfigured region for contiguous allocations */ linux,cma { compatible = "shared-dma-pool"; @@ -387,6 +397,11 @@ android { compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; + }; + fstab { compatible = "android,fstab"; vendor { @@ -394,7 +409,7 @@ dev = "/dev/block/platform/soc/4744000.sdhci/by-name/vendor"; type = "ext4"; mnt_flags = "ro,barrier=1,discard"; - fsmgr_flags = "wait,slotselect"; + fsmgr_flags = "wait,slotselect,avb"; status = "ok"; }; }; @@ -651,72 +666,72 @@ }; l1_icache0 { - qcom,dump-size = <0x9040>; + qcom,dump-size = <0x10800>; qcom,dump-id = <0x60>; }; l1_icache1 { - qcom,dump-size = <0x9040>; + qcom,dump-size = <0x10800>; qcom,dump-id = <0x61>; }; l1_icache2 { - qcom,dump-size = <0x9040>; + qcom,dump-size = <0x10800>; qcom,dump-id = <0x62>; }; l1_icache3 { - qcom,dump-size = <0x9040>; + qcom,dump-size = <0x10800>; qcom,dump-id = <0x63>; }; l1_icache100 { - qcom,dump-size = <0x12000>; + qcom,dump-size = <0x10800>; qcom,dump-id = <0x64>; }; l1_icache101 { - qcom,dump-size = <0x12000>; + qcom,dump-size = <0x10800>; qcom,dump-id = <0x65>; }; l1_icache102 { - qcom,dump-size = <0x12000>; + qcom,dump-size = <0x21000>; qcom,dump-id = <0x66>; }; l1_icache103 { - qcom,dump-size = <0x12000>; + qcom,dump-size = <0x21000>; qcom,dump-id = <0x67>; }; l1_dcache0 { - qcom,dump-size = <0x9040>; + qcom,dump-size = <0x9000>; qcom,dump-id = <0x80>; }; l1_dcache1 { - qcom,dump-size = <0x9040>; + qcom,dump-size = <0x9000>; qcom,dump-id = <0x81>; }; l1_dcache2 { - qcom,dump-size = <0x9040>; + qcom,dump-size = <0x9000>; qcom,dump-id = <0x82>; }; l1_dcache3 { - qcom,dump-size = <0x9040>; + qcom,dump-size = <0x9000>; qcom,dump-id = <0x83>; }; l1_dcache100 { - qcom,dump-size = <0x12000>; + qcom,dump-size = <0x9000>; qcom,dump-id = <0x84>; }; l1_dcache101 { - qcom,dump-size = <0x12000>; + qcom,dump-size = <0x9000>; qcom,dump-id = <0x85>; }; @@ -731,42 +746,42 @@ }; l2_tlb0 { - qcom,dump-size = <0x2000>; + qcom,dump-size = <0x5a00>; qcom,dump-id = <0x120>; }; l2_tlb1 { - qcom,dump-size = <0x2000>; + qcom,dump-size = <0x5a00>; qcom,dump-id = <0x121>; }; l2_tlb2 { - qcom,dump-size = <0x2000>; + qcom,dump-size = <0x5a00>; qcom,dump-id = <0x122>; }; l2_tlb3 { - qcom,dump-size = <0x2000>; + qcom,dump-size = <0x5a00>; qcom,dump-id = <0x123>; }; l2_tlb100 { - qcom,dump-size = <0x4800>; + qcom,dump-size = <0x5a00>; qcom,dump-id = <0x124>; }; l2_tlb101 { - qcom,dump-size = <0x4800>; + qcom,dump-size = <0x5a00>; qcom,dump-id = <0x125>; }; l2_tlb102 { - qcom,dump-size = <0x4800>; + qcom,dump-size = <0x7800>; qcom,dump-id = <0x126>; }; l2_tlb103 { - qcom,dump-size = <0x4800>; + qcom,dump-size = <0x7800>; qcom,dump-id = <0x127>; }; @@ -776,7 +791,7 @@ }; rpm_sw { - qcom,dump-size = <0x28000>; + qcom,dump-size = <0x2c000>; qcom,dump-id = <0xea>; }; @@ -819,6 +834,16 @@ qcom,dump-size = <0x1000>; qcom,dump-id = <0x104>; }; + + pcu_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x164>; + }; + + fsm_data { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x165>; + }; }; qcom,msm-imem@c125000 { @@ -858,6 +883,11 @@ reg = <0x94c 0xc8>; }; + pil@6dc { + compatible = "qcom,msm-imem-pil-disable-timeout"; + reg = <0x6dc 0x4>; + }; + diag_dload@c8 { compatible = "qcom,msm-imem-diag-dload"; reg = <0xc8 0xc8>; @@ -907,7 +937,7 @@ rpm_bus: qcom,rpm-smd { compatible = "qcom,rpm-smd"; rpm-channel-name = "rpm_requests"; - interrupts = ; + interrupts = ; rpm-channel-type = <15>; /* SMD_APPS_RPM */ }; @@ -932,37 +962,43 @@ <&rpmcc RPM_SMD_QUP_A_CLK>; }; - system_noc: interconnect@1880000 { - reg = <0x01880000 0x1900>; - compatible = "qcom,holi-system_noc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_SNOC_CLK>, - <&rpmcc RPM_SMD_SNOC_A_CLK>; - }; - - mmnrt_virt: interconnect@1899000 { - reg = <0x01899000 0x6000>; + mmnrt_virt: interconnect@0 { compatible = "qcom,holi-mmnrt_virt"; #interconnect-cells = <1>; + qcom,util-factor = <142>; + qcom,keepalive; clock-names = "bus", "bus_a"; clocks = <&rpmcc RPM_SMD_MMNRT_CLK>, <&rpmcc RPM_SMD_MMNRT_A_CLK>; }; - mmrt_virt: interconnect@189f000 { - reg = <0x0189f000 0x1000>; + mmrt_virt: interconnect@1 { compatible = "qcom,holi-mmrt_virt"; #interconnect-cells = <1>; + qcom,util-factor = <142>; + qcom,keepalive; clock-names = "bus", "bus_a"; clocks = <&rpmcc RPM_SMD_MMRT_CLK>, <&rpmcc RPM_SMD_MMRT_A_CLK>; }; + system_noc: interconnect@1880000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x01880000 0x5f080>; + compatible = "qcom,holi-system_noc"; + #interconnect-cells = <1>; + qcom,keepalive; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; + config_noc: interconnect@1900000 { reg = <0x01900000 0x6200>; compatible = "qcom,holi-config_noc"; #interconnect-cells = <1>; + qcom,keepalive; clock-names = "bus", "bus_a"; clocks = <&rpmcc RPM_SMD_CNOC_CLK>, <&rpmcc RPM_SMD_CNOC_A_CLK>; @@ -972,18 +1008,19 @@ reg = <0x04480000 0x80000>; compatible = "qcom,holi-bimc"; #interconnect-cells = <1>; + qcom,util-factor = <151>; + qcom,keepalive; clock-names = "bus", "bus_a"; clocks = <&rpmcc RPM_SMD_BIMC_CLK>, <&rpmcc RPM_SMD_BIMC_A_CLK>; }; - epss_l3_cpu: l3_cpu@fd91000 { - reg = <0x0fd91000 0x4000>; - compatible = "qcom,holi-epss-l3-cpu"; + cpucp_l3_cpu: l3_cpu@fd90000 { + reg = <0x0fd90000 0x3000>; + compatible = "qcom,holi-cpucp-l3-cpu"; #interconnect-cells = <1>; clock-names = "xo", "alternate"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; - status = "disabled"; }; qcom,memshare { @@ -1013,6 +1050,94 @@ }; }; + jtag_mm0: jtagmm@9040000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9040000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU0>; + }; + + jtag_mm1: jtagmm@9140000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9140000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU1>; + }; + + jtag_mm2: jtagmm@9240000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9240000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU2>; + }; + + jtag_mm3: jtagmm@9340000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9340000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU3>; + }; + + jtag_mm4: jtagmm@9440000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9440000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU4>; + }; + + jtag_mm5: jtagmm@9540000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9540000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU5>; + }; + + jtag_mm6: jtagmm@9640000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9640000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU6>; + }; + + jtag_mm7: jtagmm@9740000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9740000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU7>; + }; + clocks { xo_board: xo-board { compatible = "fixed-clock"; @@ -1102,13 +1227,19 @@ cpufreq_hw: qcom,cpufreq-hw { compatible = "qcom,cpufreq-hw-epss"; - reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>; - reg-names = "freq-domain0", "freq-domain1"; + reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>, + <0x0fd04504 0x4>, <0x0fd04508 0x4>; + reg-names = "freq-domain0", "freq-domain1", + "pdmem-domain0", "pdmem-domain1"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; clock-names = "xo", "alternate"; qcom,lut-row-size = <4>; qcom,max-lut-entries = <12>; qcom,skip-enable-check; + qcom,perf-lock-support; + interrupts = , + ; + interrupt-names = "dcvsh0_int", "dcvsh1_int"; #freq-domain-cells = <2>; }; @@ -1152,8 +1283,8 @@ reg-names = "ftbl-base"; governor = "mem_latency"; interconnects = - <&epss_l3_cpu MASTER_EPSS_L3_APPS - &epss_l3_cpu SLAVE_EPSS_L3_CPU0>; + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU0>; }; cpu1_cpu_l3_lat: qcom,cpu1-cpu-l3-lat { @@ -1162,8 +1293,8 @@ reg-names = "ftbl-base"; governor = "mem_latency"; interconnects = - <&epss_l3_cpu MASTER_EPSS_L3_APPS - &epss_l3_cpu SLAVE_EPSS_L3_CPU1>; + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU1>; }; cpu2_cpu_l3_lat: qcom,cpu2-cpu-l3-lat { @@ -1172,8 +1303,8 @@ reg-names = "ftbl-base"; governor = "mem_latency"; interconnects = - <&epss_l3_cpu MASTER_EPSS_L3_APPS - &epss_l3_cpu SLAVE_EPSS_L3_CPU2>; + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU2>; }; cpu3_cpu_l3_lat: qcom,cpu3-cpu-l3-lat { @@ -1182,8 +1313,8 @@ reg-names = "ftbl-base"; governor = "mem_latency"; interconnects = - <&epss_l3_cpu MASTER_EPSS_L3_APPS - &epss_l3_cpu SLAVE_EPSS_L3_CPU3>; + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU3>; }; cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat { @@ -1192,8 +1323,8 @@ reg-names = "ftbl-base"; governor = "mem_latency"; interconnects = - <&epss_l3_cpu MASTER_EPSS_L3_APPS - &epss_l3_cpu SLAVE_EPSS_L3_CPU4>; + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU4>; }; cpu5_cpu_l3_lat: qcom,cpu5-cpu-l3-lat { @@ -1202,12 +1333,12 @@ reg-names = "ftbl-base"; governor = "mem_latency"; interconnects = - <&epss_l3_cpu MASTER_EPSS_L3_APPS - &epss_l3_cpu SLAVE_EPSS_L3_CPU5>; + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU5>; }; cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { - compatible = "qcom,devfreq-icc-ddr"; + compatible = "qcom,devfreq-icc"; governor = "compute"; interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI>; qcom,active-only; @@ -1220,8 +1351,8 @@ reg-names = "ftbl-base"; governor = "mem_latency"; interconnects = - <&epss_l3_cpu MASTER_EPSS_L3_APPS - &epss_l3_cpu SLAVE_EPSS_L3_CPU6>; + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU6>; }; cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat { @@ -1230,12 +1361,12 @@ reg-names = "ftbl-base"; governor = "mem_latency"; interconnects = - <&epss_l3_cpu MASTER_EPSS_L3_APPS - &epss_l3_cpu SLAVE_EPSS_L3_CPU7>; + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU7>; }; cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat { - compatible = "qcom,devfreq-icc-ddr"; + compatible = "qcom,devfreq-icc"; governor = "mem_latency"; interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI>; qcom,active-only; @@ -1243,7 +1374,7 @@ }; cpu6_cpu_ddr_lat: qcom,cpu6-cpu-ddr-lat { - compatible = "qcom,devfreq-icc-ddr"; + compatible = "qcom,devfreq-icc"; governor = "mem_latency"; interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI>; qcom,active-only; @@ -1251,7 +1382,7 @@ }; cpu6_cpu_ddr_latfloor: qcom,cpu6-cpu-ddr-latfloor { - compatible = "qcom,devfreq-icc-ddr"; + compatible = "qcom,devfreq-icc"; governor = "compute"; interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI>; qcom,active-only; @@ -1739,7 +1870,7 @@ kryo-erp { compatible = "arm,arm64-kryo-cpu-erp"; - interrupts = , + interrupts = , ; interrupt-names = "l1-l2-faultirq","l3-scu-faultirq"; }; @@ -2028,8 +2159,12 @@ ; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; - clock-names = "core", "iface"; + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "core", "iface", "ice_core"; + + qcom,ice-clk-rates = <300000000 100000000>; interconnects = <&system_noc MASTER_EMMC &bimc SLAVE_EBI>, <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_EMMC_CFG>; @@ -2390,9 +2525,12 @@ interrupt-names = "eud_irq"; interrupts = ; reg = <0x1628000 0x2000>, - <0x162A000 0x1000>; - reg-names = "eud_base", "eud_mode_mgr2"; + <0x162A000 0x1000>, + <0x3E5018 0x4>; + reg-names = "eud_base", "eud_mode_mgr2", + "eud_tcsr_check_reg"; qcom,secure-eud-en; + qcom,eud-tcsr-check-enable; status = "ok"; }; diff --git a/qcom/lahaina-audio-overlay.dtsi b/qcom/lahaina-audio-overlay.dtsi index 41d4af5efaaa..fe10fbdf88e0 100644 --- a/qcom/lahaina-audio-overlay.dtsi +++ b/qcom/lahaina-audio-overlay.dtsi @@ -317,6 +317,10 @@ "TX SWR_INPUT", "SWR_MIC1 SWR_DMIC_OUTPUT", "TX SWR_INPUT", "SWR_MIC2 SWR_DMIC_OUTPUT", "TX SWR_INPUT", "SWR_MIC3 SWR_DMIC_OUTPUT", + "VA SWR_INPUT", "SWR_MIC0 SWR_DMIC_VA_OUTPUT", + "VA SWR_INPUT", "SWR_MIC1 SWR_DMIC_VA_OUTPUT", + "VA SWR_INPUT", "SWR_MIC2 SWR_DMIC_VA_OUTPUT", + "VA SWR_INPUT", "SWR_MIC3 SWR_DMIC_VA_OUTPUT", "VA SWR_INPUT", "SWR_MIC0 SWR_DMIC_OUTPUT", "VA SWR_INPUT", "SWR_MIC1 SWR_DMIC_OUTPUT", "VA SWR_INPUT", "SWR_MIC2 SWR_DMIC_OUTPUT", @@ -355,16 +359,22 @@ asoc-codec = <&stub_codec>, <&bolero>, <&wcd938x_codec>, <&swr_haptics>, <&wsa883x_0221>, <&wsa883x_0222>, - <&swr_dmic_01>, <&swr_dmic_02>, - <&swr_dmic_03>, <&swr_dmic_04>, + <&swr_dmic_04>, <&swr_dmic_03>, + <&swr_dmic_02>, <&swr_dmic_01>, <&ext_disp_audio_codec>; asoc-codec-names = "msm-stub-codec.1", "bolero_codec", "wcd938x_codec", "swr-haptics", "wsa-codec1", "wsa-codec2", - "swr-dmic.01", "swr-dmic.02", - "swr-dmic.03", "swr-dmic.04", + "swr-dmic.04", "swr-dmic.03", + "swr-dmic.02", "swr-dmic.01", "msm-ext-disp-audio-codec-rx"; qcom,wsa-max-devs = <2>; + qcom,cps_reg_phy_addr = <0x3250300 0x3250304 0x3250318>; + qcom,cps_wsa_vbatt_temp_reg_addr = <0x0003429 0x0003422>; + qcom,cps_threshold_levels = <148 168>; + qcom,cps_normal_values = <0x8E 0x8F 0x8F>; + qcom,cps_lower1_values = <0x10 0xD0 0xD0>; + qcom,cps_lower2_values = <0x0F 0x0F 0x18>; qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>, <&bolero>; }; diff --git a/qcom/lahaina-cdp.dtsi b/qcom/lahaina-cdp.dtsi index f6d55be6b7ae..21ae311b63e2 100644 --- a/qcom/lahaina-cdp.dtsi +++ b/qcom/lahaina-cdp.dtsi @@ -77,7 +77,7 @@ st,touch-environment = "pvm"; st,trusted-touch-spi-irq = <566>; st,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>; - st,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x4000 0x4000>; + st,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; panel = <&dsi_sw43404_amoled_cmd &dsi_sw43404_amoled_video &dsi_sw43404_amoled_fhd_plus_cmd>; }; @@ -201,17 +201,20 @@ status = "ok"; }; -&dai_mi2s2 { - qcom,msm-mi2s-tx-lines = <1>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active - &tert_mi2s_sd0_active>; - pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep - &tert_mi2s_sd0_sleep>; +&q6core { + cdc_tert_mi2s_gpios: msm_cdc_pinctrl_tert { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active + &tert_mi2s_sd0_active>; + pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep + &tert_mi2s_sd0_sleep>; + }; }; &lahaina_snd { qcom,model = "lahaina-cdp-snd-card"; + qcom,tert-mi2s-gpios = <&cdc_tert_mi2s_gpios>; }; &usb1 { diff --git a/qcom/lahaina-coresight.dtsi b/qcom/lahaina-coresight.dtsi index cac602552fcf..fbe7d8b89e88 100644 --- a/qcom/lahaina-coresight.dtsi +++ b/qcom/lahaina-coresight.dtsi @@ -107,6 +107,7 @@ coresight-name = "coresight-tmc-etf"; coresight-csr = <&swao_csr>; + coresight-ctis = <&cti0 &cti6>; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; @@ -153,7 +154,7 @@ qcom,sw-usb; coresight-name = "coresight-tmc-etr"; - coresight-ctis = <&cti0 &cti0>; + coresight-ctis = <&cti0 &cti6>; coresight-csr = <&csr>; clocks = <&clock_aop QDSS_CLK>; diff --git a/qcom/lahaina-gpu.dtsi b/qcom/lahaina-gpu.dtsi index 00a629d1c01e..1292871e224f 100644 --- a/qcom/lahaina-gpu.dtsi +++ b/qcom/lahaina-gpu.dtsi @@ -23,10 +23,18 @@ clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, <&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>, <&clock_gpucc GPU_CC_AHB_CLK>, + <&clock_gpucc GPU_CC_CX_GMU_CLK>, + <&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&clock_gpucc GPU_CC_HUB_AON_CLK>, + <&clock_gpucc GPU_CC_HUB_CX_INT_CLK>, <&clock_aop QDSS_CLK>; clock-names = "gcc_gpu_memnoc_gfx", "gcc_gpu_snoc_dvm_gfx", "gpu_cc_ahb", + "gpu_cc_cx_gmu", + "gpu_cc_hlos1_vote_gpu_smmu", + "gpu_cc_hub_aon", + "gpu_cc_hub_cx_int", "apb_pclk"; qcom,chipid = <0x06060000>; @@ -233,7 +241,7 @@ gmu: qcom,gmu@3d69000 { compatible = "qcom,gpu-gmu"; - reg = <0x3d6a000 0x30000>, + reg = <0x3d6a000 0x34000>, <0xb290000 0x10000>; reg-names = "kgsl_gmu_reg", diff --git a/qcom/lahaina-hdk.dtsi b/qcom/lahaina-hdk.dtsi index 82a081b2ed99..07ece652dcf5 100644 --- a/qcom/lahaina-hdk.dtsi +++ b/qcom/lahaina-hdk.dtsi @@ -1 +1,69 @@ #include "lahaina-qrd-common.dtsi" + +&lahaina_snd { + qcom,model = "lahaina-hdk-snd-card"; + + qcom,audio-routing = + "AMIC1", "Analog Mic1", + "Analog Mic1", "MIC BIAS1", + "AMIC2", "Analog Mic2", + "Analog Mic2", "MIC BIAS2", + "AMIC3", "Analog Mic3", + "Analog Mic3", "MIC BIAS3", + "AMIC4", "Analog Mic4", + "Analog Mic4", "MIC BIAS3", + "AMIC5", "Analog Mic5", + "Analog Mic5", "MIC BIAS4", + "TX DMIC0", "Digital Mic0", + "Digital Mic0", "MIC BIAS1", + "TX DMIC1", "Digital Mic1", + "Digital Mic1", "MIC BIAS1", + "TX DMIC2", "Digital Mic2", + "Digital Mic2", "MIC BIAS3", + "TX DMIC3", "Digital Mic3", + "Digital Mic3", "MIC BIAS3", + "TX DMIC4", "Digital Mic4", + "Digital Mic4", "MIC BIAS4", + "TX DMIC5", "Digital Mic5", + "Digital Mic5", "MIC BIAS4", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "IN3_AUX", "AUX_OUT", + "HAP_IN", "PCM_OUT", + "WSA SRC0_INP", "SRC0", + "WSA_TX DEC0_INP", "TX DEC0 MUX", + "WSA_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "SpkrLeft IN", "WSA_SPK1 OUT", + "TX SWR_INPUT", "WCD_TX_OUTPUT", + "VA SWR_INPUT", "VA_SWR_CLK", + "VA SWR_INPUT", "WCD_TX_OUTPUT", + "VA_AIF1 CAP", "VA_SWR_CLK", + "VA_AIF2 CAP", "VA_SWR_CLK", + "VA_AIF3 CAP", "VA_SWR_CLK", + "VA DMIC0", "Digital Mic0", + "VA DMIC1", "Digital Mic1", + "VA DMIC2", "Digital Mic2", + "VA DMIC3", "Digital Mic3", + "VA DMIC4", "Digital Mic4", + "VA DMIC5", "Digital Mic5", + "Digital Mic0", "VA MIC BIAS1", + "Digital Mic1", "VA MIC BIAS1", + "Digital Mic2", "VA MIC BIAS3", + "Digital Mic3", "VA MIC BIAS3", + "Digital Mic4", "VA MIC BIAS4", + "Digital Mic5", "VA MIC BIAS4"; + + qcom,msm-mbhc-usbc-audio-supported = <0>; + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; +}; + +&usb1 { + dwc3@a800000 { + dr_mode = "host"; + }; +}; diff --git a/qcom/lahaina-mtp.dtsi b/qcom/lahaina-mtp.dtsi index f2094b9e91a2..277333c2c9bd 100644 --- a/qcom/lahaina-mtp.dtsi +++ b/qcom/lahaina-mtp.dtsi @@ -79,7 +79,7 @@ st,touch-environment = "pvm"; st,trusted-touch-spi-irq = <566>; st,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>; - st,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x4000 0x4000>; + st,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; panel = <&dsi_sw43404_amoled_cmd &dsi_sw43404_amoled_video &dsi_sw43404_amoled_fhd_plus_cmd>; }; @@ -182,13 +182,19 @@ status = "ok"; }; -&dai_mi2s2 { - qcom,msm-mi2s-tx-lines = <1>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active - &tert_mi2s_sd0_active>; - pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep - &tert_mi2s_sd0_sleep>; +&q6core { + cdc_tert_mi2s_gpios: msm_cdc_pinctrl_tert { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active + &tert_mi2s_sd0_active>; + pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep + &tert_mi2s_sd0_sleep>; + }; +}; + +&lahaina_snd { + qcom,tert-mi2s-gpios = <&cdc_tert_mi2s_gpios>; }; &usb1 { diff --git a/qcom/lahaina-pcie.dtsi b/qcom/lahaina-pcie.dtsi index ba945b01962d..055e3d3bc9d3 100644 --- a/qcom/lahaina-pcie.dtsi +++ b/qcom/lahaina-pcie.dtsi @@ -102,7 +102,7 @@ qcom,boot-option = <0x1>; qcom,drv-supported; qcom,l1ss-sleep-disable = <0x1>; - qcom,drv-l1ss-timeout-us = <10000>; + qcom,drv-l1ss-timeout-us = <5000>; qcom,use-19p2mhz-aux-clk; qcom,no-l0s-supported; qcom,l1-2-th-scale = <2>; @@ -110,7 +110,7 @@ qcom,slv-addr-space-size = <0x4000000>; qcom,ep-latency = <10>; - qcom,pcie-phy-ver = <10099>; + qcom,pcie-phy-ver = <10100>; qcom,phy-status-offset = <0x214>; qcom,phy-status-bit = <6>; qcom,phy-power-down-offset = <0x240>; @@ -177,6 +177,7 @@ 0x1050 0x08 0x0 0x1044 0xf0 0x0 0x11a4 0x38 0x0 + 0x10cc 0xf0 0x0 0x0694 0x00 0x0 0x0654 0x00 0x0 0x06a8 0x0f 0x0 diff --git a/qcom/lahaina-pm.dtsi b/qcom/lahaina-pm.dtsi index 3ba734efc30e..5028b6e124e4 100644 --- a/qcom/lahaina-pm.dtsi +++ b/qcom/lahaina-pm.dtsi @@ -24,15 +24,28 @@ qcom,psci-mode = <0x1>; }; - CLUSTER_OFF: qcom,pm-cluster-level@1 { /* AOSS sleep */ + CLUSTER_OFF: qcom,pm-cluster-level@1 { /* D4 */ reg = <1>; compatible = "arm,idle-state"; + idle-state-name = "l3-pc"; + entry-latency-us = <2752>; + exit-latency-us = <3048>; + min-residency-us = <6118>; + arm,psci-suspend-param = <0x40>; + qcom,psci-mode = <0x4>; + qcom,is-reset; + qcom,min-child-idx = <1>; + }; + + LLCC_OFF: qcom,pm-cluster-level@2 { /* AOSS sleep */ + reg = <2>; + compatible = "arm,idle-state"; idle-state-name = "llcc-off"; entry-latency-us = <3263>; exit-latency-us = <6562>; min-residency-us = <9987>; - arm,psci-suspend-param = <0xc240>; - qcom,psci-mode = <0xc24>; + arm,psci-suspend-param = <0xc340>; + qcom,psci-mode = <0xc34>; qcom,is-reset; qcom,notify-rpm; qcom,min-child-idx = <1>; diff --git a/qcom/lahaina-pmic-overlay.dtsi b/qcom/lahaina-pmic-overlay.dtsi index 57a499100d31..04f9febe27b1 100644 --- a/qcom/lahaina-pmic-overlay.dtsi +++ b/qcom/lahaina-pmic-overlay.dtsi @@ -554,3 +554,11 @@ nvmem-cell-names = "restart_reason"; }; }; + +&soc { + pmic-pon-log { + compatible = "qcom,pmic-pon-log"; + nvmem = <&pmk8350_sdam_5>; + nvmem-names = "pon_log"; + }; +}; diff --git a/qcom/lahaina-qrd-common.dtsi b/qcom/lahaina-qrd-common.dtsi index 54706c61fe95..438c2393b90e 100644 --- a/qcom/lahaina-qrd-common.dtsi +++ b/qcom/lahaina-qrd-common.dtsi @@ -97,6 +97,17 @@ }; }; +&q6core { + cdc_tert_mi2s_gpios: msm_cdc_pinctrl_tert { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active + &tert_mi2s_sd0_active>; + pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep + &tert_mi2s_sd0_sleep>; + }; +}; + &lahaina_snd { qcom,model = "lahaina-qrd-snd-card"; @@ -164,25 +175,8 @@ qcom,msm-mbhc-usbc-audio-supported = <1>; qcom,msm-mbhc-hphl-swh = <0>; qcom,msm-mbhc-gnd-swh = <0>; -}; -&usb1 { - status = "disabled"; -}; - -&usb2_phy1 { - status = "disabled"; -}; - -&usb_qmp_phy { - status = "disabled"; -}; - -&usb2_phy0 { - qcom,param-override-seq = - <0xe6 0x6c - 0x0f 0x70 - 0x17 0x74>; + qcom,tert-mi2s-gpios = <&cdc_tert_mi2s_gpios>; }; &qupv3_se4_i2c { @@ -214,15 +208,6 @@ }; }; -&dai_mi2s2 { - qcom,msm-mi2s-tx-lines = <1>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active - &tert_mi2s_sd0_active>; - pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep - &tert_mi2s_sd0_sleep>; -}; - &battery_charger { qcom,thermal-mitigation = <10000000 9500000 9000000 8500000 8000000 7500000 7000000 6500000 6000000 5500000 @@ -235,48 +220,6 @@ status = "ok"; }; -&usb_qmp_dp_phy { - pinctrl-names = "portselect"; -}; - -&usb0 { - ssusb_redriver = <&redriver>; -}; - -&qupv3_se13_i2c { - status = "ok"; - - redriver: redriver@1c { - compatible = "onnn,redriver"; - reg = <0x1c>; - - pinctrl-names = "enable_gpio"; - pinctrl-0 = <&usb3phy_portselect_gpio>; - orientation_gpio = <&tlmm 81 0>; - - eq = /bits/ 8 < - /* Parameters for USB */ - 0x4 0x4 0x4 0x4 - /* Parameters for DP */ - 0x6 0x4 0x4 0x6>; - flat-gain = /bits/ 8 < - /* Parameters for USB */ - 0x3 0x1 0x1 0x3 - /* Parameters for DP */ - 0x2 0x1 0x1 0x2>; - output-comp = /bits/ 8 < - /* Parameters for USB */ - 0x3 0x3 0x3 0x3 - /* Parameters for DP */ - 0x3 0x3 0x3 0x3>; - loss-match = /bits/ 8 < - /* Parameters for USB */ - 0x1 0x3 0x3 0x1 - /* Parameters for DP */ - 0x3 0x3 0x3 0x3>; - }; -}; - &qupv3_se15_i2c { status = "ok"; qcom,clk-freq-out = <1000000>; diff --git a/qcom/lahaina-qrd-module.dtsi b/qcom/lahaina-qrd-module.dtsi index 82a081b2ed99..e69c9b3b3c8d 100644 --- a/qcom/lahaina-qrd-module.dtsi +++ b/qcom/lahaina-qrd-module.dtsi @@ -1 +1,62 @@ #include "lahaina-qrd-common.dtsi" + +&usb1 { + status = "disabled"; +}; + +&usb2_phy1 { + status = "disabled"; +}; + +&usb_qmp_phy { + status = "disabled"; +}; + +&usb2_phy0 { + qcom,param-override-seq = + <0xe6 0x6c + 0x0f 0x70 + 0x17 0x74>; +}; + +&usb_qmp_dp_phy { + pinctrl-names = "portselect"; +}; + +&usb0 { + ssusb_redriver = <&redriver>; +}; + +&qupv3_se13_i2c { + status = "ok"; + + redriver: redriver@1c { + compatible = "onnn,redriver"; + reg = <0x1c>; + + pinctrl-names = "enable_gpio"; + pinctrl-0 = <&usb3phy_portselect_gpio>; + orientation_gpio = <&tlmm 81 0>; + + eq = /bits/ 8 < + /* Parameters for USB */ + 0x4 0x4 0x4 0x4 + /* Parameters for DP */ + 0x6 0x4 0x4 0x6>; + flat-gain = /bits/ 8 < + /* Parameters for USB */ + 0x3 0x1 0x1 0x3 + /* Parameters for DP */ + 0x2 0x1 0x1 0x2>; + output-comp = /bits/ 8 < + /* Parameters for USB */ + 0x3 0x3 0x3 0x3 + /* Parameters for DP */ + 0x3 0x3 0x3 0x3>; + loss-match = /bits/ 8 < + /* Parameters for USB */ + 0x1 0x3 0x3 0x1 + /* Parameters for DP */ + 0x3 0x3 0x3 0x3>; + }; +}; diff --git a/qcom/lahaina-qrd.dtsi b/qcom/lahaina-qrd.dtsi index 9e353a076090..d169151f2a0f 100644 --- a/qcom/lahaina-qrd.dtsi +++ b/qcom/lahaina-qrd.dtsi @@ -1,2 +1,62 @@ #include "lahaina-qrd-common.dtsi" +&usb1 { + status = "disabled"; +}; + +&usb2_phy1 { + status = "disabled"; +}; + +&usb_qmp_phy { + status = "disabled"; +}; + +&usb2_phy0 { + qcom,param-override-seq = + <0xe6 0x6c + 0x0c 0x70 + 0x17 0x74>; +}; + +&usb_qmp_dp_phy { + pinctrl-names = "portselect"; +}; + +&usb0 { + ssusb_redriver = <&redriver>; +}; + +&qupv3_se13_i2c { + status = "ok"; + + redriver: redriver@1c { + compatible = "onnn,redriver"; + reg = <0x1c>; + + pinctrl-names = "enable_gpio"; + pinctrl-0 = <&usb3phy_portselect_gpio>; + orientation_gpio = <&tlmm 81 0>; + + eq = /bits/ 8 < + /* Parameters for USB */ + 0x4 0x4 0x4 0x4 + /* Parameters for DP */ + 0x6 0x4 0x4 0x6>; + flat-gain = /bits/ 8 < + /* Parameters for USB */ + 0x3 0x1 0x1 0x3 + /* Parameters for DP */ + 0x2 0x1 0x1 0x2>; + output-comp = /bits/ 8 < + /* Parameters for USB */ + 0x3 0x3 0x3 0x3 + /* Parameters for DP */ + 0x3 0x3 0x3 0x3>; + loss-match = /bits/ 8 < + /* Parameters for USB */ + 0x1 0x3 0x3 0x1 + /* Parameters for DP */ + 0x3 0x3 0x3 0x3>; + }; +}; diff --git a/qcom/lahaina-regulators.dtsi b/qcom/lahaina-regulators.dtsi index c7579bec6687..9454da56a665 100644 --- a/qcom/lahaina-regulators.dtsi +++ b/qcom/lahaina-regulators.dtsi @@ -749,7 +749,7 @@ regulator-name = "pm8350c_l12"; qcom,set = ; regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; qcom,init-voltage = <1800000>; qcom,init-mode = ; qcom,proxy-consumer-enable; diff --git a/qcom/lahaina-thermal-overlay.dtsi b/qcom/lahaina-thermal-overlay.dtsi index 322c971c2ac9..2889f53abedb 100644 --- a/qcom/lahaina-thermal-overlay.dtsi +++ b/qcom/lahaina-thermal-overlay.dtsi @@ -50,6 +50,11 @@ trip = <&b_bcl_lvl0>; cooling-device = <&msm_gpu 2 2>; }; + + vbat_cdsp0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cdsp_sw 2 2>; + }; }; }; @@ -69,6 +74,11 @@ trip = <&b_bcl_lvl1>; cooling-device = <&msm_gpu 4 4>; }; + + vbat_cdsp1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cdsp_sw 4 4>; + }; }; }; @@ -79,6 +89,12 @@ cooling-device = <&msm_gpu THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + vbat_cdsp2 { + trip = <&b_bcl_lvl2>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; }; }; @@ -99,6 +115,11 @@ trip = <&c_bcl_lvl0>; cooling-device = <&msm_gpu 2 2>; }; + + vph_cdsp0 { + trip = <&c_bcl_lvl0>; + cooling-device = <&cdsp_sw 2 2>; + }; }; }; @@ -119,6 +140,11 @@ trip = <&c_bcl_lvl1>; cooling-device = <&msm_gpu 4 4>; }; + + vph_cdsp1 { + trip = <&c_bcl_lvl1>; + cooling-device = <&cdsp_sw 4 4>; + }; }; }; @@ -130,6 +156,12 @@ cooling-device = <&msm_gpu THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + vph_cdsp2 { + trip = <&c_bcl_lvl2>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; }; }; diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi index 3dbb450d5b00..4dea98aea115 100644 --- a/qcom/lahaina-thermal.dtsi +++ b/qcom/lahaina-thermal.dtsi @@ -974,14 +974,13 @@ }; }; - gpuss-max-step { + gpuss-0-step { polling-delay-passive = <10>; - polling-delay = <100>; + polling-delay = <0>; thermal-governor = "step_wise"; - thermal-sensors = <&tsens1 1>, <&tsens1 2>; - sensor-aggregation = ; + thermal-sensors = <&tsens1 1>; trips { - gpuss_config: active-config0 { + gpuss0_config: active-config0 { temperature = <95000>; hysteresis = <0>; type = "passive"; @@ -990,7 +989,29 @@ cooling-maps { gpu_cdev { - trip = <&gpuss_config>; + trip = <&gpuss0_config>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + gpuss-1-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 2>; + trips { + gpuss1_config: active-config0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + gpu_cdev { + trip = <&gpuss1_config>; cooling-device = <&msm_gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; diff --git a/qcom/lahaina-usb.dtsi b/qcom/lahaina-usb.dtsi index d07743548705..dfb0f8d3899b 100644 --- a/qcom/lahaina-usb.dtsi +++ b/qcom/lahaina-usb.dtsi @@ -29,10 +29,9 @@ <&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, <&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&clock_gcc GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON>; + <&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>; clock-names = "core_clk", "iface_clk", "bus_aggr_clk", - "utmi_clk", "sleep_clk", "core_csr_clk"; + "utmi_clk", "sleep_clk"; resets = <&clock_gcc GCC_USB30_PRIM_BCR>; reset-names = "core_reset"; @@ -365,10 +364,9 @@ <&clock_gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, <&clock_gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, <&clock_gcc GCC_USB30_SEC_SLEEP_CLK>, - <&clock_gcc GCC_USB3_SEC_CLKREF_EN>, - <&clock_gcc GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON>; + <&clock_gcc GCC_USB3_SEC_CLKREF_EN>; clock-names = "core_clk", "iface_clk", "bus_aggr_clk", - "utmi_clk", "sleep_clk", "xo", "core_csr_clk"; + "utmi_clk", "sleep_clk", "xo"; resets = <&clock_gcc GCC_USB30_SEC_BCR>; reset-names = "core_reset"; diff --git a/qcom/lahaina-v2-gpu.dtsi b/qcom/lahaina-v2-gpu.dtsi index 102735787d69..55666de74e94 100644 --- a/qcom/lahaina-v2-gpu.dtsi +++ b/qcom/lahaina-v2-gpu.dtsi @@ -1,7 +1,7 @@ &msm_gpu { qcom,chipid = <0x06060001>; - qcom,initial-pwrlevel = <5>; + qcom,initial-pwrlevel = <9>; /* Power levels */ qcom,gpu-pwrlevels { @@ -12,6 +12,38 @@ qcom,gpu-pwrlevel@0 { reg = <0>; + qcom,gpu-freq = <840000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882c5ffd>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <778000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82d5ffd>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <738000000>; qcom,level = ; @@ -22,10 +54,12 @@ qcom,bus-freq-ddr8 = <11>; qcom,bus-min-ddr8 = <11>; qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82d5ffd>; }; - qcom,gpu-pwrlevel@1 { - reg = <1>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <676000000>; qcom,level = ; @@ -36,10 +70,12 @@ qcom,bus-freq-ddr8 = <10>; qcom,bus-min-ddr8 = <10>; qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82c5ffd>; }; - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <608000000>; qcom,level = ; @@ -50,10 +86,12 @@ qcom,bus-freq-ddr8 = <7>; qcom,bus-min-ddr8 = <7>; qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882d5ffd>; }; - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <540000000>; qcom,level = ; @@ -64,10 +102,26 @@ qcom,bus-freq-ddr8 = <7>; qcom,bus-min-ddr8 = <7>; qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0xa82d5ffd>; }; - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <491000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + }; + + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <443000000>; qcom,level = ; @@ -76,12 +130,26 @@ qcom,bus-max-ddr7 = <10>; qcom,bus-freq-ddr8 = <7>; - qcom,bus-min-ddr8 = <6>; - qcom,bus-max-ddr8 = <9>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; }; - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <379000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + }; + + qcom,gpu-pwrlevel@9 { + reg = <9>; qcom,gpu-freq = <315000000>; qcom,level = ; @@ -91,7 +159,7 @@ qcom,bus-freq-ddr8 = <2>; qcom,bus-min-ddr8 = <2>; - qcom,bus-max-ddr8 = <8>; + qcom,bus-max-ddr8 = <7>; }; }; }; diff --git a/qcom/lahaina-v2.dtsi b/qcom/lahaina-v2.dtsi index f2106bdc6f3f..1391441bb5d8 100644 --- a/qcom/lahaina-v2.dtsi +++ b/qcom/lahaina-v2.dtsi @@ -43,7 +43,7 @@ }; &pcie0 { - qcom,pcie-phy-ver = <20099>; + qcom,pcie-phy-ver = <20100>; qcom,phy-sequence = <0x0240 0x03 0x0 0x0094 0x08 0x0 0x0154 0x34 0x0 @@ -107,6 +107,7 @@ 0x1050 0x08 0x0 0x1044 0xf0 0x0 0x11a4 0x38 0x0 + 0x10cc 0xf0 0x0 0x0694 0x00 0x0 0x0654 0x00 0x0 0x06a8 0x0f 0x0 @@ -160,7 +161,7 @@ &cpu7_l3_computemon { qcom,core-dev-table = - < 2592000 300000000 >, + < 2035200 300000000 >, < 2814600 1593600000 >; }; @@ -275,3 +276,9 @@ < 1881600 1 >, < 2841600 2 >; }; + +&cpu7_qoslatmon { + qcom,core-dev-table = + < 2035200 1 >, + < 2841600 2 >; +}; diff --git a/qcom/lahaina-vm-cdp.dts b/qcom/lahaina-vm-cdp.dts new file mode 100644 index 000000000000..74e1fc3fdae7 --- /dev/null +++ b/qcom/lahaina-vm-cdp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "lahaina-vm.dtsi" +#include "lahaina-vm-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lahaina SVM CDP"; + compatible = "qcom,lahaina-cdp", "qcom,lahaina", "qcom,cdp"; + qcom,board-id = <0x10001 0>; +}; diff --git a/qcom/lahaina-vm-cdp.dtsi b/qcom/lahaina-vm-cdp.dtsi new file mode 100644 index 000000000000..e62004ae5e1e --- /dev/null +++ b/qcom/lahaina-vm-cdp.dtsi @@ -0,0 +1 @@ +/*#include "display/lahaina-sde-display-cdp.dtsi"*/ diff --git a/qcom/trustedvm-ion.dtsi b/qcom/lahaina-vm-ion.dtsi similarity index 100% rename from qcom/trustedvm-ion.dtsi rename to qcom/lahaina-vm-ion.dtsi diff --git a/qcom/lahaina-vm-mtp.dts b/qcom/lahaina-vm-mtp.dts new file mode 100644 index 000000000000..816a8fc0d9df --- /dev/null +++ b/qcom/lahaina-vm-mtp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "lahaina-vm.dtsi" +#include "lahaina-vm-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lahaina SVM MTP"; + compatible = "qcom,lahaina-mtp", "qcom,lahaina", "qcom,mtp"; + qcom,board-id = <0x10008 0>; +}; diff --git a/qcom/lahaina-vm-mtp.dtsi b/qcom/lahaina-vm-mtp.dtsi new file mode 100644 index 000000000000..7411556ed73b --- /dev/null +++ b/qcom/lahaina-vm-mtp.dtsi @@ -0,0 +1 @@ +/*#include "display/lahaina-sde-display-mtp.dtsi"*/ diff --git a/qcom/lahaina-vm-qrd.dts b/qcom/lahaina-vm-qrd.dts new file mode 100644 index 000000000000..4c01845cfd2c --- /dev/null +++ b/qcom/lahaina-vm-qrd.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "lahaina-vm.dtsi" +#include "lahaina-vm-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lahaina SVM QRD"; + compatible = "qcom,lahaina-qrd", "qcom,lahaina", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/lahaina-vm-qrd.dtsi b/qcom/lahaina-vm-qrd.dtsi new file mode 100644 index 000000000000..ed306e6a6f78 --- /dev/null +++ b/qcom/lahaina-vm-qrd.dtsi @@ -0,0 +1 @@ +/*#include "display/lahaina-sde-display-qrd.dtsi"*/ diff --git a/qcom/trustedvm.dtsi b/qcom/lahaina-vm.dtsi similarity index 81% rename from qcom/trustedvm.dtsi rename to qcom/lahaina-vm.dtsi index ae677e856060..c7e230103dee 100644 --- a/qcom/trustedvm.dtsi +++ b/qcom/lahaina-vm.dtsi @@ -6,6 +6,7 @@ / { #address-cells = <0x2>; #size-cells = <0x2>; + qcom,msm-id = <415 0x10000>; interrupt-parent = <&vgic>; qcom-mem-buf { @@ -14,7 +15,7 @@ }; chosen { - bootargs = "nokaslr root=/dev/ram rw init=/init console=hvc0 loglevel=8"; + bootargs = "nokaslr no_console_suspend root=/dev/ram rw init=/init console=hvc0 loglevel=8"; linux,initrd-start = <0x2a900000>; linux,initrd-end = <0x2b100000>; /* 8 MB */ kaslr-seed = <0xfeedbeef 0xc0def00d>; @@ -29,7 +30,8 @@ reg = <0x0 0x0>; device_type = "cpu"; enable-method = "psci"; - cpu-idle-states = <0x2>; + cpu-idle-states = <&CPU_PWR_DWN + &CLUSTER_PWR_DWN>; }; CPU1: cpu@100 { @@ -37,79 +39,30 @@ reg = <0x0 0x100>; device_type = "cpu"; enable-method = "psci"; - cpu-idle-states = <0x2>; - }; - - CPU2: cpu@200 { - compatible = "arm,armv8"; - reg = <0x0 0x200>; - device_type = "cpu"; - enable-method = "psci"; - cpu-idle-states = <0x2>; - }; - - CPU3: cpu@300 { - compatible = "arm,armv8"; - reg = <0x0 0x300>; - device_type = "cpu"; - enable-method = "psci"; - cpu-idle-states = <0x2>; - }; - - CPU4: cpu@400 { - compatible = "arm,armv8"; - reg = <0x0 0x400>; - device_type = "cpu"; - enable-method = "psci"; - cpu-idle-states = <0x2>; - }; - - CPU5: cpu@500 { - compatible = "arm,armv8"; - reg = <0x0 0x500>; - device_type = "cpu"; - enable-method = "psci"; - cpu-idle-states = <0x2>; - }; - - CPU6: cpu@600 { - compatible = "arm,armv8"; - reg = <0x0 0x600>; - device_type = "cpu"; - enable-method = "psci"; - cpu-idle-states = <0x2>; - }; - - CPU7: cpu@700 { - compatible = "arm,armv8"; - reg = <0x0 0x700>; - device_type = "cpu"; - enable-method = "psci"; - cpu-idle-states = <0x2>; + cpu-idle-states = <&CPU_PWR_DWN + &CLUSTER_PWR_DWN>; }; }; - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - qrtr_shbuf: qrtr-shmem { - no-map; - reg = <0x0 0x2fef7000 0x0 0x9000>; - qcom,label = <3>; + idle-states { + CPU_PWR_DWN: c4 { /* Using Gold C4 latencies */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <702>; + exit-latency-us = <1061>; + min-residency-us = <4488>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; }; - chan0_shbuf: neuron-block@0 { - no-map; - reg = <0x0 0x2ff00000 0x0 0x80000>; - qcom,label = <1>; - }; - - chan1_shbuf: neuron-block@1 { - no-map; - reg = <0x0 0x2ff80000 0x0 0x80000>; - qcom,label = <2>; + CLUSTER_PWR_DWN: d4 { /* C4+D4 */ + compatible = "arm,idle-state"; + idle-state-name = "l3-pc"; + entry-latency-us = <2752>; + exit-latency-us = <3048>; + min-residency-us = <6118>; + arm,psci-suspend-param = <0x40000044>; + local-timer-stop; }; }; @@ -133,7 +86,6 @@ class = "message-queue"; direction = "send"; max-size = <0 65536>; - shared-buffer = <&chan0_shbuf>; haven-label = <1>; }; @@ -143,7 +95,6 @@ class = "message-queue"; direction = "receive"; max-size = <0 65536>; - shared-buffer = <&chan1_shbuf>; haven-label = <2>; }; }; @@ -151,7 +102,6 @@ qrtr-haven { compatible = "qcom,qrtr-haven"; haven-label = <3>; - shared-buffer = <&qrtr_shbuf>; }; qcom,vm-config { @@ -189,8 +139,8 @@ vcpus { config = "/cpus"; affinity = "static"; - affinity-map = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7>; - sched-priority = < (-1) >; /* relative to PVM */ + affinity-map = <0x4 0x5>; + sched-priority = <0>; /* relative to PVM */ sched-timeslice = <2000>; /* in ms */ }; @@ -384,7 +334,7 @@ }; }; -#include "trustedvm-ion.dtsi" +#include "lahaina-vm-ion.dtsi" #include "display/trustedvm-lahaina-sde.dtsi" #include "display/trustedvm-lahaina-sde-display.dtsi" #include "display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi" diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index a5ee90add681..92cbfe27c466 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -311,6 +311,11 @@ reg = <0x0 0x80860000 0x0 0x20000>; }; + reserved_xbl_uefi_log: res_xbl_uefi_log_region@80880000 { + no-map; + reg = <0x0 0x80880000 0x0 0x14000>; + }; + smem_mem: smem_region@80900000 { no-map; reg = <0x0 0x80900000 0x0 0x200000>; @@ -489,7 +494,7 @@ compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; reusable; - size = <0 0x2c00000>; + size = <0 0x3000000>; }; sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ @@ -2080,6 +2085,11 @@ reg = <0x94c 0xc8>; }; + pil@6dc { + compatible = "qcom,msm-imem-pil-disable-timeout"; + reg = <0x6dc 0x4>; + }; + diag_dload@c8 { compatible = "qcom,msm-imem-diag-dload"; reg = <0xc8 0xc8>; @@ -2174,7 +2184,6 @@ reg = <0x7040000 0x1000>; reg-names = "etm-base"; - status = "disabled"; clocks = <&clock_aop QDSS_CLK>; clock-names = "core_clk"; @@ -2186,7 +2195,6 @@ reg = <0x7140000 0x1000>; reg-names = "etm-base"; - status = "disabled"; clocks = <&clock_aop QDSS_CLK>; clock-names = "core_clk"; @@ -2198,7 +2206,6 @@ reg = <0x7240000 0x1000>; reg-names = "etm-base"; - status = "disabled"; clocks = <&clock_aop QDSS_CLK>; clock-names = "core_clk"; @@ -2210,7 +2217,6 @@ reg = <0x7340000 0x1000>; reg-names = "etm-base"; - status = "disabled"; clocks = <&clock_aop QDSS_CLK>; clock-names = "core_clk"; @@ -2222,7 +2228,6 @@ reg = <0x7440000 0x1000>; reg-names = "etm-base"; - status = "disabled"; clocks = <&clock_aop QDSS_CLK>; clock-names = "core_clk"; @@ -2234,7 +2239,6 @@ reg = <0x7540000 0x1000>; reg-names = "etm-base"; - status = "disabled"; clocks = <&clock_aop QDSS_CLK>; clock-names = "core_clk"; @@ -2246,7 +2250,6 @@ reg = <0x7640000 0x1000>; reg-names = "etm-base"; - status = "disabled"; clocks = <&clock_aop QDSS_CLK>; clock-names = "core_clk"; @@ -2258,7 +2261,6 @@ reg = <0x7740000 0x1000>; reg-names = "etm-base"; - status = "disabled"; clocks = <&clock_aop QDSS_CLK>; clock-names = "core_clk"; @@ -2764,7 +2766,7 @@ qcom,tcs-config = , , , - ; + ; apps_bcm_voter: bcm_voter { compatible = "qcom,bcm-voter"; @@ -3207,6 +3209,16 @@ qcom,iommu-dma = "bypass"; status = "disabled"; + + qos0 { + mask = <0x0f>; + vote = <44>; + }; + + qos1 { + mask = <0xf0>; + vote = <44>; + }; }; kryo-erp { @@ -3851,6 +3863,13 @@ mboxes = <&qmp_aop 0>; }; + cpu7_cpu_ddr_qoslatfloor: qcom,cpu7-cpu-ddr-qoslatfloor { + compatible = "qcom,devfreq-qoslat"; + governor = "mem_latency"; + operating-points-v2 = <&qoslat_opp_table>; + mboxes = <&qmp_aop 0>; + }; + cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl { qcom,core-dev-table = < 300000 300000000 >, @@ -3988,9 +4007,10 @@ cpu7_l3_computemon: qcom,cpu7-l3-computemon { compatible = "qcom,arm-compute-mon"; + qcom,cpulist = <&CPU7>; qcom,target-dev = <&cpu7_cpu_l3_latfloor>; qcom,core-dev-table = - < 2304000 300000000 >, + < 1996800 300000000 >, < 2400000 1516800000 >; }; @@ -4098,18 +4118,23 @@ < 300000 1 >, < 3000000 2 >; }; + + cpu7_qoslatmon: qcom,cpu7-qoslatmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,target-dev = <&cpu7_cpu_ddr_qoslatfloor>; + qcom,cachemiss-ev = <0x1000>; + qcom,core-dev-table = + < 1996800 1 >, + < 2400000 2 >; + }; }; wdog: qcom,wdt@17c10000{ compatible = "qcom,msm-watchdog"; reg = <0x17c10000 0x1000>; reg-names = "wdt-base"; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, - <0 1 IRQ_TYPE_LEVEL_HIGH>; - qcom,bark-time = <11000>; - qcom,pet-time = <9360>; - qcom,ipi-ping; - qcom,wakeup-enable; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; }; tsens0:tsens@c222000 { @@ -4235,6 +4260,7 @@ qcom,slpi_qrtr { qcom,glink-channels = "IPCRTR"; + qcom,net-id = <2>; qcom,low-latency; qcom,intents = <0x800 5 0x2000 3 @@ -5005,6 +5031,26 @@ qcom,dump-size = <0x1000>; qcom,dump-id = <0x104>; }; + + LLCC_1: llcc_1_dcache { + qcom,dump-size = <0x1141c0>; + qcom,dump-id = <0x140>; + }; + + LLCC_2: llcc_2_dcache { + qcom,dump-size = <0x1141c0>; + qcom,dump-id = <0x141>; + }; + + LLCC_3: llcc_3_dcache { + qcom,dump-size = <0x1141c0>; + qcom,dump-id = <0x142>; + }; + + LLCC_4: llcc_4_dcache { + qcom,dump-size = <0x1141c0>; + qcom,dump-id = <0x143>; + }; }; qcom,ssc@5c00000 { @@ -5128,9 +5174,7 @@ qcom,hlos-ce-hw-instance = <0>; qcom,qsee-ce-hw-instance = <0>; qcom,disk-encrypt-pipe-pair = <2>; - qcom,support-fde; qcom,no-clock-support; - qcom,fde-key-size; qcom,appsbl-qseecom-support; qcom,commonlib64-loaded-by-uefi; qcom,qsee-reentrancy-support = <2>; @@ -5397,7 +5441,7 @@ mhi,num-elements = <32>; mhi,intmod = <0>; mhi,msi = <1>; - mhi,priority = <1>; + mhi,priority = <0>; mhi,brstmode = <2>; mhi,data-type = <1>; }; diff --git a/qcom/lahainap-v2.dtsi b/qcom/lahainap-v2.dtsi index c6f6b0305032..dd53c27b15b6 100644 --- a/qcom/lahainap-v2.dtsi +++ b/qcom/lahainap-v2.dtsi @@ -6,10 +6,6 @@ qcom,msm-id = <439 0x20000>; }; -&pil_modem { - status = "disabled"; -}; - &ipa_hw { status = "disabled"; }; diff --git a/qcom/lahainap.dtsi b/qcom/lahainap.dtsi index 4f3acd3069f6..dee1f6a43c26 100644 --- a/qcom/lahainap.dtsi +++ b/qcom/lahainap.dtsi @@ -6,10 +6,6 @@ qcom,msm-id = <439 0x10000>; }; -&pil_modem { - status = "disabled"; -}; - &ipa_hw { status = "disabled"; }; diff --git a/qcom/msm-arm-smmu-holi.dtsi b/qcom/msm-arm-smmu-holi.dtsi index 9f9cf20f453e..20343e67832b 100644 --- a/qcom/msm-arm-smmu-holi.dtsi +++ b/qcom/msm-arm-smmu-holi.dtsi @@ -120,10 +120,12 @@ qcom,active-only; qcom,actlr = - /* For rt TBU +3 deep PF */ + /* For rt TBU camera +3 deep PF */ <0x800 0x3ff 0x103>, /* For nrt TBU +3 deep PF */ - <0xc00 0x3ff 0x103>; + <0xc00 0x3ff 0x103>, + /* For anoc_1 TBU disable PF */ + <0x0 0x3ff 0x001>; anoc_1_tbu: anoc_1_tbu@0c705000 { compatible = "qcom,qsmmuv500-tbu"; diff --git a/qcom/msm-arm-smmu-lahaina.dtsi b/qcom/msm-arm-smmu-lahaina.dtsi index 549022958c79..de6054d5d612 100644 --- a/qcom/msm-arm-smmu-lahaina.dtsi +++ b/qcom/msm-arm-smmu-lahaina.dtsi @@ -20,10 +20,19 @@ clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, <&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>, - <&clock_gpucc GPU_CC_AHB_CLK>; + <&clock_gpucc GPU_CC_AHB_CLK>, + <&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&clock_gpucc GPU_CC_CX_GMU_CLK>, + <&clock_gpucc GPU_CC_HUB_CX_INT_CLK>, + <&clock_gpucc GPU_CC_HUB_AON_CLK>; + clock-names = "gcc_gpu_memnoc_gfx", "gcc_gpu_snoc_dvm_gfx", - "gpu_cc_ahb"; + "gpu_cc_ahb", + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_hub_aon_clk"; interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>; diff --git a/qcom/msm-arm-smmu-sdxlemur.dtsi b/qcom/msm-arm-smmu-sdxlemur.dtsi index 47e46d630975..d173665338c3 100644 --- a/qcom/msm-arm-smmu-sdxlemur.dtsi +++ b/qcom/msm-arm-smmu-sdxlemur.dtsi @@ -47,8 +47,8 @@ , ; - interconnects = <&system_noc MASTER_APPSS_PROC - &mem_noc SLAVE_IMEM_CFG>; + interconnects = <&mem_noc MASTER_APPSS_PROC + &system_noc SLAVE_IMEM_CFG>; qcom,active-only; periph_tbu: periph_tbu@15045000 { @@ -57,8 +57,8 @@ <0x15042200 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x0 0x400>; - interconnects = <&system_noc MASTER_APPSS_PROC - &mem_noc SLAVE_IMEM_CFG>; + interconnects = <&mem_noc MASTER_APPSS_PROC + &system_noc SLAVE_IMEM_CFG>; qcom,active-only; }; @@ -68,8 +68,8 @@ <0x15042208 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x400 0x400>; - interconnects = <&system_noc MASTER_APPSS_PROC - &mem_noc SLAVE_IMEM_CFG>; + interconnects = <&mem_noc MASTER_APPSS_PROC + &system_noc SLAVE_IMEM_CFG>; qcom,active-only; }; }; diff --git a/qcom/msm-arm-smmu-shima.dtsi b/qcom/msm-arm-smmu-shima.dtsi index f6b9eceb3008..869521cf883e 100644 --- a/qcom/msm-arm-smmu-shima.dtsi +++ b/qcom/msm-arm-smmu-shima.dtsi @@ -20,11 +20,18 @@ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>, - <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + clock-names = "gcc_gpu_memnoc_gfx", "gcc_gpu_snoc_dvm_gfx", "gpu_cc_ahb", - "gpu_cc_hlos1_vote_gpu_smmu_clk"; + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_hub_aon_clk"; interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>; @@ -333,7 +340,6 @@ }; kgsl_iommu_coherent_test_device { - status = "disabled"; compatible = "iommu-debug-test"; iommus = <&kgsl_smmu 0x407 0>; qcom,iommu-dma = "disabled"; diff --git a/qcom/pm6150l.dtsi b/qcom/pm6150l.dtsi index ab066a734d02..c5028363e7e9 100644 --- a/qcom/pm6150l.dtsi +++ b/qcom/pm6150l.dtsi @@ -87,7 +87,7 @@ compatible = "qcom,adc-tm5"; reg = <0x3500>; interrupts = <0x4 0x35 0x0 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "thr-int-en"; + interrupt-names = "threshold"; #address-cells = <1>; #size-cells = <0>; #thermal-sensor-cells = <1>; @@ -283,7 +283,7 @@ pm6150l_lpg: qcom,pwms@b100 { compatible = "qcom,pwm-lpg"; - reg = <0xb100 0x300>, <0xb000 0x100>; + reg = <0xb100>, <0xb000>; reg-names = "lpg-base", "lut-base"; #pwm-cells = <2>; qcom,num-lpg-channels = <3>; @@ -383,7 +383,7 @@ }; &thermal_zones { - pm6150l-tz { + pm6150l_tz { polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "step_wise"; diff --git a/qcom/pm7250b.dtsi b/qcom/pm7250b.dtsi index bc0711644daf..12a626a950a8 100644 --- a/qcom/pm7250b.dtsi +++ b/qcom/pm7250b.dtsi @@ -15,16 +15,203 @@ #address-cells = <1>; #size-cells = <0>; - pm7250b_revid: qcom,revid@100 { - compatible = "qcom,qpnp-revid"; - reg = <0x100>; - }; - qcom,power-on@800 { compatible = "qcom,qpnp-power-on"; reg = <0x800>; }; + pm7250b_charger: qcom,qpnp-smb5 { + compatible = "qcom,pm7250b-smb5"; + #address-cells = <1>; + #size-cells = <0>; + #cooling-cells = <2>; + + qcom,thermal-mitigation = <5400000 4500000 4000000 + 3500000 3000000 2500000 2000000 1500000 + 1000000 500000>; + + qcom,chgr@1000 { + reg = <0x1000>; + interrupts = + <0x2 0x10 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x4 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x5 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "chgr-error", + "chg-state-change", + "step-chg-state-change", + "step-chg-soc-update-fail", + "step-chg-soc-update-req", + "fg-fvcal-qualified", + "vph-alarm", + "vph-drop-prechg"; + }; + + qcom,dcdc@1100 { + reg = <0x1100>; + interrupts = + <0x2 0x11 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x11 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x11 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x11 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x11 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x11 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x11 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x11 0x7 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "otg-fail", + "otg-oc-disable-sw", + "otg-oc-hiccup", + "bsm-active", + "high-duty-cycle", + "input-current-limiting", + "concurrent-mode-disable", + "switcher-power-ok"; + }; + + qcom,batif@1200 { + reg = <0x1200>; + interrupts = + <0x2 0x12 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x6 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x7 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "bat-temp", + "bat-ov", + "bat-low", + "bat-therm-or-id-missing", + "bat-terminal-missing", + "buck-oc", + "vph-ov"; + }; + + qcom,usb@1300 { + reg = <0x1300>; + interrupts = + <0x2 0x13 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x13 0x7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "usbin-collapse", + "usbin-vashdn", + "usbin-uv", + "usbin-ov", + "usbin-plugin", + "usbin-revi-change", + "usbin-src-change", + "usbin-icl-change"; + }; + + qcom,dc@1400 { + reg = <0x1400>; + interrupts = + <0x2 0x14 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x14 0x7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dcin-vashdn", + "dcin-uv", + "dcin-ov", + "dcin-plugin", + "dcin-revi", + "dcin-pon", + "dcin-en"; + }; + + qcom,typec@1500 { + reg = <0x1500>; + interrupts = + <0x2 0x15 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x4 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x5 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "typec-or-rid-detect-change", + "typec-vpd-detect", + "typec-cc-state-change", + "typec-vconn-oc", + "typec-vbus-change", + "typec-attach-detach", + "typec-legacy-cable-detect", + "typec-try-snk-src-detect"; + }; + + qcom,misc@1600 { + reg = <0x1600>; + interrupts = + <0x2 0x16 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x16 0x5 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog-snarl", + "wdog-bark", + "aicl-fail", + "aicl-done", + "smb-en", + "imp-trigger", + "temp-change", + "temp-change-smb"; + }; + + qcom,chg-sdam@b000 { + reg = <0xb000>; + }; + }; + + pm7250b_qg: qpnp,qg { + compatible = "qcom,pm7250b-qg"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,vbatt-cutoff-mv = <3200>; + qcom,vbatt-low-mv = <3300>; + qcom,vbatt-low-cold-mv = <3700>; + qcom,vbatt-empty-mv = <3000>; + qcom,vbatt-empty-cold-mv = <3000>; + qcom,s3-entry-fifo-length = <2>; + + qcom,qgauge@4800 { + status = "okay"; + reg = <0x4800>; + interrupts = + <0x2 0x48 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x48 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x48 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x48 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x48 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "qg-batt-missing", + "qg-vbat-low", + "qg-vbat-empty", + "qg-fifo-done", + "qg-good-ocv"; + }; + + qcom,qg-sdam@b100 { + status = "okay"; + reg = <0xb100>; + }; + }; + pm7250b_tz: qcom,temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; @@ -161,7 +348,7 @@ compatible = "qcom,adc-tm5"; reg = <0x3500>; interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "thr-int-en"; + interrupt-names = "threshold"; #address-cells = <1>; #size-cells = <0>; #thermal-sensor-cells = <1>; @@ -192,6 +379,32 @@ interrupt-controller; #interrupt-cells = <2>; }; + + pm7250b_pdphy: qcom,usb-pdphy@1700 { + compatible = "qcom,qpnp-pdphy"; + reg = <0x1700 0x100>; + interrupts = <0x2 0x17 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x4 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x5 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "sig-tx", + "sig-rx", + "msg-tx", + "msg-rx", + "msg-tx-failed", + "msg-tx-discarded", + "msg-rx-discarded", + "fr-swap"; + + qcom,default-sink-caps = <5000 3000>, /* 5V @ 3A */ + <9000 3000>, /* 9V @ 3A */ + <12000 2250>; /* 12V @ 2.25A */ + }; }; qcom,pm7250b@3 { @@ -210,7 +423,7 @@ }; &thermal_zones { - pm7250b-tz { + pm7250b_tz { polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "step_wise"; diff --git a/qcom/pm8350b.dtsi b/qcom/pm8350b.dtsi index 500fc5a2aff4..aa966642e70e 100644 --- a/qcom/pm8350b.dtsi +++ b/qcom/pm8350b.dtsi @@ -251,7 +251,7 @@ trips { ibat_lvl0:ibat-lvl0 { - temperature = <4500>; + temperature = <6000>; hysteresis = <200>; type = "passive"; }; @@ -266,7 +266,7 @@ trips { ibat_lvl1:ibat-lvl1 { - temperature = <5000>; + temperature = <7500>; hysteresis = <200>; type = "passive"; }; diff --git a/qcom/pmk8350.dtsi b/qcom/pmk8350.dtsi index e6caf85f2752..164366a0734b 100644 --- a/qcom/pmk8350.dtsi +++ b/qcom/pmk8350.dtsi @@ -199,6 +199,11 @@ }; }; + pmk8350_sdam_5: sdam@7400 { + compatible = "qcom,spmi-sdam"; + reg = <0x7400>; + }; + pmk8350_sdam_13: sdam@7c00 { compatible = "qcom,spmi-sdam"; reg = <0x7c00>; diff --git a/qcom/pmx65.dtsi b/qcom/pmx65.dtsi new file mode 100644 index 000000000000..813eed17ef68 --- /dev/null +++ b/qcom/pmx65.dtsi @@ -0,0 +1,67 @@ +#include +#include + +&spmi_bus { + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pmx65@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmx65_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmx65_pwm: pwms@e800 { + compatible = "qcom,pwm-lpg"; + reg = <0xe800>; + reg-names = "lpg-base"; + #pwm-cells = <2>; + qcom,num-lpg-channels = <4>; + }; + + pmx65_gpios: pinctrl@8800 { + compatible = "qcom,pmx65-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&thermal_zones { + pmx65_temp_alarm: pmx65_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pmx65_tz>; + + trips { + pmx65_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pmx65_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + + pmx65_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; diff --git a/qcom/qg-batterydata-alium-3600mah.dtsi b/qcom/qg-batterydata-alium-3600mah.dtsi new file mode 100644 index 000000000000..051f64164fb2 --- /dev/null +++ b/qcom/qg-batterydata-alium-3600mah.dtsi @@ -0,0 +1,1035 @@ +qcom,alium_860_89032_0000_3600mAh { + /* Alium_860_89032_0000_3600mAh_averaged_MasterSlave_Jun15th2018 */ + qcom,max-voltage-uv = <4350000>; + qcom,fg-cc-cv-threshold-uv = <4340000>; + qcom,fastchg-current-ma = <5400>; + qcom,batt-id-kohm = <107>; + qcom,battery-beta = <4250>; + qcom,battery-therm-kohm = <100>; + qcom,battery-type = "Alium_860_89032_0000_3600mAh_Jun15th2018"; + qcom,qg-batt-profile-ver = <100>; + + qcom,jeita-fcc-ranges = <0 50 2500000 + 51 400 5400000 + 401 450 2500000>; + qcom,jeita-fv-ranges = <0 50 4250000 + 51 400 4350000 + 401 450 4250000>; + qcom,step-chg-ranges = <3600000 3800000 5400000 + 3800001 4300000 3600000 + 4300001 4350000 2500000>; + qcom,ocv-based-step-chg; + + /* COOL = 5 DegC, WARM = 40 DegC */ + qcom,jeita-soft-thresholds = <0x5314 0x25e3>; + /* COLD = 0 DegC, HOT = 45 DegC */ + qcom,jeita-hard-thresholds = <0x58cd 0x20b8>; + /* COOL hys = 8 DegC, WARM hys = 37 DegC */ + qcom,jeita-soft-hys-thresholds = <0x4f5e 0x2943>; + qcom,jeita-soft-fcc-ua = <2500000 2500000>; + qcom,jeita-soft-fv-uv = <4250000 4250000>; + + qcom,fcc1-temp-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-data = <3426 3519 3581 3613 3630>; + }; + + qcom,fcc2-temp-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-data = <3546 3576 3586 3588 3583 3583>; + }; + + qcom,pc-temp-v1-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <43078 43267 43365 43394 43399>, + <42839 43052 43147 43186 43196>, + <42609 42823 42920 42964 42981>, + <42392 42591 42693 42738 42759>, + <42186 42370 42469 42513 42535>, + <41983 42159 42248 42289 42310>, + <41776 41953 42032 42066 42085>, + <41565 41745 41820 41847 41863>, + <41376 41534 41607 41630 41645>, + <41226 41338 41393 41412 41426>, + <41086 41189 41206 41205 41212>, + <40873 41057 41063 41032 41014>, + <40523 40858 40918 40878 40833>, + <40155 40509 40680 40678 40639>, + <39917 40145 40325 40390 40407>, + <39757 39925 40039 40116 40180>, + <39638 39781 39894 39960 40010>, + <39541 39669 39779 39850 39877>, + <39455 39579 39646 39699 39715>, + <39364 39489 39487 39469 39489>, + <39266 39366 39306 39235 39257>, + <39165 39210 39096 39058 39072>, + <39060 39042 38900 38912 38919>, + <38955 38854 38767 38784 38785>, + <38859 38675 38671 38668 38668>, + <38773 38551 38581 38562 38562>, + <38692 38462 38490 38466 38462>, + <38619 38394 38403 38377 38369>, + <38552 38343 38327 38296 38283>, + <38491 38301 38257 38222 38203>, + <38439 38261 38195 38156 38132>, + <38392 38224 38142 38097 38067>, + <38348 38190 38095 38043 38010>, + <38306 38161 38052 37989 37952>, + <38265 38135 38015 37938 37895>, + <38223 38102 37976 37886 37836>, + <38181 38066 37935 37830 37771>, + <38128 38020 37890 37771 37701>, + <38054 37950 37823 37699 37623>, + <37964 37850 37727 37613 37538>, + <37862 37740 37617 37512 37439>, + <37739 37617 37494 37390 37318>, + <37601 37487 37361 37256 37185>, + <37448 37354 37221 37119 37052>, + <37327 37238 37120 37019 36955>, + <37241 37161 37057 36960 36898>, + <37209 37134 37035 36943 36881>, + <37182 37113 37018 36927 36865>, + <37146 37086 36991 36896 36829>, + <37036 36976 36855 36724 36634>, + <36712 36636 36510 36372 36278>, + <36253 36181 36056 35916 35819>, + <35673 35600 35476 35330 35231>, + <34889 34811 34685 34533 34429>, + <33644 33573 33450 33289 33175>, + <30000 30000 30000 30000 30000>; + }; + + qcom,pc-temp-v2-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <43405 43390 43380 43360 43310 43280>, + <43003 43066 43092 43094 43055 43033>, + <42659 42770 42823 42839 42808 42792>, + <42388 42505 42573 42597 42570 42556>, + <42183 42269 42342 42369 42341 42328>, + <41972 42046 42121 42146 42116 42104>, + <41647 41828 41907 41928 41893 41879>, + <41314 41618 41700 41715 41674 41657>, + <41242 41409 41488 41499 41455 41438>, + <41295 41194 41265 41273 41232 41219>, + <41338 41020 41073 41079 41031 41013>, + <41030 40918 40949 40949 40883 40839>, + <40301 40831 40837 40833 40747 40674>, + <39816 40619 40617 40621 40542 40474>, + <39553 40056 40158 40222 40214 40226>, + <39352 39574 39750 39893 39934 39999>, + <39187 39400 39544 39757 39792 39836>, + <39047 39287 39391 39659 39684 39694>, + <38903 39154 39240 39507 39524 39512>, + <38748 38998 39093 39269 39281 39271>, + <38600 38840 38951 39039 39045 39043>, + <38473 38688 38809 38867 38872 38870>, + <38360 38541 38673 38723 38728 38725>, + <38269 38408 38551 38598 38603 38600>, + <38195 38289 38441 38488 38492 38488>, + <38132 38186 38339 38387 38390 38385>, + <38076 38102 38245 38293 38296 38290>, + <38026 38033 38158 38206 38208 38200>, + <37976 37977 38077 38128 38127 38118>, + <37929 37931 38001 38058 38053 38043>, + <37882 37891 37932 37991 37985 37974>, + <37835 37852 37869 37926 37922 37912>, + <37786 37815 37814 37863 37863 37853>, + <37734 37776 37764 37798 37793 37778>, + <37680 37735 37722 37732 37704 37675>, + <37621 37692 37680 37666 37610 37565>, + <37558 37641 37633 37602 37526 37469>, + <37492 37582 37583 37538 37448 37384>, + <37421 37513 37524 37470 37374 37308>, + <37348 37429 37450 37396 37302 37235>, + <37274 37332 37362 37312 37222 37156>, + <37201 37229 37261 37208 37121 37056>, + <37130 37124 37145 37082 36997 36933>, + <37054 37029 37028 36964 36881 36820>, + <36966 36949 36952 36902 36830 36771>, + <36849 36873 36903 36875 36801 36743>, + <36768 36823 36880 36854 36784 36726>, + <36666 36763 36850 36823 36756 36699>, + <36509 36668 36775 36740 36671 36604>, + <36284 36467 36557 36486 36422 36338>, + <35954 36107 36161 36071 36005 35919>, + <35477 35597 35626 35539 35482 35397>, + <34808 34917 34941 34844 34796 34717>, + <33818 33942 34003 33928 33918 33830>, + <32458 32548 32795 32808 32663 32496>, + <28619 28270 28017 28020 27984 27930>; + }; + + qcom,pc-temp-z1-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <14545 13238 12041 11680 11593>, + <14523 13183 12045 11678 11602>, + <14531 13174 12043 11685 11612>, + <14535 13182 12039 11687 11616>, + <14547 13186 12035 11688 11618>, + <14571 13181 12033 11688 11620>, + <14591 13164 12034 11689 11623>, + <14582 13150 12035 11692 11626>, + <14551 13149 12037 11694 11629>, + <14518 13154 12041 11697 11631>, + <14486 13152 12045 11701 11634>, + <14452 13134 12047 11704 11639>, + <14403 13116 12047 11707 11643>, + <14352 13102 12043 11707 11644>, + <14318 13096 12036 11705 11644>, + <14291 13097 12033 11703 11644>, + <14262 13097 12036 11707 11647>, + <14226 13100 12042 11714 11653>, + <14194 13111 12052 11721 11659>, + <14181 13129 12065 11726 11663>, + <14179 13150 12076 11731 11667>, + <14186 13172 12085 11736 11672>, + <14195 13188 12093 11741 11676>, + <14207 13195 12101 11745 11681>, + <14215 13201 12109 11751 11686>, + <14220 13210 12116 11756 11690>, + <14223 13222 12123 11760 11695>, + <14228 13229 12130 11764 11699>, + <14239 13234 12137 11768 11703>, + <14255 13242 12143 11772 11707>, + <14279 13250 12149 11776 11711>, + <14302 13257 12154 11780 11716>, + <14310 13265 12160 11784 11720>, + <14314 13278 12166 11789 11725>, + <14320 13297 12174 11794 11729>, + <14343 13315 12181 11799 11733>, + <14395 13333 12189 11802 11736>, + <14443 13346 12197 11804 11738>, + <14481 13351 12202 11807 11740>, + <14512 13353 12205 11809 11741>, + <14514 13357 12209 11811 11742>, + <14472 13369 12217 11813 11744>, + <14451 13384 12223 11815 11745>, + <14446 13399 12224 11816 11746>, + <14433 13385 12228 11817 11746>, + <14447 13396 12231 11819 11746>, + <14441 13396 12232 11819 11745>, + <14440 13403 12233 11819 11746>, + <14431 13399 12239 11820 11747>, + <14460 13394 12241 11824 11750>, + <14470 13423 12251 11830 11755>, + <14506 13430 12275 11839 11760>, + <14485 13470 12295 11850 11770>, + <14544 13512 12338 11868 11782>, + <14544 13512 12338 11868 11782>, + <14544 13512 12338 11868 11782>; + }; + + qcom,pc-temp-z2-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <11192 9778 10257 10603 10910>, + <10253 10813 10276 10490 10558>, + <9726 10534 10287 10428 10436>, + <9734 10061 10282 10413 10412>, + <9760 9938 10269 10392 10406>, + <9775 9923 10261 10380 10404>, + <9777 9909 10257 10375 10408>, + <9772 9898 10258 10370 10412>, + <9765 9890 10262 10368 10412>, + <9755 9884 10265 10372 10421>, + <9746 9880 10259 10375 10444>, + <9750 9878 10227 10382 10452>, + <9766 9881 10199 10414 10451>, + <9772 9895 10216 10429 10452>, + <9752 9907 10260 10399 10450>, + <9717 9910 10282 10371 10439>, + <9701 9914 10279 10383 10449>, + <9697 9923 10269 10418 10506>, + <9693 9949 10295 10465 10551>, + <9686 9981 10388 10545 10559>, + <9673 10014 10446 10602 10559>, + <9662 10050 10419 10553 10531>, + <9655 10080 10371 10429 10478>, + <9649 10101 10339 10379 10444>, + <9631 10116 10316 10398 10420>, + <9588 10124 10303 10422 10405>, + <9554 10131 10300 10409 10406>, + <9540 10135 10301 10384 10415>, + <9483 10134 10309 10376 10426>, + <9426 10131 10329 10376 10445>, + <9408 10130 10351 10380 10472>, + <9395 10131 10373 10399 10506>, + <9386 10133 10396 10437 10548>, + <9378 10137 10420 10474 10594>, + <9372 10146 10446 10506 10651>, + <9368 10154 10463 10533 10695>, + <9374 10162 10468 10556 10712>, + <9380 10167 10471 10580 10722>, + <9389 10171 10479 10593 10733>, + <9398 10176 10491 10596 10745>, + <9397 10178 10497 10597 10753>, + <9384 10169 10490 10609 10755>, + <9380 10140 10483 10625 10759>, + <9386 9964 10481 10631 10781>, + <9324 9926 10454 10642 10811>, + <9305 9932 10438 10669 10808>, + <9287 9948 10463 10697 10858>, + <9289 9933 10557 10698 10889>, + <9274 9965 10622 10758 10917>, + <9278 9923 10533 10711 10837>, + <9316 9884 10462 10634 10693>, + <9326 9807 10425 10609 10671>, + <9285 9724 10395 10535 10591>, + <9245 9615 10285 10458 10500>, + <9245 9615 10285 10458 10500>, + <9245 9615 10285 10458 10500>; + }; + + qcom,pc-temp-z3-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <19525 19431 19373 19383 19355>, + <19784 19494 19408 19370 19350>, + <19920 19574 19438 19372 19351>, + <19937 19651 19450 19380 19356>, + <19918 19673 19455 19382 19359>, + <19895 19676 19456 19383 19362>, + <19884 19677 19454 19381 19362>, + <19879 19677 19451 19376 19359>, + <19877 19680 19448 19372 19355>, + <19874 19682 19446 19372 19353>, + <19872 19668 19440 19372 19352>, + <19877 19628 19423 19367 19352>, + <19894 19610 19400 19355 19349>, + <19909 19638 19406 19350 19345>, + <19892 19671 19439 19363 19347>, + <19843 19665 19457 19379 19351>, + <19796 19628 19436 19373 19348>, + <19760 19594 19408 19356 19338>, + <19726 19567 19407 19352 19335>, + <19697 19550 19425 19366 19342>, + <19672 19554 19438 19379 19351>, + <19654 19573 19439 19379 19357>, + <19644 19591 19439 19374 19361>, + <19636 19603 19437 19373 19362>, + <19628 19612 19434 19380 19360>, + <19619 19613 19433 19386 19358>, + <19607 19611 19439 19383 19356>, + <19596 19607 19445 19378 19354>, + <19583 19601 19446 19374 19352>, + <19567 19594 19444 19369 19350>, + <19549 19588 19442 19365 19348>, + <19530 19583 19439 19362 19345>, + <19514 19578 19434 19360 19342>, + <19499 19571 19431 19359 19338>, + <19486 19563 19429 19358 19334>, + <19479 19557 19426 19358 19332>, + <19483 19551 19422 19358 19332>, + <19491 19546 19418 19357 19334>, + <19513 19542 19415 19356 19334>, + <19535 19539 19414 19351 19331>, + <19526 19535 19412 19347 19329>, + <19496 19530 19410 19347 19330>, + <19483 19519 19408 19347 19330>, + <19481 19451 19404 19347 19331>, + <19372 19379 19382 19344 19327>, + <19345 19348 19360 19337 19320>, + <19337 19340 19358 19328 19312>, + <19339 19335 19342 19326 19312>, + <19316 19318 19331 19324 19309>, + <19320 19317 19352 19335 19324>, + <19371 19345 19355 19339 19331>, + <19418 19350 19357 19342 19332>, + <19442 19348 19353 19346 19335>, + <19464 19360 19359 19349 19340>, + <19464 19360 19359 19349 19340>, + <19464 19360 19359 19349 19340>; + }; + + qcom,pc-temp-z4-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <16385 15501 14962 14712 14715>, + <16621 15491 14959 14790 14777>, + <16602 15456 14922 14802 14786>, + <16518 15370 14881 14784 14773>, + <16384 15265 14843 14759 14750>, + <16241 15178 14812 14736 14726>, + <16119 15106 14786 14721 14710>, + <16009 15051 14764 14710 14700>, + <15894 15008 14752 14704 14694>, + <15746 14969 14746 14701 14689>, + <15604 14928 14744 14698 14685>, + <15557 14895 14744 14693 14681>, + <15579 14889 14745 14687 14673>, + <15600 14901 14749 14689 14670>, + <15554 14908 14754 14704 14683>, + <15436 14889 14752 14715 14696>, + <15339 14846 14732 14699 14686>, + <15282 14813 14713 14669 14663>, + <15245 14793 14712 14671 14662>, + <15230 14781 14722 14728 14708>, + <15221 14780 14742 14778 14758>, + <15217 14783 14794 14782 14763>, + <15221 14793 14846 14777 14751>, + <15227 14842 14846 14766 14737>, + <15232 14904 14815 14739 14722>, + <15237 14918 14783 14717 14709>, + <15244 14915 14759 14707 14700>, + <15250 14910 14740 14702 14693>, + <15262 14895 14729 14697 14687>, + <15275 14872 14722 14693 14682>, + <15283 14853 14717 14690 14677>, + <15290 14837 14715 14686 14673>, + <15294 14821 14714 14682 14670>, + <15292 14806 14713 14682 14669>, + <15285 14792 14713 14684 14672>, + <15265 14778 14712 14686 14677>, + <15218 14764 14710 14689 14683>, + <15171 14753 14707 14691 14689>, + <15100 14750 14704 14691 14691>, + <15036 14748 14701 14691 14688>, + <15028 14745 14698 14690 14685>, + <15035 14740 14695 14688 14684>, + <15033 14741 14690 14685 14683>, + <15011 14800 14682 14681 14680>, + <15037 14827 14679 14667 14668>, + <15046 14838 14675 14645 14644>, + <15051 14840 14669 14641 14637>, + <15043 14842 14681 14633 14624>, + <15056 14851 14689 14629 14622>, + <15040 14847 14670 14638 14636>, + <15003 14839 14678 14645 14640>, + <14990 14846 14681 14646 14645>, + <14996 14862 14691 14647 14646>, + <15017 14877 14695 14650 14646>, + <15017 14877 14695 14650 14646>, + <15017 14877 14695 14650 14646>; + }; + + qcom,pc-temp-z5-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <11068 11690 13464 19085 17868>, + <12016 12370 14843 18209 18510>, + <12567 13373 16287 18434 19041>, + <12767 14431 17166 19331 19871>, + <12906 14953 17644 19970 20772>, + <13043 15275 18035 20553 21985>, + <13254 15589 18448 20812 22838>, + <13520 16021 18878 20763 23075>, + <13787 16665 19253 20832 23069>, + <14074 17170 19532 21287 23403>, + <14425 17078 19373 21540 24108>, + <14893 16220 17894 20839 24888>, + <15428 16083 16100 18925 24832>, + <15715 18342 16976 18223 24189>, + <15770 20589 20553 20659 24472>, + <15797 20502 22513 23616 25498>, + <15834 19565 21295 23828 25788>, + <15830 19061 19385 22969 25708>, + <15750 18918 21990 23440 25684>, + <15580 18870 30436 27428 25707>, + <15309 20532 34653 30469 25746>, + <15057 25755 30884 27232 24220>, + <14852 31080 25218 20500 20766>, + <14649 35866 22212 18547 19399>, + <14406 39481 20440 20518 19854>, + <14102 39590 19963 22400 20596>, + <13801 37343 21441 23200 21434>, + <13549 34779 23939 23840 22513>, + <13290 32437 26091 24203 23750>, + <13021 30286 28345 24605 25226>, + <12746 29196 30150 25017 26620>, + <12479 28629 31211 25585 27804>, + <12282 28181 32038 26640 28805>, + <12126 27688 32872 28101 29029>, + <11990 27267 33745 30291 28636>, + <11896 27207 34089 31579 28289>, + <11945 27442 32771 31455 28513>, + <12049 27808 30864 31087 28942>, + <12350 28315 30537 30322 28828>, + <12671 28953 30633 27821 27284>, + <12642 29117 30687 26060 26101>, + <12299 27717 30577 26308 26287>, + <12208 24781 30313 26635 26505>, + <12309 16408 28848 26643 26112>, + <11428 13096 22891 26468 25271>, + <11198 12322 18301 26248 25109>, + <11112 12144 18213 22490 22887>, + <11116 12041 15832 22757 25790>, + <10935 11705 14733 23506 25696>, + <10976 11757 17791 27597 30144>, + <11440 12275 17295 25361 28944>, + <11648 12197 17311 24873 26253>, + <11657 11966 16067 25059 25290>, + <11600 11884 16052 23410 24581>, + <11600 11884 16052 23410 24581>, + <11600 11884 16052 23410 24581>; + }; + + qcom,pc-temp-z6-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <16538 15406 14813 14639 14611>, + <16749 15432 14830 14667 14637>, + <16795 15447 14830 14674 14643>, + <16769 15440 14820 14671 14641>, + <16699 15411 14805 14663 14634>, + <16612 15372 14791 14653 14625>, + <16540 15333 14779 14645 14619>, + <16482 15307 14768 14638 14613>, + <16423 15289 14762 14634 14608>, + <16352 15271 14759 14633 14606>, + <16282 15242 14755 14632 14604>, + <16243 15204 14746 14628 14603>, + <16229 15190 14734 14620 14598>, + <16213 15202 14738 14617 14595>, + <16158 15216 14756 14631 14602>, + <16064 15204 14764 14643 14610>, + <15984 15167 14745 14634 14604>, + <15930 15138 14722 14613 14590>, + <15887 15120 14722 14612 14588>, + <15858 15110 14737 14646 14613>, + <15836 15113 14757 14675 14640>, + <15826 15129 14785 14678 14644>, + <15826 15150 14807 14675 14644>, + <15831 15182 14806 14671 14642>, + <15836 15213 14793 14664 14635>, + <15841 15221 14782 14658 14628>, + <15846 15221 14776 14653 14623>, + <15850 15220 14772 14648 14620>, + <15854 15214 14769 14645 14617>, + <15856 15204 14766 14641 14614>, + <15856 15196 14763 14638 14611>, + <15856 15188 14761 14635 14608>, + <15855 15180 14760 14632 14605>, + <15853 15174 14759 14632 14604>, + <15851 15168 14759 14633 14604>, + <15851 15164 14758 14634 14604>, + <15853 15160 14756 14636 14607>, + <15855 15157 14754 14637 14611>, + <15855 15157 14752 14637 14612>, + <15854 15158 14751 14634 14610>, + <15851 15158 14750 14632 14608>, + <15842 15157 14749 14631 14608>, + <15832 15156 14747 14631 14607>, + <15821 15148 14743 14630 14607>, + <15777 15126 14731 14621 14600>, + <15764 15120 14719 14609 14585>, + <15763 15114 14716 14602 14578>, + <15759 15116 14713 14598 14572>, + <15757 15111 14711 14595 14570>, + <15765 15116 14716 14605 14584>, + <15777 15136 14723 14612 14591>, + <15805 15152 14732 14616 14594>, + <15840 15173 14739 14621 14598>, + <15893 15213 14754 14628 14605>, + <15893 15213 14754 14628 14605>, + <15893 15213 14754 14628 14605>; + }; + + qcom,pc-temp-y1-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <7598 6764 6071 5440 5223 5179>, + <7604 6767 6083 5439 5222 5181>, + <7616 6772 6090 5438 5222 5182>, + <7629 6778 6094 5436 5222 5184>, + <7640 6782 6096 5435 5223 5185>, + <7645 6784 6096 5434 5223 5187>, + <7644 6784 6092 5434 5224 5187>, + <7642 6784 6086 5434 5226 5188>, + <7635 6781 6085 5435 5228 5189>, + <7612 6774 6088 5436 5229 5190>, + <7594 6768 6090 5437 5231 5192>, + <7603 6766 6086 5437 5232 5193>, + <7624 6767 6080 5437 5234 5195>, + <7644 6772 6081 5438 5236 5197>, + <7668 6789 6096 5445 5241 5202>, + <7683 6807 6107 5453 5244 5204>, + <7674 6820 6111 5455 5244 5205>, + <7655 6831 6115 5458 5245 5205>, + <7640 6832 6116 5460 5246 5206>, + <7626 6817 6114 5461 5248 5209>, + <7619 6805 6114 5464 5251 5212>, + <7638 6807 6125 5468 5255 5216>, + <7673 6815 6139 5472 5259 5219>, + <7681 6821 6141 5477 5262 5223>, + <7680 6824 6136 5481 5265 5226>, + <7684 6828 6135 5485 5267 5230>, + <7689 6840 6144 5489 5270 5234>, + <7692 6860 6155 5494 5274 5237>, + <7690 6871 6158 5499 5277 5240>, + <7672 6876 6162 5505 5280 5242>, + <7648 6878 6167 5510 5283 5245>, + <7641 6875 6171 5515 5287 5248>, + <7643 6871 6175 5520 5290 5252>, + <7645 6871 6176 5523 5293 5255>, + <7649 6869 6177 5526 5296 5257>, + <7656 6867 6179 5529 5298 5259>, + <7671 6879 6183 5531 5300 5260>, + <7690 6895 6188 5533 5301 5261>, + <7693 6895 6193 5534 5301 5262>, + <7679 6883 6197 5535 5302 5262>, + <7669 6879 6202 5537 5303 5263>, + <7670 6885 6209 5541 5305 5265>, + <7670 6891 6220 5544 5306 5266>, + <7670 6898 6217 5546 5307 5267>, + <7674 6904 6224 5551 5310 5269>, + <7684 6923 6224 5553 5310 5270>, + <7689 6920 6233 5556 5310 5270>, + <7718 6926 6243 5556 5310 5270>, + <7735 6923 6251 5558 5311 5270>, + <7724 6942 6247 5561 5314 5272>, + <7721 6975 6265 5570 5317 5275>, + <7736 7003 6293 5585 5324 5280>, + <7777 7007 6312 5604 5331 5286>, + <7862 7038 6346 5623 5340 5292>, + <7862 7038 6346 5623 5340 5292>, + <7862 7038 6346 5623 5340 5292>; + }; + + qcom,pc-temp-y2-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <9686 10401 10680 11050 11104 11401>, + <9784 10367 10651 11029 11106 11345>, + <9844 10346 10618 11003 11105 11260>, + <9875 10335 10585 10974 11102 11170>, + <9887 10331 10557 10941 11096 11098>, + <9890 10330 10539 10906 11089 11068>, + <9836 10343 10530 10861 11080 11075>, + <9739 10365 10523 10815 11067 11086>, + <9714 10360 10518 10793 11048 11085>, + <9726 10302 10514 10780 11017 11066>, + <9749 10260 10512 10771 10981 11044>, + <9880 10338 10522 10756 10934 11003>, + <10116 10474 10547 10736 10885 10947>, + <10170 10505 10586 10738 10874 10940>, + <9944 10486 10664 10781 10896 10992>, + <9729 10473 10720 10835 10928 11033>, + <9701 10495 10746 10897 10988 11035>, + <9694 10532 10766 10960 11059 11032>, + <9688 10541 10781 10991 11079 11043>, + <9682 10540 10795 11004 11080 11097>, + <9677 10537 10806 11018 11082 11163>, + <9674 10483 10815 11049 11128 11225>, + <9672 10313 10824 11092 11200 11283>, + <9670 10193 10827 11124 11234 11325>, + <9667 10079 10832 11151 11254 11356>, + <9664 10012 10836 11169 11271 11377>, + <9663 9998 10834 11180 11289 11395>, + <9662 9984 10826 11184 11309 11414>, + <9661 9965 10822 11175 11317 11445>, + <9660 9940 10820 11150 11329 11500>, + <9659 9913 10815 11136 11341 11537>, + <9659 9889 10729 11139 11328 11522>, + <9658 9867 10574 11151 11311 11482>, + <9657 9842 10507 11164 11315 11466>, + <9656 9813 10490 11161 11321 11473>, + <9656 9786 10478 11140 11317 11478>, + <9655 9762 10470 11112 11316 11484>, + <9655 9732 10507 11097 11321 11496>, + <9654 9708 10556 11103 11323 11495>, + <9654 9694 10525 11104 11318 11473>, + <9654 9684 10426 11103 11314 11461>, + <9654 9675 10396 11106 11316 11468>, + <9654 9668 10406 11101 11314 11471>, + <9653 9662 10267 11078 11283 11464>, + <9653 9659 10199 11060 11283 11440>, + <9653 9659 10180 11025 11296 11394>, + <9653 9658 10256 11021 11274 11345>, + <9653 9657 10321 11043 11240 11336>, + <9653 9656 10323 11048 11247 11344>, + <9652 9656 10295 10982 11294 11322>, + <9652 9654 10240 10956 11255 11261>, + <9652 9653 10172 10913 11134 11175>, + <9652 9652 10118 10825 11023 11061>, + <9650 9652 10099 10780 10831 10826>, + <9650 9652 10099 10780 10831 10826>, + <9650 9652 10099 10780 10831 10826>; + }; + + qcom,pc-temp-y3-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <13434 13398 13345 13285 13280 13272>, + <13675 13407 13338 13284 13280 13274>, + <13823 13420 13334 13283 13280 13275>, + <13901 13433 13334 13283 13280 13277>, + <13931 13444 13336 13283 13280 13278>, + <13936 13449 13340 13285 13280 13278>, + <13804 13449 13347 13288 13280 13278>, + <13564 13448 13355 13293 13281 13278>, + <13499 13451 13358 13295 13281 13278>, + <13498 13470 13359 13296 13281 13277>, + <13499 13484 13360 13296 13281 13277>, + <13523 13470 13373 13303 13284 13279>, + <13572 13441 13392 13313 13289 13282>, + <13584 13425 13393 13314 13290 13283>, + <13548 13416 13371 13310 13288 13282>, + <13516 13410 13351 13307 13286 13282>, + <13520 13407 13346 13309 13288 13282>, + <13536 13405 13343 13313 13292 13283>, + <13543 13402 13339 13313 13292 13283>, + <13545 13397 13334 13305 13287 13280>, + <13546 13391 13329 13296 13283 13277>, + <13548 13381 13324 13288 13281 13276>, + <13552 13365 13319 13283 13280 13275>, + <13557 13351 13318 13282 13279 13275>, + <13568 13340 13317 13283 13278 13275>, + <13586 13335 13317 13284 13278 13274>, + <13605 13336 13317 13283 13278 13274>, + <13625 13339 13317 13283 13277 13274>, + <13647 13343 13317 13285 13277 13274>, + <13675 13347 13317 13289 13277 13273>, + <13709 13352 13317 13292 13277 13273>, + <13746 13357 13312 13293 13278 13273>, + <13786 13364 13305 13292 13278 13274>, + <13834 13372 13302 13292 13279 13274>, + <13889 13385 13303 13290 13278 13274>, + <13952 13400 13304 13288 13278 13273>, + <14017 13416 13307 13286 13278 13273>, + <14082 13434 13314 13284 13277 13273>, + <14146 13456 13320 13283 13277 13273>, + <14209 13488 13324 13283 13277 13273>, + <14273 13532 13327 13283 13277 13273>, + <14339 13585 13333 13283 13278 13274>, + <14405 13648 13342 13283 13278 13274>, + <14482 13731 13345 13284 13278 13274>, + <14570 13843 13353 13283 13278 13274>, + <14605 13890 13360 13291 13279 13276>, + <14655 13886 13365 13292 13281 13277>, + <14684 13912 13378 13296 13283 13280>, + <14733 14009 13393 13298 13282 13280>, + <14859 14104 13394 13294 13281 13277>, + <14999 14246 13402 13296 13280 13277>, + <15153 14472 13423 13301 13283 13281>, + <15376 14712 13458 13305 13286 13284>, + <16172 14971 13514 13315 13290 13286>, + <16172 14971 13514 13315 13290 13286>, + <16172 14971 13514 13315 13290 13286>; + }; + + qcom,pc-temp-y4-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <17845 16850 16626 16493 16453 16452>, + <17707 16859 16623 16499 16453 16450>, + <17643 16875 16623 16504 16455 16449>, + <17641 16896 16626 16507 16456 16448>, + <17685 16923 16631 16509 16458 16448>, + <17761 16953 16638 16510 16459 16448>, + <17959 16995 16646 16508 16461 16449>, + <18315 17038 16657 16506 16462 16452>, + <18708 17060 16668 16506 16465 16454>, + <19236 17069 16679 16513 16469 16457>, + <19572 17084 16696 16524 16475 16461>, + <19006 17415 16799 16542 16489 16473>, + <17760 17958 16951 16564 16509 16488>, + <17274 17986 16977 16573 16513 16492>, + <17223 17320 16899 16575 16509 16491>, + <17197 16817 16810 16579 16507 16490>, + <17184 16821 16750 16620 16529 16506>, + <17165 16866 16699 16681 16570 16536>, + <17135 16877 16663 16682 16576 16541>, + <17076 16837 16634 16593 16532 16509>, + <17012 16792 16611 16517 16486 16475>, + <16969 16768 16596 16504 16468 16461>, + <16936 16750 16584 16498 16457 16451>, + <16927 16747 16578 16495 16456 16450>, + <16931 16735 16574 16491 16456 16450>, + <16939 16719 16571 16489 16457 16451>, + <16945 16707 16570 16491 16459 16453>, + <16955 16695 16570 16493 16462 16456>, + <16966 16694 16569 16494 16465 16460>, + <16978 16706 16564 16496 16471 16465>, + <16990 16724 16560 16498 16478 16472>, + <17002 16743 16564 16500 16488 16483>, + <17014 16767 16573 16502 16499 16496>, + <17027 16792 16580 16500 16501 16498>, + <17040 16818 16585 16489 16484 16481>, + <17052 16845 16589 16478 16463 16460>, + <17064 16879 16594 16475 16452 16451>, + <17077 16927 16600 16473 16446 16447>, + <17095 16964 16604 16474 16446 16448>, + <17121 16978 16617 16477 16450 16453>, + <17160 16988 16637 16480 16455 16458>, + <17211 16994 16652 16483 16456 16459>, + <17278 17008 16664 16484 16454 16456>, + <17363 17031 16681 16481 16445 16443>, + <17450 17090 16711 16491 16449 16446>, + <17435 17135 16736 16501 16471 16474>, + <17438 17159 16742 16516 16496 16504>, + <17389 17194 16787 16546 16537 16546>, + <17360 17262 16870 16574 16540 16536>, + <17381 17283 16862 16542 16494 16484>, + <17398 17284 16856 16542 16480 16473>, + <17425 17312 16891 16573 16496 16487>, + <17507 17393 16998 16635 16528 16517>, + <18186 17570 17197 16862 16705 16664>, + <18186 17570 17197 16862 16705 16664>, + <18186 17570 17197 16862 16705 16664>; + }; + + qcom,pc-temp-y5-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <8712 13450 15024 13637 17779 13876>, + <8712 13482 14393 13094 17299 16002>, + <9887 13538 13920 12763 16795 17370>, + <12171 13602 13593 12592 16319 18144>, + <13352 13655 13402 12528 15924 18488>, + <13712 13682 13338 12519 15663 18564>, + <12526 13686 13491 13011 15524 18119>, + <10345 13688 13732 13797 15423 17285>, + <9855 13494 13762 13896 15233 16665>, + <10836 12338 13637 13520 14742 16018>, + <12278 11512 13460 13263 14463 15589>, + <14305 12246 13117 13605 14692 15613>, + <16658 13838 12700 14184 15051 15805>, + <17024 14948 12908 14300 15117 15807>, + <14139 15828 14686 14149 14970 15538>, + <11513 16242 16074 14033 14913 15280>, + <11523 16069 16259 14411 15080 15197>, + <11996 15810 16323 15261 15416 15147>, + <12172 15770 16274 15815 15959 15251>, + <12062 15859 16079 16180 16933 16031>, + <11868 15956 15846 16328 17499 16947>, + <11620 15469 15368 15383 17703 17632>, + <11312 13975 14705 13688 17924 18203>, + <11115 12872 14496 13266 17959 18431>, + <11014 12058 14552 13626 17682 18509>, + <10964 11631 14629 13920 17362 18511>, + <10973 11596 14709 13944 17173 18320>, + <10988 11605 14796 13932 17044 17852>, + <10995 11588 14900 14573 17019 17407>, + <11030 11538 15113 16622 17008 17007>, + <11086 11527 15270 18010 17024 16810>, + <11136 11527 14539 18405 17391 17083>, + <11177 11500 13186 18651 18220 17910>, + <11216 11497 12702 18616 19096 18783>, + <11256 11585 12708 17851 20108 19561>, + <11296 11690 12725 16773 20954 20137>, + <11333 11737 12833 15892 21243 20622>, + <11364 11658 13487 15086 21079 21066>, + <11372 11570 14099 14616 20668 21138>, + <11354 11602 14046 14527 20112 20711>, + <11333 11673 13559 14611 19900 20367>, + <11347 11689 13647 14598 20136 20790>, + <11447 11633 14091 14488 20830 22215>, + <11628 11564 13261 14690 21851 23634>, + <11886 11464 12890 13840 19650 20132>, + <12228 11536 12810 15945 17300 17267>, + <12464 11547 13361 15880 17100 16566>, + <12844 11910 14094 16530 16574 16161>, + <12886 12441 14613 16353 15911 15963>, + <12844 12583 14513 15967 17037 16654>, + <12567 12345 14561 17027 17428 17457>, + <12151 12056 14328 17704 18241 18950>, + <11887 11870 14282 17302 18299 19121>, + <11109 11677 14642 17219 17830 18283>, + <11109 11677 14642 17219 17830 18283>, + <11109 11677 14642 17219 17830 18283>; + }; + + qcom,pc-temp-y6-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <6900 5639 5266 5065 5021 5010>, + <6907 5646 5261 5064 5021 5011>, + <6911 5654 5258 5063 5021 5012>, + <6911 5662 5258 5064 5021 5013>, + <6908 5670 5260 5065 5022 5013>, + <6903 5678 5262 5066 5023 5014>, + <6855 5686 5268 5068 5023 5015>, + <6776 5694 5276 5071 5025 5015>, + <6772 5702 5281 5074 5026 5016>, + <6911 5708 5283 5076 5027 5017>, + <7024 5719 5288 5079 5029 5018>, + <6900 5804 5324 5090 5036 5023>, + <6611 5932 5379 5103 5045 5030>, + <6465 5932 5387 5106 5047 5032>, + <6414 5744 5349 5105 5045 5031>, + <6390 5602 5310 5104 5043 5031>, + <6395 5604 5291 5117 5051 5036>, + <6409 5621 5276 5138 5065 5045>, + <6413 5625 5263 5138 5067 5047>, + <6412 5613 5251 5107 5051 5035>, + <6410 5600 5242 5078 5035 5023>, + <6413 5590 5235 5069 5028 5018>, + <6426 5582 5230 5064 5025 5015>, + <6444 5577 5229 5063 5024 5015>, + <6469 5575 5230 5063 5024 5015>, + <6500 5574 5231 5064 5024 5016>, + <6530 5579 5232 5065 5025 5016>, + <6560 5589 5235 5066 5026 5017>, + <6592 5602 5237 5068 5027 5018>, + <6630 5619 5238 5072 5029 5020>, + <6673 5639 5239 5076 5031 5022>, + <6719 5661 5240 5078 5035 5026>, + <6770 5688 5241 5079 5039 5030>, + <6823 5717 5243 5078 5040 5031>, + <6880 5750 5247 5074 5035 5026>, + <6940 5787 5251 5070 5029 5020>, + <7001 5830 5256 5068 5026 5018>, + <7062 5880 5264 5067 5024 5016>, + <7124 5938 5274 5066 5024 5017>, + <7187 6002 5285 5067 5025 5018>, + <7249 6076 5296 5069 5027 5020>, + <7312 6161 5311 5070 5028 5021>, + <7379 6261 5328 5071 5027 5020>, + <7458 6383 5344 5072 5025 5017>, + <7552 6532 5369 5074 5027 5018>, + <7589 6585 5388 5083 5033 5027>, + <7631 6596 5395 5089 5042 5037>, + <7646 6631 5423 5100 5055 5051>, + <7684 6743 5466 5110 5056 5048>, + <7789 6847 5472 5099 5042 5031>, + <7903 6977 5491 5102 5038 5029>, + <8038 7181 5547 5117 5046 5036>, + <8244 7391 5646 5141 5058 5047>, + <9160 7653 5795 5217 5112 5092>, + <9160 7653 5795 5217 5112 5092>, + <9160 7653 5795 5217 5112 5092>; + }; +}; diff --git a/qcom/qg-batterydata-atl436186020H_3780mAh.dtsi b/qcom/qg-batterydata-atl436186020H_3780mAh.dtsi new file mode 100644 index 000000000000..389a2743a930 --- /dev/null +++ b/qcom/qg-batterydata-atl436186020H_3780mAh.dtsi @@ -0,0 +1,1040 @@ +qcom,ATL436186_020H_3780mAh { + /* ATL436186_020H_3780mAh_Averaged_MasterSlave_Feb25th2020 */ + qcom,max-voltage-uv = <4400000>; + qcom,fg-cc-cv-threshold-uv = <4400000>; + qcom,fastchg-current-ma = <10000>; + qcom,batt-id-kohm = <39>; + qcom,battery-beta = <4250>; + qcom,battery-therm-kohm = <100>; + qcom,battery-type = + "ATL436186_020H_3780mAh_Averaged_MasterSlave_Feb25th2020"; + qcom,qg-batt-profile-ver = <100>; + + qcom,jeita-fcc-ranges = <0 100 1890000 + 101 200 3780000 + 201 450 10000000 + 451 550 1890000>; + + qcom,jeita-fv-ranges = <0 100 4400000 + 101 200 4400000 + 201 450 4400000 + 451 550 4050000>; + + qcom,step-chg-ranges = <3500000 4000000 10000000 + 4000001 4200000 8000000 + 4200001 4400000 6000000>; + qcom,ocv-based-step-chg; + + /* COOL = 10 degc, WARM = 45 degC */ + qcom,jeita-soft-thresholds = <0x4ccc 0x20b8>; + /* COLD = 0 degC, HOT = 55 degC*/ + qcom,jeita-hard-thresholds = <0x58cd 0x181d>; + /* COOL hys = 13 degC, WARM hys = 42 degC */ + qcom,jeita-soft-hys-thresholds = <0x48d4 0x23c0>; + qcom,jeita-soft-fcc-ua = <1890000 1890000>; + qcom,jeita-soft-fv-uv = <4400000 4050000>; + + qcom,fcc1-temp-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-data = <3697 3755 3812 3835 3845>; + }; + + qcom,fcc2-temp-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-data = <3792 3795 3802 3819 3809 3801>; + }; + + qcom,pc-temp-v1-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <43837 43914 43961 43974 43979>, + <43618 43702 43752 43762 43768>, + <43394 43485 43537 43549 43556>, + <43166 43264 43318 43332 43342>, + <42938 43039 43095 43113 43125>, + <42710 42810 42869 42890 42903>, + <42481 42578 42639 42662 42677>, + <42256 42346 42406 42431 42450>, + <42034 42119 42176 42201 42223>, + <41817 41896 41949 41975 41997>, + <41609 41677 41725 41751 41771>, + <41407 41462 41506 41531 41550>, + <41207 41252 41291 41313 41332>, + <41011 41053 41083 41103 41121>, + <40819 40863 40881 40898 40917>, + <40625 40675 40686 40700 40720>, + <40431 40487 40499 40510 40529>, + <40258 40304 40321 40329 40345>, + <40119 40139 40148 40153 40167>, + <39977 39988 39986 39986 39997>, + <39774 39809 39817 39819 39828>, + <39506 39562 39607 39622 39634>, + <39289 39314 39366 39391 39406>, + <39151 39148 39169 39185 39199>, + <39041 39021 39021 39027 39039>, + <38943 38908 38896 38893 38903>, + <38856 38802 38783 38774 38781>, + <38774 38706 38682 38669 38673>, + <38695 38620 38590 38572 38573>, + <38621 38542 38505 38481 38478>, + <38554 38471 38429 38398 38392>, + <38493 38405 38359 38322 38312>, + <38438 38346 38296 38252 38238>, + <38387 38291 38238 38189 38170>, + <38341 38243 38188 38137 38109>, + <38300 38198 38138 38084 38049>, + <38266 38162 38090 38022 37975>, + <38227 38123 38040 37953 37891>, + <38155 38058 37972 37872 37800>, + <38045 37951 37874 37776 37702>, + <37922 37829 37759 37666 37594>, + <37785 37699 37633 37539 37465>, + <37631 37552 37490 37396 37318>, + <37448 37375 37320 37231 37158>, + <37301 37226 37175 37102 37032>, + <37200 37139 37097 37033 36972>, + <37176 37110 37072 37016 36954>, + <37175 37095 37054 37001 36939>, + <37137 37069 37036 36980 36914>, + <37063 36993 36930 36851 36764>, + <36758 36680 36593 36504 36417>, + <36291 36221 36130 36040 35954>, + <35695 35625 35535 35440 35357>, + <34884 34815 34721 34626 34546>, + <33616 33554 33462 33363 33302>, + <30000 30000 30000 30000 30000>; + }; + + qcom,pc-temp-v2-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <44010 43990 43980 43955 43910 43895>, + <43674 43710 43723 43710 43669 43653>, + <43367 43445 43475 43472 43433 43418>, + <43093 43196 43238 43240 43203 43189>, + <42851 42966 43012 43017 42980 42968>, + <42613 42737 42786 42792 42757 42746>, + <42365 42504 42555 42562 42527 42517>, + <42121 42270 42323 42330 42297 42288>, + <41898 42038 42094 42100 42070 42062>, + <41692 41806 41864 41873 41844 41837>, + <41486 41578 41638 41648 41621 41615>, + <41265 41355 41418 41427 41403 41397>, + <41047 41138 41202 41209 41188 41182>, + <40862 40936 40996 41001 40980 40975>, + <40707 40746 40796 40798 40776 40772>, + <40521 40559 40598 40601 40580 40577>, + <40232 40377 40403 40410 40392 40389>, + <39909 40189 40207 40224 40211 40207>, + <39657 39968 40007 40045 40036 40032>, + <39447 39713 39804 39870 39866 39866>, + <39247 39471 39594 39674 39679 39682>, + <39047 39253 39364 39429 39442 39449>, + <38856 39052 39141 39188 39206 39213>, + <38674 38878 38961 39005 39025 39033>, + <38496 38724 38807 38848 38871 38882>, + <38358 38586 38671 38714 38738 38751>, + <38264 38460 38551 38597 38623 38636>, + <38190 38345 38443 38492 38520 38532>, + <38129 38232 38342 38395 38426 38435>, + <38078 38123 38247 38304 38337 38344>, + <38030 38040 38160 38220 38255 38261>, + <37982 37980 38078 38142 38179 38186>, + <37935 37931 38002 38068 38106 38114>, + <37884 37893 37933 38000 38035 38038>, + <37832 37863 37868 37935 37964 37959>, + <37777 37829 37812 37862 37879 37865>, + <37715 37789 37766 37778 37771 37744>, + <37646 37742 37719 37690 37659 37617>, + <37568 37678 37654 37600 37560 37514>, + <37480 37592 37571 37507 37468 37423>, + <37378 37484 37472 37409 37367 37324>, + <37250 37342 37350 37301 37256 37212>, + <37117 37183 37208 37173 37128 37083>, + <36996 37011 37048 37022 36979 36931>, + <36898 36881 36926 36922 36889 36842>, + <36814 36811 36868 36890 36863 36817>, + <36773 36779 36838 36869 36848 36802>, + <36727 36738 36803 36842 36825 36779>, + <36660 36680 36748 36790 36781 36737>, + <36517 36561 36624 36620 36609 36535>, + <36231 36271 36298 36228 36203 36133>, + <35764 35780 35781 35692 35681 35615>, + <35118 35133 35110 35007 35009 34946>, + <34216 34250 34193 34048 34114 34057>, + <32787 32833 32800 32877 32759 32761>, + <29558 29605 29729 29539 29540 29544>; + }; + + qcom,pc-temp-z1-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <10270 9660 9205 8982 8932>, + <10729 10185 9985 9894 9870>, + <10961 10522 10161 10008 9971>, + <11078 10616 10231 10065 10021>, + <11137 10656 10248 10073 10030>, + <11151 10675 10258 10073 10030>, + <11155 10683 10258 10073 10029>, + <11157 10687 10253 10071 10028>, + <11160 10685 10249 10068 10027>, + <11164 10677 10247 10067 10027>, + <11163 10670 10245 10066 10026>, + <11158 10666 10244 10066 10026>, + <11155 10663 10242 10066 10026>, + <11156 10660 10241 10066 10026>, + <11157 10657 10242 10066 10026>, + <11156 10656 10243 10066 10026>, + <11151 10657 10244 10066 10027>, + <11148 10661 10245 10067 10028>, + <11149 10661 10246 10069 10029>, + <11150 10662 10249 10070 10030>, + <11154 10662 10251 10071 10030>, + <11163 10665 10253 10073 10031>, + <11167 10668 10256 10075 10032>, + <11169 10672 10259 10077 10033>, + <11173 10677 10263 10079 10035>, + <11179 10682 10268 10081 10037>, + <11187 10688 10272 10083 10039>, + <11191 10694 10276 10084 10040>, + <11188 10695 10280 10086 10041>, + <11182 10696 10284 10089 10042>, + <11180 10697 10287 10091 10044>, + <11182 10699 10290 10093 10046>, + <11186 10703 10294 10095 10047>, + <11195 10707 10298 10098 10048>, + <11210 10711 10302 10101 10050>, + <11214 10715 10307 10104 10052>, + <11209 10725 10311 10107 10054>, + <11204 10735 10316 10109 10057>, + <11209 10736 10321 10112 10059>, + <11224 10733 10326 10114 10060>, + <11232 10731 10331 10116 10062>, + <11233 10740 10335 10119 10063>, + <11234 10751 10340 10121 10065>, + <11236 10753 10345 10123 10065>, + <11250 10761 10351 10125 10066>, + <11246 10766 10354 10126 10067>, + <11246 10761 10358 10127 10067>, + <11257 10768 10360 10127 10067>, + <11246 10764 10362 10128 10068>, + <11264 10770 10369 10131 10069>, + <11271 10785 10373 10132 10072>, + <11301 10793 10379 10137 10073>, + <11283 10797 10389 10144 10076>, + <11343 10815 10399 10147 10080>, + <11343 10815 10399 10147 10080>, + <11343 10815 10399 10147 10080>; + }; + + qcom,pc-temp-z2-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <9998 10274 10794 10844 10945>, + <10167 10355 10550 10730 10846>, + <10239 10399 10603 10678 10871>, + <10266 10395 10627 10658 10860>, + <10276 10383 10590 10661 10840>, + <10258 10382 10530 10681 10820>, + <10229 10393 10504 10694 10818>, + <10222 10402 10503 10691 10838>, + <10225 10403 10506 10686 10861>, + <10230 10402 10495 10698 10866>, + <10468 10399 10479 10712 10863>, + <10817 10392 10478 10717 10858>, + <10830 10389 10490 10720 10866>, + <10488 10389 10497 10723 10887>, + <10237 10383 10489 10733 10919>, + <10238 10380 10479 10753 10955>, + <10250 10394 10485 10763 10976>, + <10293 10409 10508 10767 10990>, + <10590 10407 10522 10769 10998>, + <10856 10392 10525 10764 10996>, + <10737 10386 10523 10757 10989>, + <10407 10410 10531 10746 10961>, + <10271 10437 10570 10711 10841>, + <10271 10447 10592 10670 10746>, + <10273 10453 10576 10628 10731>, + <10283 10454 10553 10595 10727>, + <10306 10441 10542 10604 10733>, + <10322 10425 10536 10639 10758>, + <10324 10424 10535 10657 10785>, + <10323 10434 10540 10663 10803>, + <10323 10447 10549 10671 10824>, + <10329 10467 10557 10698 10870>, + <10336 10487 10569 10749 10948>, + <10345 10497 10586 10795 11004>, + <10355 10502 10622 10833 11059>, + <10358 10503 10654 10871 11110>, + <10355 10506 10670 10914 11142>, + <10351 10511 10681 10958 11183>, + <10348 10514 10696 10979 11193>, + <10344 10522 10730 10992 11177>, + <10338 10526 10756 11000 11154>, + <10307 10496 10725 10996 11137>, + <10278 10462 10682 10987 11119>, + <10264 10453 10689 10977 11087>, + <10246 10428 10699 10978 11047>, + <10229 10374 10720 11010 11096>, + <10188 10355 10691 11025 11117>, + <10121 10306 10709 11029 11193>, + <10243 10335 10714 11081 11268>, + <10479 10337 10724 10961 10999>, + <10405 10348 10693 10847 10883>, + <10327 10360 10632 10748 10808>, + <9992 10290 10623 10696 10740>, + <10016 10209 10570 10627 10634>, + <10016 10209 10570 10627 10634>, + <10016 10209 10570 10627 10634>; + }; + + qcom,pc-temp-z3-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <19393 19347 19322 19314 19304>, + <19481 19407 19348 19323 19310>, + <19528 19444 19374 19334 19318>, + <19557 19459 19384 19340 19321>, + <19571 19467 19381 19338 19320>, + <19574 19469 19375 19332 19319>, + <19576 19464 19371 19330 19317>, + <19574 19458 19367 19329 19315>, + <19563 19453 19365 19329 19313>, + <19554 19448 19361 19327 19312>, + <19555 19445 19358 19323 19311>, + <19558 19444 19356 19321 19310>, + <19555 19442 19354 19320 19310>, + <19544 19439 19353 19319 19309>, + <19533 19433 19353 19318 19306>, + <19526 19431 19353 19318 19302>, + <19521 19432 19352 19317 19300>, + <19520 19434 19351 19315 19300>, + <19527 19434 19350 19314 19299>, + <19535 19434 19349 19312 19299>, + <19537 19434 19349 19311 19299>, + <19543 19435 19353 19313 19303>, + <19546 19436 19361 19324 19317>, + <19536 19440 19369 19333 19326>, + <19524 19451 19377 19336 19325>, + <19524 19456 19381 19338 19323>, + <19532 19456 19380 19338 19321>, + <19538 19454 19377 19335 19319>, + <19538 19451 19374 19332 19317>, + <19537 19445 19369 19330 19315>, + <19535 19440 19365 19327 19312>, + <19531 19436 19361 19324 19309>, + <19527 19434 19358 19321 19306>, + <19524 19432 19356 19318 19303>, + <19521 19430 19355 19315 19301>, + <19519 19429 19354 19313 19300>, + <19515 19426 19353 19312 19300>, + <19511 19424 19352 19312 19301>, + <19506 19420 19350 19312 19301>, + <19499 19415 19347 19313 19303>, + <19494 19410 19343 19314 19304>, + <19492 19407 19342 19315 19306>, + <19489 19404 19341 19316 19307>, + <19483 19400 19338 19319 19308>, + <19461 19390 19335 19317 19308>, + <19456 19383 19327 19309 19299>, + <19436 19385 19328 19304 19295>, + <19263 19371 19326 19300 19292>, + <19262 19374 19319 19296 19290>, + <19261 19369 19326 19308 19301>, + <19261 19365 19335 19313 19303>, + <19261 19355 19338 19313 19303>, + <19264 19362 19329 19315 19304>, + <19263 19368 19332 19316 19306>, + <19263 19368 19332 19316 19306>, + <19263 19368 19332 19316 19306>; + }; + + qcom,pc-temp-z4-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <15411 15118 14858 14791 14756>, + <15540 15131 14945 14798 14741>, + <15522 15130 14892 14768 14727>, + <15372 15081 14836 14731 14698>, + <15215 14972 14795 14714 14687>, + <15110 14894 14763 14705 14683>, + <15022 14847 14748 14697 14679>, + <14959 14816 14739 14690 14675>, + <14908 14802 14731 14684 14670>, + <14869 14794 14723 14679 14665>, + <14839 14788 14717 14674 14661>, + <14817 14781 14710 14669 14656>, + <14812 14775 14704 14663 14651>, + <14820 14769 14698 14658 14647>, + <14832 14763 14693 14652 14643>, + <14850 14762 14688 14647 14640>, + <14880 14770 14686 14643 14636>, + <14889 14779 14685 14640 14631>, + <14846 14773 14684 14639 14628>, + <14800 14754 14688 14641 14629>, + <14825 14750 14695 14648 14632>, + <14928 14825 14724 14663 14641>, + <14993 14913 14779 14695 14664>, + <15001 14914 14799 14712 14678>, + <14998 14879 14781 14707 14677>, + <14983 14850 14758 14697 14673>, + <14949 14834 14746 14689 14669>, + <14924 14823 14738 14683 14664>, + <14914 14821 14734 14678 14660>, + <14908 14820 14732 14673 14656>, + <14907 14819 14731 14670 14652>, + <14908 14821 14731 14669 14650>, + <14909 14823 14731 14668 14648>, + <14909 14826 14732 14668 14647>, + <14909 14829 14734 14669 14646>, + <14909 14831 14738 14670 14646>, + <14902 14827 14742 14676 14650>, + <14892 14820 14745 14686 14661>, + <14881 14812 14746 14689 14665>, + <14868 14804 14742 14686 14662>, + <14851 14792 14736 14681 14659>, + <14827 14773 14724 14676 14657>, + <14801 14751 14709 14671 14655>, + <14776 14733 14701 14668 14655>, + <14722 14697 14683 14659 14649>, + <14692 14666 14659 14644 14634>, + <14706 14660 14649 14639 14629>, + <14871 14659 14641 14630 14620>, + <14866 14650 14633 14626 14617>, + <14863 14655 14638 14628 14623>, + <14867 14664 14635 14630 14625>, + <14872 14672 14633 14629 14625>, + <14872 14667 14638 14627 14624>, + <14877 14663 14636 14625 14622>, + <14877 14663 14636 14625 14622>, + <14877 14663 14636 14625 14622>; + }; + + qcom,pc-temp-z5-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <12262 12657 13731 16808 17854>, + <13952 14497 15898 18081 19486>, + <15214 16021 17443 19818 21650>, + <16162 17186 18570 21296 23275>, + <17097 18170 19329 21536 24003>, + <18157 19258 19745 21509 24358>, + <19290 20662 19830 21628 24381>, + <20511 21771 20008 22343 23971>, + <21891 22042 20173 22938 23666>, + <23153 22138 20134 22808 23885>, + <24239 22299 20112 22359 24494>, + <25122 22870 20235 22259 25170>, + <25283 23518 20612 22732 26113>, + <24901 23610 21090 23419 26820>, + <24579 23449 21852 24318 26214>, + <24560 23299 22739 25492 24698>, + <24597 23117 23372 26450 24419>, + <24657 22978 23855 27282 26292>, + <24758 24230 24222 27692 27840>, + <24963 27807 24600 27046 27691>, + <27120 29427 24875 25350 27235>, + <33501 27662 23857 23361 26672>, + <36732 25045 20915 20755 24954>, + <32079 23961 19681 19621 23155>, + <25894 23427 20225 19990 22122>, + <25017 23670 21187 20786 21421>, + <26081 25610 22464 21686 21497>, + <27398 27942 24124 22802 22457>, + <28893 29059 25372 23931 23556>, + <30402 29771 26311 25076 24526>, + <31214 30415 27177 26252 25453>, + <31859 31149 28012 27490 26246>, + <32223 31779 28804 28771 27082>, + <32238 32053 29691 29417 27978>, + <32222 32216 30909 29665 29280>, + <32171 32224 31681 29773 30219>, + <31897 31917 31314 28697 28966>, + <31589 31417 30242 26131 25565>, + <31432 30966 29114 25294 24387>, + <31306 30513 27668 25736 25464>, + <31237 30105 26683 26472 27140>, + <31178 29635 26578 27651 29292>, + <31252 29276 26516 29015 31174>, + <31626 29252 25441 29682 30555>, + <31440 30295 26157 28469 30177>, + <32621 30638 26358 26578 24593>, + <28667 32814 29500 26931 25216>, + <11283 24894 31532 29489 30335>, + <11256 26655 27253 28994 33457>, + <11252 24276 28331 30163 34171>, + <11253 21078 30650 32037 33143>, + <11197 17749 31712 30278 31282>, + <11126 18743 23249 30719 30746>, + <11019 19676 23476 30978 30980>, + <11019 19676 23476 30978 30980>, + <11019 19676 23476 30978 30980>; + }; + + qcom,pc-temp-z6-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <14990 14531 14250 14172 14140>, + <15156 14653 14425 14331 14298>, + <15177 14719 14443 14341 14309>, + <15121 14708 14447 14344 14312>, + <15058 14667 14434 14340 14311>, + <15003 14634 14414 14332 14308>, + <14950 14608 14404 14326 14304>, + <14907 14588 14397 14323 14301>, + <14868 14577 14391 14319 14297>, + <14840 14569 14386 14316 14295>, + <14826 14563 14381 14312 14292>, + <14817 14558 14377 14308 14290>, + <14813 14553 14373 14305 14287>, + <14809 14548 14370 14302 14285>, + <14806 14542 14367 14299 14282>, + <14809 14540 14365 14297 14278>, + <14818 14544 14364 14294 14275>, + <14821 14549 14363 14292 14273>, + <14809 14546 14362 14291 14272>, + <14796 14539 14364 14292 14272>, + <14808 14538 14368 14294 14274>, + <14856 14573 14383 14302 14280>, + <14885 14613 14414 14324 14298>, + <14885 14616 14425 14335 14309>, + <14882 14609 14421 14334 14309>, + <14877 14602 14416 14332 14306>, + <14871 14596 14412 14329 14304>, + <14866 14592 14407 14325 14301>, + <14864 14589 14404 14321 14298>, + <14862 14587 14401 14318 14295>, + <14861 14586 14399 14316 14292>, + <14863 14587 14397 14314 14289>, + <14864 14589 14396 14312 14287>, + <14865 14591 14396 14311 14285>, + <14867 14593 14398 14310 14284>, + <14867 14594 14400 14310 14283>, + <14867 14594 14402 14312 14285>, + <14866 14593 14405 14317 14291>, + <14865 14591 14405 14318 14293>, + <14863 14588 14403 14318 14292>, + <14861 14584 14400 14317 14292>, + <14859 14579 14395 14315 14292>, + <14858 14574 14389 14314 14292>, + <14856 14569 14386 14314 14293>, + <14840 14557 14379 14311 14291>, + <14835 14546 14366 14300 14280>, + <14833 14546 14362 14295 14275>, + <14822 14541 14359 14289 14270>, + <14825 14541 14353 14285 14267>, + <14833 14546 14359 14292 14276>, + <14843 14554 14364 14297 14279>, + <14856 14555 14367 14297 14280>, + <14867 14566 14367 14299 14281>, + <14891 14579 14371 14300 14282>, + <14891 14579 14371 14300 14282>, + <14891 14579 14371 14300 14282>; + }; + + qcom,pc-temp-y1-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <5613 5139 4854 4609 4486 4453>, + <5582 5142 4858 4605 4484 4452>, + <5561 5141 4859 4600 4482 4452>, + <5548 5138 4858 4596 4480 4451>, + <5541 5134 4856 4592 4478 4450>, + <5539 5133 4853 4590 4477 4450>, + <5549 5131 4848 4587 4476 4450>, + <5563 5129 4842 4585 4475 4450>, + <5562 5129 4838 4583 4474 4449>, + <5545 5126 4835 4580 4474 4447>, + <5535 5124 4832 4578 4473 4446>, + <5536 5124 4827 4577 4472 4447>, + <5537 5122 4823 4575 4470 4447>, + <5539 5121 4821 4574 4470 4447>, + <5550 5118 4820 4572 4470 4447>, + <5558 5117 4820 4571 4470 4447>, + <5560 5127 4820 4572 4470 4447>, + <5560 5138 4822 4572 4470 4447>, + <5556 5137 4822 4573 4470 4447>, + <5550 5127 4821 4574 4471 4448>, + <5547 5124 4821 4576 4472 4448>, + <5548 5124 4824 4576 4472 4448>, + <5549 5126 4826 4577 4472 4449>, + <5552 5130 4827 4579 4473 4449>, + <5561 5136 4829 4581 4473 4450>, + <5570 5140 4831 4583 4474 4451>, + <5579 5139 4834 4585 4476 4451>, + <5585 5137 4837 4588 4477 4452>, + <5579 5139 4841 4591 4478 4452>, + <5566 5146 4848 4594 4479 4453>, + <5563 5150 4851 4597 4480 4453>, + <5559 5154 4853 4600 4482 4454>, + <5551 5159 4854 4604 4484 4455>, + <5550 5161 4854 4607 4486 4456>, + <5556 5162 4855 4611 4488 4458>, + <5561 5162 4856 4615 4489 4458>, + <5559 5157 4859 4619 4490 4459>, + <5555 5152 4862 4623 4491 4460>, + <5560 5155 4871 4624 4492 4461>, + <5575 5164 4883 4625 4493 4462>, + <5582 5167 4888 4627 4495 4463>, + <5567 5164 4886 4631 4496 4463>, + <5558 5165 4888 4634 4497 4464>, + <5581 5178 4892 4640 4499 4465>, + <5588 5163 4895 4644 4500 4466>, + <5579 5172 4907 4646 4501 4466>, + <5597 5165 4900 4650 4502 4466>, + <5597 5165 4903 4654 4502 4468>, + <5638 5175 4904 4656 4503 4467>, + <5637 5176 4909 4658 4503 4468>, + <5722 5182 4909 4660 4503 4468>, + <5802 5199 4918 4665 4506 4469>, + <5999 5220 4916 4671 4508 4470>, + <6440 5346 4923 4681 4510 4473>, + <6440 5346 4923 4681 4510 4473>, + <6440 5346 4923 4681 4510 4473>; + }; + + qcom,pc-temp-y2-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <10579 10898 11101 11195 11534 11808>, + <10587 10890 11091 11188 11513 11753>, + <10595 10879 11070 11175 11481 11696>, + <10604 10868 11044 11157 11444 11639>, + <10612 10857 11017 11136 11403 11584>, + <10621 10848 10996 11113 11363 11533>, + <10630 10840 10976 11081 11311 11480>, + <10639 10830 10955 11051 11264 11433>, + <10650 10820 10936 11044 11251 11410>, + <10673 10808 10914 11046 11247 11392>, + <10698 10802 10904 11044 11242 11376>, + <10744 10811 10908 11020 11234 11359>, + <10793 10832 10916 10994 11227 11343>, + <10791 10866 10931 11000 11228 11330>, + <10754 10934 10967 11040 11240 11314>, + <10733 10997 11008 11088 11247 11303>, + <10770 11068 11064 11140 11246 11302>, + <10824 11133 11128 11204 11248 11309>, + <10829 11137 11183 11298 11292 11337>, + <10812 11095 11236 11421 11410 11407>, + <10788 11055 11257 11462 11470 11467>, + <10757 11032 11230 11408 11472 11558>, + <10716 11010 11191 11350 11476 11666>, + <10655 10989 11177 11340 11522 11710>, + <10520 10968 11170 11336 11595 11730>, + <10362 10946 11169 11335 11630 11752>, + <10105 10916 11177 11364 11639 11784>, + <9860 10890 11186 11400 11646 11820>, + <9786 10887 11191 11417 11670 11856>, + <9751 10889 11190 11437 11713 11899>, + <9729 10890 11180 11443 11749 11939>, + <9712 10843 11139 11445 11777 11976>, + <9699 10771 11103 11445 11803 12006>, + <9691 10761 11101 11445 11829 12028>, + <9685 10796 11105 11451 11852 12052>, + <9680 10818 11107 11445 11855 12059>, + <9676 10793 11098 11416 11825 12028>, + <9673 10743 11080 11393 11794 11998>, + <9671 10658 11045 11390 11782 12004>, + <9669 10468 10976 11389 11776 12021>, + <9667 10230 10887 11379 11772 12015>, + <9666 9913 10756 11355 11767 11932>, + <9664 9749 10615 11333 11749 11876>, + <9663 9708 10495 11285 11708 11873>, + <9662 9691 10413 11193 11663 11846>, + <9660 9683 10344 11207 11610 11670>, + <9659 9678 10297 11200 11562 11627>, + <9658 9673 10226 11178 11454 11533>, + <9657 9669 10160 11156 11417 11523>, + <9654 9666 10110 11116 11448 11504>, + <9651 9663 10039 11055 11432 11472>, + <9650 9659 9904 10988 11333 11399>, + <9648 9654 9774 10991 11236 11296>, + <9648 9651 9700 11020 11107 11175>, + <9648 9651 9700 11020 11107 11175>, + <9648 9651 9700 11020 11107 11175>; + }; + + qcom,pc-temp-y3-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <13401 13334 13305 13279 13270 13266>, + <13404 13336 13305 13280 13270 13266>, + <13407 13339 13306 13281 13271 13267>, + <13409 13341 13307 13281 13271 13268>, + <13412 13343 13308 13282 13272 13269>, + <13414 13345 13309 13282 13272 13270>, + <13415 13347 13310 13283 13273 13270>, + <13416 13349 13312 13283 13273 13270>, + <13421 13351 13312 13284 13274 13270>, + <13434 13352 13313 13284 13274 13271>, + <13442 13353 13314 13285 13275 13271>, + <13422 13356 13315 13285 13275 13272>, + <13394 13359 13316 13285 13275 13272>, + <13389 13356 13316 13286 13275 13273>, + <13391 13345 13316 13288 13276 13273>, + <13393 13339 13316 13289 13276 13273>, + <13388 13342 13313 13290 13277 13274>, + <13379 13346 13310 13291 13279 13275>, + <13373 13345 13309 13291 13279 13275>, + <13369 13337 13308 13290 13280 13276>, + <13364 13329 13308 13289 13280 13277>, + <13360 13325 13305 13286 13277 13274>, + <13356 13322 13300 13282 13274 13270>, + <13351 13319 13298 13280 13272 13269>, + <13343 13318 13297 13279 13270 13268>, + <13338 13316 13296 13278 13270 13268>, + <13339 13315 13296 13278 13270 13268>, + <13342 13314 13295 13278 13270 13268>, + <13347 13312 13295 13278 13270 13268>, + <13356 13310 13295 13278 13271 13268>, + <13365 13309 13294 13278 13271 13268>, + <13373 13306 13293 13278 13271 13268>, + <13381 13304 13293 13278 13270 13269>, + <13391 13305 13293 13278 13270 13269>, + <13406 13311 13292 13278 13271 13269>, + <13425 13316 13293 13278 13271 13268>, + <13451 13318 13293 13277 13270 13268>, + <13484 13321 13294 13277 13269 13267>, + <13520 13323 13295 13276 13269 13267>, + <13561 13327 13295 13274 13269 13267>, + <13608 13332 13296 13275 13269 13268>, + <13660 13343 13298 13276 13269 13268>, + <13722 13357 13299 13277 13270 13268>, + <13798 13368 13301 13277 13270 13268>, + <13898 13385 13305 13278 13269 13267>, + <13981 13408 13307 13278 13270 13270>, + <14066 13433 13309 13279 13272 13271>, + <14173 13468 13312 13281 13273 13271>, + <14311 13522 13319 13285 13275 13271>, + <14673 13589 13329 13285 13273 13270>, + <15387 13676 13335 13285 13273 13270>, + <16730 13847 13348 13287 13274 13271>, + <19422 14291 13383 13291 13275 13271>, + <24674 15433 13481 13297 13276 13273>, + <24674 15433 13481 13297 13276 13273>, + <24674 15433 13481 13297 13276 13273>; + }; + + qcom,pc-temp-y4-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <16694 16620 16544 16472 16435 16430>, + <16722 16640 16554 16470 16434 16428>, + <16772 16662 16560 16467 16433 16426>, + <16827 16684 16563 16465 16431 16424>, + <16872 16700 16565 16463 16430 16422>, + <16890 16706 16565 16462 16429 16422>, + <16887 16703 16562 16462 16429 16422>, + <16884 16698 16557 16461 16429 16422>, + <16883 16695 16555 16462 16430 16423>, + <16885 16692 16555 16463 16431 16424>, + <16889 16691 16555 16465 16432 16424>, + <16942 16691 16558 16469 16434 16426>, + <17027 16693 16566 16474 16438 16427>, + <17070 16714 16578 16479 16441 16429>, + <17099 16795 16599 16484 16446 16433>, + <17108 16843 16624 16491 16451 16436>, + <17016 16843 16657 16503 16456 16441>, + <16874 16835 16685 16519 16463 16446>, + <16813 16813 16685 16543 16477 16457>, + <16782 16754 16670 16575 16501 16474>, + <16750 16699 16650 16585 16510 16481>, + <16705 16656 16605 16546 16490 16467>, + <16657 16619 16553 16498 16463 16447>, + <16613 16593 16528 16477 16449 16437>, + <16568 16574 16513 16462 16439 16430>, + <16550 16558 16506 16458 16436 16428>, + <16559 16545 16503 16459 16436 16429>, + <16570 16532 16502 16460 16438 16430>, + <16576 16512 16501 16463 16440 16431>, + <16581 16488 16500 16468 16444 16435>, + <16587 16478 16500 16474 16449 16439>, + <16596 16484 16498 16479 16456 16444>, + <16606 16495 16495 16485 16463 16450>, + <16615 16506 16490 16490 16469 16454>, + <16625 16517 16481 16494 16473 16457>, + <16632 16529 16479 16494 16473 16457>, + <16639 16549 16486 16481 16460 16447>, + <16644 16569 16497 16466 16445 16436>, + <16647 16580 16503 16453 16440 16434>, + <16650 16587 16507 16443 16437 16433>, + <16650 16588 16511 16442 16435 16433>, + <16636 16578 16517 16445 16432 16432>, + <16620 16568 16522 16450 16430 16431>, + <16614 16563 16525 16453 16428 16427>, + <16615 16562 16523 16451 16422 16420>, + <16613 16564 16518 16456 16427 16422>, + <16627 16574 16527 16464 16431 16427>, + <16649 16594 16545 16476 16440 16441>, + <16680 16626 16576 16495 16462 16472>, + <16773 16666 16611 16492 16462 16446>, + <16928 16677 16605 16482 16430 16426>, + <17295 16696 16613 16495 16436 16431>, + <18563 16866 16657 16525 16454 16445>, + <24332 17928 16752 16586 16506 16498>, + <24332 17928 16752 16586 16506 16498>, + <24332 17928 16752 16586 16506 16498>; + }; + + qcom,pc-temp-y5-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <17385 18969 19820 18348 20163 15959>, + <17747 18838 19450 18890 20657 19132>, + <18103 18812 19205 19190 21127 22137>, + <18411 18852 19060 19305 21522 24662>, + <18626 18918 18991 19291 21795 26391>, + <18705 18971 18974 19205 21896 27007>, + <18629 19094 19073 18964 21813 26331>, + <18510 19255 19222 18609 21627 25304>, + <18766 19163 19149 18291 21388 24842>, + <20163 18555 18614 17964 21017 24218>, + <21032 18009 18042 17605 20541 23551>, + <19032 17765 17592 16853 19821 22949>, + <16117 17560 17120 16095 18943 22277>, + <16345 17065 16488 16048 18051 21384>, + <19627 15838 15525 16241 17057 20196>, + <21566 15288 15054 16327 16646 19365>, + <21325 17934 15379 15963 16689 18762>, + <20982 21635 16106 15532 16771 18242>, + <21191 22355 17495 15688 16847 18058>, + <22316 22435 20149 16465 16869 17992>, + <23224 22550 21963 17525 17119 18301>, + <23686 22921 22848 19857 19274 19217>, + <23988 23459 23408 22065 21698 20457>, + <23290 23862 23498 22361 21910 21812>, + <19618 24215 23492 22200 21660 23372>, + <16438 24526 23534 22071 21408 23966>, + <14775 24905 23990 22050 21155 23476>, + <13666 25190 24552 22075 21047 22545>, + <13635 24764 24798 22051 21119 21378>, + <13849 22890 24942 21876 21068 19896>, + <13996 20838 25126 21761 20694 19265>, + <14033 18639 25610 21706 19522 19158>, + <14060 16889 26149 21672 18549 19111>, + <14124 17260 26121 21984 18968 19337>, + <14308 19696 25472 22832 20290 20169>, + <14508 21521 24816 23852 21110 20787>, + <14746 22141 24379 25326 21478 20975>, + <14986 22550 23907 26231 21632 21128>, + <15179 22752 23025 24735 21694 21438>, + <15372 22757 21838 22015 22081 22256>, + <15402 22360 21056 21454 22681 23441>, + <14907 20259 20513 22055 23749 25248>, + <14397 17852 19989 21633 24797 27697>, + <14093 15614 19667 21203 26044 30188>, + <13935 14761 20276 22289 27496 29447>, + <13951 14682 20221 21232 22757 27736>, + <13926 14690 18886 19253 22810 27775>, + <14234 14424 17632 18735 22875 24541>, + <14603 14818 17328 19657 22999 21351>, + <13616 15527 17751 21342 20705 20460>, + <12552 15663 18495 22607 27375 29585>, + <11145 14831 17455 22804 28646 29386>, + <9957 13010 16230 23779 29324 28727>, + <9195 10486 14924 24477 27339 28153>, + <9195 10486 14924 24477 27339 28153>, + <9195 10486 14924 24477 27339 28153>; + }; + + qcom,pc-temp-y6-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <5494 5203 5060 4960 4929 4921>, + <5509 5209 5061 4960 4929 4921>, + <5520 5213 5060 4959 4928 4921>, + <5526 5215 5059 4959 4928 4921>, + <5530 5216 5058 4958 4928 4921>, + <5531 5216 5057 4958 4928 4921>, + <5527 5214 5055 4958 4928 4921>, + <5521 5210 5053 4958 4929 4922>, + <5521 5207 5051 4958 4929 4922>, + <5525 5205 5050 4959 4930 4923>, + <5530 5204 5049 4959 4931 4923>, + <5532 5203 5050 4960 4931 4924>, + <5535 5204 5052 4962 4932 4925>, + <5541 5208 5055 4963 4934 4926>, + <5556 5221 5060 4966 4935 4927>, + <5563 5231 5066 4969 4937 4928>, + <5536 5233 5073 4973 4939 4930>, + <5494 5234 5079 4978 4942 4932>, + <5478 5229 5079 4985 4947 4935>, + <5470 5207 5074 4993 4954 4941>, + <5463 5187 5068 4996 4956 4943>, + <5453 5173 5053 4982 4948 4937>, + <5444 5162 5036 4966 4938 4928>, + <5437 5156 5028 4959 4933 4925>, + <5431 5152 5023 4954 4929 4922>, + <5429 5150 5021 4953 4928 4922>, + <5436 5149 5021 4953 4928 4922>, + <5449 5148 5022 4954 4928 4922>, + <5463 5146 5023 4955 4929 4923>, + <5480 5145 5024 4957 4931 4923>, + <5500 5145 5025 4959 4933 4925>, + <5522 5150 5026 4961 4934 4927>, + <5546 5159 5026 4963 4936 4929>, + <5573 5171 5027 4965 4938 4930>, + <5604 5188 5027 4967 4940 4931>, + <5637 5207 5028 4967 4940 4931>, + <5673 5229 5032 4964 4936 4927>, + <5711 5253 5039 4959 4931 4924>, + <5753 5277 5046 4956 4930 4923>, + <5798 5302 5053 4953 4929 4924>, + <5845 5328 5061 4953 4929 4924>, + <5892 5353 5072 4955 4928 4924>, + <5947 5381 5086 4959 4928 4924>, + <6021 5417 5102 4961 4927 4922>, + <6115 5463 5120 4962 4926 4920>, + <6200 5508 5125 4964 4928 4922>, + <6283 5549 5138 4968 4931 4925>, + <6392 5602 5160 4974 4934 4929>, + <6541 5672 5190 4983 4941 4939>, + <6922 5760 5227 4983 4941 4930>, + <7615 5860 5251 4980 4931 4924>, + <8825 6039 5300 4988 4934 4926>, + <11227 6535 5388 5002 4940 4931>, + <16611 7839 5546 5027 4956 4948>, + <16611 7839 5546 5027 4956 4948>, + <16611 7839 5546 5027 4956 4948>; + }; +}; diff --git a/qcom/qg-batterydata-atl466271_3300mAh.dtsi b/qcom/qg-batterydata-atl466271_3300mAh.dtsi new file mode 100644 index 000000000000..456c17bc725c --- /dev/null +++ b/qcom/qg-batterydata-atl466271_3300mAh.dtsi @@ -0,0 +1,1041 @@ +qcom,ATL466271_3300mAh { + /* ATL466271_3300mAh_averaged_MasterSlave_Jun12th2019 */ + qcom,max-voltage-uv = <4400000>; + qcom,fg-cc-cv-threshold-uv = <4390000>; + qcom,fastchg-current-ma = <8000>; + qcom,batt-id-kohm = <24>; + qcom,battery-beta = <4250>; + qcom,battery-therm-kohm = <100>; + qcom,battery-type = + "ATL466271_3300mAh_averaged_MasterSlave_Jun12th2019"; + qcom,qg-batt-profile-ver = <100>; + + qcom,jeita-fcc-ranges = <0 100 1600000 + 101 200 3200000 + 201 450 8000000 + 451 550 1600000>; + + qcom,jeita-fv-ranges = <0 100 4400000 + 101 200 4400000 + 201 450 4400000 + 451 550 4050000>; + + qcom,step-chg-ranges = <3500000 4000000 8000000 + 4000001 4200000 6000000 + 4200001 4400000 4000000>; + qcom,ocv-based-step-chg; + + /* COOL = 10 degc, WARM = 45 degC */ + qcom,jeita-soft-thresholds = <0x4ccc 0x20b8>; + /* COLD = 0 degC, HOT = 55 degC*/ + qcom,jeita-hard-thresholds = <0x58cd 0x181d>; + /* COOL hys = 13 degC, WARM hys = 42 degC */ + qcom,jeita-soft-hys-thresholds = <0x48d4 0x23c0>; + qcom,jeita-soft-fcc-ua = <1600000 1600000>; + qcom,jeita-soft-fv-uv = <4400000 4050000>; + + qcom,fcc1-temp-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-data = <3191 3260 3320 3354 3366>; + }; + + qcom,fcc2-temp-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-data = <3307 3309 3324 3332 3330 3326>; + }; + + qcom,pc-temp-v1-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <43710 43825 43909 43937 43942>, + <43473 43605 43706 43721 43723>, + <43237 43380 43489 43509 43510>, + <43003 43150 43267 43294 43299>, + <42775 42918 43038 43070 43079>, + <42550 42687 42804 42837 42850>, + <42328 42457 42573 42606 42620>, + <42109 42230 42341 42375 42390>, + <41894 42008 42113 42145 42161>, + <41684 41789 41886 41917 41933>, + <41476 41574 41663 41690 41705>, + <41278 41360 41446 41467 41481>, + <41103 41159 41232 41247 41261>, + <40943 40987 41027 41035 41047>, + <40756 40823 40831 40833 40840>, + <40499 40625 40638 40639 40642>, + <40235 40371 40434 40442 40448>, + <40047 40136 40224 40241 40259>, + <39905 39978 40039 40053 40076>, + <39770 39845 39893 39894 39909>, + <39637 39668 39742 39742 39748>, + <39498 39402 39527 39546 39554>, + <39319 39159 39260 39286 39299>, + <39057 39018 39056 39062 39070>, + <38841 38914 38916 38909 38913>, + <38748 38814 38798 38783 38786>, + <38688 38714 38686 38668 38667>, + <38628 38621 38584 38566 38559>, + <38566 38536 38491 38471 38460>, + <38504 38459 38406 38380 38367>, + <38445 38391 38330 38297 38282>, + <38388 38330 38261 38223 38205>, + <38337 38276 38199 38156 38134>, + <38292 38228 38143 38095 38068>, + <38251 38187 38095 38043 38009>, + <38214 38146 38049 37992 37951>, + <38182 38111 38004 37933 37881>, + <38143 38071 37958 37869 37800>, + <38074 38006 37895 37793 37711>, + <37974 37903 37802 37697 37614>, + <37864 37788 37692 37587 37506>, + <37736 37663 37571 37457 37376>, + <37592 37522 37433 37310 37228>, + <37427 37351 37270 37152 37071>, + <37293 37218 37135 37037 36964>, + <37218 37148 37061 36976 36918>, + <37197 37127 37043 36958 36899>, + <37176 37114 37027 36945 36884>, + <37152 37086 37005 36915 36845>, + <37053 36954 36879 36723 36623>, + <36674 36578 36526 36347 36242>, + <36195 36086 36041 35859 35751>, + <35574 35449 35427 35229 35116>, + <34729 34574 34574 34362 34242>, + <33401 33172 33225 32989 32851>, + <30000 30000 30000 30000 30000>; + }; + + qcom,pc-temp-v2-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <43975 43950 43930 43905 43855 43835>, + <43614 43647 43667 43663 43617 43596>, + <43279 43361 43410 43424 43383 43362>, + <42972 43092 43162 43188 43150 43130>, + <42688 42841 42921 42956 42921 42903>, + <42432 42596 42682 42724 42691 42675>, + <42220 42350 42446 42490 42458 42443>, + <42020 42110 42212 42257 42225 42210>, + <41772 41881 41982 42027 41995 41980>, + <41458 41662 41755 41799 41766 41751>, + <41235 41448 41531 41574 41541 41526>, + <41153 41235 41310 41352 41318 41305>, + <41088 41026 41094 41134 41100 41087>, + <40904 40832 40899 40930 40893 40877>, + <40447 40653 40720 40736 40694 40672>, + <40034 40458 40525 40537 40495 40472>, + <39788 40221 40292 40319 40288 40277>, + <39585 39967 40050 40106 40087 40088>, + <39406 39734 39841 39926 39912 39913>, + <39248 39515 39652 39767 39754 39750>, + <39074 39305 39456 39583 39572 39566>, + <38832 39100 39232 39336 39328 39323>, + <38584 38908 39017 39089 39082 39080>, + <38426 38747 38845 38906 38903 38901>, + <38310 38609 38699 38752 38755 38754>, + <38226 38477 38570 38621 38627 38625>, + <38164 38335 38453 38506 38513 38511>, + <38113 38204 38348 38403 38410 38407>, + <38062 38112 38253 38308 38314 38311>, + <38014 38043 38166 38221 38224 38220>, + <37968 37988 38082 38140 38142 38137>, + <37925 37942 37996 38064 38067 38062>, + <37882 37901 37921 37993 37995 37989>, + <37836 37861 37870 37925 37926 37914>, + <37789 37823 37831 37859 37858 37837>, + <37739 37781 37790 37789 37775 37745>, + <37688 37735 37747 37715 37668 37625>, + <37631 37682 37698 37637 37559 37505>, + <37562 37619 37632 37559 37469 37410>, + <37480 37542 37547 37477 37386 37325>, + <37385 37449 37447 37382 37290 37228>, + <37268 37321 37322 37269 37178 37113>, + <37144 37177 37181 37135 37045 36979>, + <37027 37026 37025 36987 36895 36830>, + <36932 36918 36939 36908 36841 36784>, + <36855 36857 36899 36885 36818 36762>, + <36812 36827 36875 36867 36801 36749>, + <36761 36786 36846 36843 36779 36722>, + <36679 36721 36775 36779 36692 36597>, + <36475 36551 36546 36552 36390 36264>, + <36066 36173 36127 36133 35937 35797>, + <35499 35647 35579 35596 35370 35211>, + <34766 34968 34863 34909 34633 34453>, + <33784 34024 33935 33996 33658 33408>, + <32412 32711 32567 32650 31840 31311>, + <28215 28831 27522 28579 27814 27518>; + }; + + qcom,pc-temp-z1-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <11770 11167 10508 10200 10123>, + <11802 11193 10579 10273 10190>, + <11806 11200 10581 10275 10191>, + <11805 11183 10570 10275 10191>, + <11792 11170 10557 10270 10189>, + <11777 11154 10545 10264 10185>, + <11765 11131 10537 10259 10182>, + <11755 11116 10530 10255 10180>, + <11743 11111 10524 10251 10178>, + <11735 11108 10520 10250 10177>, + <11730 11108 10517 10249 10175>, + <11726 11108 10514 10248 10174>, + <11721 11108 10512 10248 10173>, + <11717 11105 10511 10247 10173>, + <11714 11099 10510 10247 10172>, + <11704 11097 10508 10245 10172>, + <11693 11095 10507 10245 10172>, + <11693 11095 10506 10245 10172>, + <11704 11097 10506 10246 10174>, + <11714 11101 10509 10248 10175>, + <11726 11106 10513 10252 10177>, + <11741 11114 10517 10254 10179>, + <11744 11122 10522 10256 10181>, + <11737 11128 10527 10258 10183>, + <11732 11133 10532 10260 10185>, + <11733 11134 10537 10264 10187>, + <11737 11132 10542 10267 10190>, + <11740 11131 10548 10272 10194>, + <11743 11133 10553 10276 10197>, + <11747 11137 10558 10280 10200>, + <11750 11142 10564 10285 10203>, + <11754 11154 10571 10288 10206>, + <11758 11165 10579 10292 10209>, + <11769 11165 10584 10296 10213>, + <11781 11161 10589 10301 10217>, + <11789 11159 10594 10306 10221>, + <11796 11169 10600 10312 10225>, + <11803 11182 10606 10317 10229>, + <11809 11185 10612 10322 10233>, + <11816 11186 10619 10326 10236>, + <11819 11188 10625 10330 10239>, + <11821 11199 10630 10335 10243>, + <11823 11208 10636 10340 10246>, + <11826 11206 10642 10342 10248>, + <11820 11215 10648 10344 10249>, + <11820 11220 10655 10347 10250>, + <11830 11225 10660 10348 10252>, + <11816 11232 10658 10350 10253>, + <11831 11224 10662 10354 10257>, + <11856 11221 10671 10358 10261>, + <11833 11233 10673 10362 10265>, + <11848 11251 10678 10368 10270>, + <11885 11257 10688 10374 10275>, + <11898 11288 10702 10382 10282>, + <11898 11288 10702 10382 10282>, + <11898 11288 10702 10382 10282>; + }; + + qcom,pc-temp-z2-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <9894 9757 10034 10106 10345>, + <9913 9932 10014 10164 10226>, + <9939 10003 10052 10124 10214>, + <9961 9993 10069 10079 10205>, + <9956 9975 10063 10081 10205>, + <9932 9968 10050 10100 10208>, + <9909 9964 10028 10116 10214>, + <9894 9962 9988 10127 10224>, + <9882 9965 9971 10137 10239>, + <9879 9971 9979 10146 10256>, + <9887 9975 9990 10155 10278>, + <9899 9978 9996 10160 10293>, + <9908 9983 10003 10160 10302>, + <9915 10111 10010 10159 10307>, + <9923 10305 10017 10164 10303>, + <9937 10319 10021 10171 10296>, + <9949 10152 10020 10170 10294>, + <9950 10028 10015 10163 10294>, + <9944 10019 10013 10158 10295>, + <9940 10013 10022 10178 10307>, + <9940 10015 10039 10212 10331>, + <9943 10049 10081 10217 10334>, + <9948 10079 10155 10205 10297>, + <9962 10074 10180 10185 10246>, + <9973 10059 10141 10123 10180>, + <9974 10052 10094 10050 10113>, + <9972 10052 10070 10041 10102>, + <9972 10053 10053 10046 10113>, + <9973 10046 10049 10054 10127>, + <9975 10033 10060 10064 10141>, + <9976 10029 10075 10077 10158>, + <9978 10038 10091 10098 10180>, + <9980 10052 10108 10129 10208>, + <9983 10064 10127 10163 10243>, + <9988 10077 10148 10206 10293>, + <9992 10087 10168 10244 10345>, + <9997 10095 10183 10263 10380>, + <10003 10102 10195 10276 10409>, + <10012 10114 10208 10287 10417>, + <10023 10130 10226 10298 10403>, + <10024 10137 10237 10306 10390>, + <10014 10120 10220 10308 10389>, + <10008 10106 10192 10307 10384>, + <10006 10106 10186 10298 10361>, + <10058 10124 10199 10299 10329>, + <10061 10124 10204 10309 10360>, + <10054 10113 10214 10301 10359>, + <10052 10093 10207 10352 10392>, + <10039 10104 10227 10397 10452>, + <9972 10155 10228 10268 10254>, + <10081 10129 10171 10193 10218>, + <10034 10095 10128 10161 10175>, + <9993 10043 10103 10128 10146>, + <9836 9993 10057 10083 10063>, + <9836 9993 10057 10083 10063>, + <9836 9993 10057 10083 10063>; + }; + + qcom,pc-temp-z3-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <19500 19444 19370 19351 19313>, + <19626 19520 19402 19353 19340>, + <19677 19560 19426 19362 19348>, + <19706 19570 19435 19369 19353>, + <19708 19575 19432 19369 19353>, + <19704 19574 19427 19367 19351>, + <19701 19566 19421 19364 19348>, + <19699 19557 19414 19360 19345>, + <19697 19549 19409 19355 19341>, + <19692 19541 19406 19353 19340>, + <19680 19535 19404 19352 19339>, + <19665 19529 19401 19351 19338>, + <19649 19525 19397 19351 19337>, + <19632 19526 19395 19351 19336>, + <19625 19529 19394 19350 19335>, + <19632 19529 19394 19349 19331>, + <19639 19523 19394 19348 19329>, + <19638 19517 19394 19347 19327>, + <19628 19510 19394 19345 19325>, + <19621 19502 19390 19341 19323>, + <19618 19501 19385 19335 19320>, + <19616 19515 19389 19337 19322>, + <19618 19527 19402 19355 19339>, + <19632 19520 19415 19369 19354>, + <19643 19503 19428 19376 19357>, + <19638 19499 19437 19380 19359>, + <19626 19519 19437 19380 19359>, + <19619 19539 19434 19373 19356>, + <19618 19539 19430 19368 19353>, + <19618 19535 19425 19366 19350>, + <19619 19530 19418 19364 19347>, + <19621 19524 19413 19362 19343>, + <19622 19517 19409 19358 19340>, + <19621 19512 19405 19354 19336>, + <19618 19508 19401 19349 19331>, + <19615 19505 19398 19346 19328>, + <19611 19503 19397 19346 19330>, + <19607 19500 19396 19347 19336>, + <19603 19497 19395 19348 19339>, + <19597 19494 19393 19350 19339>, + <19593 19490 19390 19351 19339>, + <19592 19487 19386 19352 19339>, + <19588 19483 19383 19353 19339>, + <19579 19481 19385 19354 19341>, + <19543 19466 19382 19350 19341>, + <19529 19450 19368 19337 19321>, + <19525 19448 19365 19331 19318>, + <19523 19438 19363 19324 19312>, + <19489 19434 19359 19320 19312>, + <19401 19438 19363 19342 19330>, + <19514 19442 19376 19345 19331>, + <19508 19444 19378 19345 19332>, + <19506 19447 19381 19346 19334>, + <19479 19451 19379 19353 19342>, + <19479 19451 19379 19353 19342>, + <19479 19451 19379 19353 19342>; + }; + + qcom,pc-temp-z4-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <15847 15406 14998 14784 14808>, + <15949 15355 15044 14878 14825>, + <15794 15280 14959 14838 14798>, + <15524 15160 14880 14782 14745>, + <15335 15024 14821 14755 14725>, + <15199 14932 14776 14735 14717>, + <15092 14862 14760 14724 14712>, + <15007 14818 14752 14719 14708>, + <14938 14795 14745 14715 14704>, + <14892 14781 14736 14710 14700>, + <14861 14774 14728 14704 14696>, + <14839 14771 14722 14699 14691>, + <14823 14768 14716 14693 14687>, + <14809 14746 14714 14688 14682>, + <14805 14717 14714 14683 14677>, + <14837 14717 14714 14679 14672>, + <14877 14763 14713 14676 14669>, + <14877 14798 14707 14672 14666>, + <14845 14782 14700 14669 14663>, + <14819 14748 14691 14667 14660>, + <14809 14748 14684 14665 14657>, + <14802 14849 14717 14676 14662>, + <14817 14940 14810 14736 14713>, + <14926 14941 14844 14773 14752>, + <15018 14932 14810 14755 14738>, + <15011 14916 14769 14725 14711>, + <14979 14870 14751 14712 14699>, + <14949 14826 14739 14706 14693>, + <14922 14811 14733 14701 14688>, + <14898 14803 14730 14696 14684>, + <14881 14800 14728 14693 14681>, + <14867 14800 14728 14691 14678>, + <14859 14800 14727 14689 14675>, + <14855 14800 14728 14689 14674>, + <14853 14801 14730 14689 14673>, + <14850 14801 14732 14690 14672>, + <14845 14800 14733 14694 14676>, + <14843 14799 14734 14701 14687>, + <14846 14800 14735 14703 14692>, + <14851 14805 14736 14701 14691>, + <14852 14807 14737 14699 14691>, + <14843 14799 14733 14696 14691>, + <14831 14786 14724 14692 14690>, + <14819 14776 14719 14690 14690>, + <14767 14740 14703 14678 14676>, + <14740 14710 14680 14653 14645>, + <14731 14703 14668 14647 14637>, + <14725 14696 14656 14637 14627>, + <14741 14692 14651 14632 14622>, + <14832 14699 14662 14641 14641>, + <14739 14707 14661 14645 14646>, + <14748 14705 14661 14648 14648>, + <14752 14704 14661 14650 14649>, + <14789 14699 14665 14647 14645>, + <14789 14699 14665 14647 14645>, + <14789 14699 14665 14647 14645>; + }; + + qcom,pc-temp-z5-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <11792 12279 13535 15414 14204>, + <13001 13808 15235 16383 17416>, + <13841 15100 16456 17237 19077>, + <14514 16104 17533 18315 20517>, + <15113 17028 18754 19244 21245>, + <15689 18181 19650 20146 21743>, + <16375 19593 19683 20412 21915>, + <17353 20752 19475 20064 21544>, + <18570 21607 19385 19726 21069>, + <19714 22312 19837 19833 21119>, + <20922 22624 20368 20227 21592>, + <21654 22649 20366 20704 22135>, + <21494 22792 20190 21409 22819>, + <21073 24392 20127 22129 23478>, + <21017 26764 20584 22757 23767>, + <22555 26941 21094 23386 23725>, + <24349 24455 21214 23801 23655>, + <24216 22548 21439 24313 23878>, + <22900 22853 21828 24599 24211>, + <22166 23930 23250 24474 24553>, + <23067 25813 24579 24129 24960>, + <25218 31144 24161 23371 24839>, + <27733 35337 22682 21648 23111>, + <31628 31478 21716 20674 21705>, + <34089 22242 21182 20941 21493>, + <31865 19114 20879 21395 21408>, + <26536 20884 21549 21643 21618>, + <23985 23280 23503 21875 22646>, + <23503 25063 24966 22255 23786>, + <23364 26728 25863 23569 24665>, + <23874 27767 26627 25316 25537>, + <25339 28404 27366 26549 26565>, + <26580 28812 28051 27647 27783>, + <27299 28952 28637 28369 28438>, + <27859 29013 29244 28922 28605>, + <28127 28980 29596 29269 28749>, + <28121 28632 29354 28928 29008>, + <28035 28071 28613 27970 29397>, + <28032 27480 27672 27629 29838>, + <28024 26731 26146 27677 30769>, + <27889 25936 24626 27779 31609>, + <27436 24934 23369 28434 31801>, + <26929 24388 22499 29368 31887>, + <26421 24450 22608 28936 31937>, + <27988 25663 22852 26365 31185>, + <27430 25453 21972 22626 21099>, + <26554 25602 22352 22600 22211>, + <26806 23914 24361 22775 24450>, + <23478 23641 24736 23227 28936>, + <18946 23905 22228 28971 29716>, + <23561 21707 23990 27451 26335>, + <20333 21474 23601 25150 24619>, + <18967 20996 23606 23367 22997>, + <16796 21104 21653 24495 23716>, + <16796 21104 21653 24495 23716>, + <16796 21104 21653 24495 23716>; + }; + + qcom,pc-temp-z6-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <15776 15081 14574 14403 14378>, + <15822 15066 14611 14457 14412>, + <15728 15042 14587 14444 14404>, + <15561 14985 14560 14425 14386>, + <15434 14901 14531 14412 14376>, + <15332 14840 14504 14402 14371>, + <15250 14790 14491 14394 14367>, + <15184 14755 14482 14389 14362>, + <15130 14736 14475 14384 14359>, + <15088 14723 14469 14380 14356>, + <15057 14715 14464 14377 14353>, + <15033 14710 14459 14374 14350>, + <15014 14704 14454 14371 14348>, + <14997 14693 14451 14368 14345>, + <14991 14680 14450 14366 14342>, + <15002 14679 14449 14363 14338>, + <15017 14691 14448 14361 14335>, + <15016 14701 14446 14359 14333>, + <14999 14693 14443 14357 14331>, + <14987 14676 14438 14354 14328>, + <14985 14676 14433 14350 14326>, + <14985 14729 14451 14357 14329>, + <14996 14777 14500 14394 14362>, + <15054 14775 14519 14417 14387>, + <15101 14767 14512 14412 14383>, + <15097 14759 14503 14404 14374>, + <15080 14752 14497 14398 14368>, + <15067 14746 14492 14393 14365>, + <15057 14742 14488 14389 14362>, + <15050 14739 14484 14386 14358>, + <15047 14737 14482 14384 14356>, + <15045 14735 14480 14382 14353>, + <15045 14734 14478 14379 14350>, + <15046 14734 14478 14378 14347>, + <15047 14735 14478 14376 14345>, + <15049 14736 14479 14375 14343>, + <15050 14738 14480 14377 14345>, + <15052 14740 14481 14381 14354>, + <15055 14743 14482 14384 14358>, + <15061 14747 14484 14384 14358>, + <15065 14749 14485 14385 14359>, + <15066 14747 14482 14385 14359>, + <15067 14746 14478 14385 14360>, + <15067 14745 14478 14385 14361>, + <15047 14732 14473 14378 14356>, + <15035 14716 14457 14362 14333>, + <15030 14712 14451 14356 14327>, + <15027 14706 14445 14348 14320>, + <15020 14704 14442 14344 14318>, + <15023 14714 14450 14360 14336>, + <15046 14724 14459 14366 14341>, + <15055 14730 14462 14368 14344>, + <15068 14739 14467 14371 14347>, + <15088 14751 14472 14376 14351>, + <15088 14751 14472 14376 14351>, + <15088 14751 14472 14376 14351>; + }; + + qcom,pc-temp-y1-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <5821 5347 5037 4674 4481 4427>, + <5843 5351 5036 4672 4484 4429>, + <5865 5355 5035 4670 4485 4430>, + <5883 5361 5033 4667 4485 4430>, + <5897 5365 5031 4664 4484 4431>, + <5903 5367 5030 4660 4482 4431>, + <5900 5367 5025 4656 4477 4430>, + <5895 5365 5019 4650 4473 4429>, + <5896 5364 5014 4646 4472 4427>, + <5901 5359 5010 4643 4472 4425>, + <5903 5356 5008 4640 4472 4423>, + <5904 5358 5011 4637 4470 4422>, + <5908 5361 5015 4634 4468 4422>, + <5911 5361 5013 4632 4467 4421>, + <5920 5359 5004 4630 4465 4419>, + <5925 5358 5000 4629 4464 4419>, + <5922 5365 5003 4629 4464 4419>, + <5917 5374 5007 4629 4464 4419>, + <5917 5376 5008 4629 4464 4419>, + <5916 5373 5005 4630 4465 4419>, + <5914 5372 5003 4631 4465 4419>, + <5914 5377 5004 4633 4467 4420>, + <5916 5382 5005 4635 4469 4422>, + <5917 5383 5005 4638 4469 4422>, + <5917 5382 5006 4640 4469 4422>, + <5917 5382 5008 4643 4470 4423>, + <5915 5390 5013 4646 4472 4423>, + <5911 5400 5019 4650 4474 4424>, + <5907 5401 5024 4654 4476 4426>, + <5900 5398 5029 4659 4479 4428>, + <5896 5395 5032 4664 4481 4430>, + <5906 5395 5032 4669 4484 4431>, + <5922 5398 5032 4675 4487 4432>, + <5932 5401 5035 4679 4490 4434>, + <5943 5403 5043 4682 4493 4437>, + <5946 5405 5047 4686 4496 4440>, + <5933 5401 5047 4691 4499 4442>, + <5912 5395 5048 4695 4501 4444>, + <5901 5393 5053 4701 4504 4445>, + <5892 5393 5061 4707 4506 4446>, + <5887 5393 5065 4710 4509 4448>, + <5896 5394 5064 4713 4511 4451>, + <5900 5398 5066 4715 4513 4451>, + <5883 5418 5079 4717 4515 4451>, + <5915 5410 5075 4725 4518 4454>, + <5906 5399 5089 4726 4521 4456>, + <5899 5402 5088 4727 4519 4457>, + <5893 5400 5081 4734 4522 4457>, + <5894 5416 5082 4737 4521 4457>, + <5893 5422 5089 4735 4523 4458>, + <5951 5403 5099 4738 4525 4460>, + <5978 5411 5100 4752 4529 4462>, + <5943 5406 5107 4748 4534 4464>, + <5955 5420 5108 4757 4536 4469>, + <5955 5420 5108 4757 4536 4469>, + <5955 5420 5108 4757 4536 4469>; + }; + + qcom,pc-temp-y2-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <10091 10247 10509 10767 10785 10927>, + <10085 10259 10500 10740 10807 10958>, + <10082 10274 10489 10711 10818 10974>, + <10082 10288 10479 10684 10821 10978>, + <10084 10301 10470 10661 10818 10974>, + <10088 10309 10463 10643 10813 10967>, + <10129 10314 10458 10630 10787 10948>, + <10196 10318 10454 10619 10754 10920>, + <10242 10317 10452 10606 10748 10891>, + <10309 10310 10448 10589 10749 10854>, + <10343 10306 10446 10578 10750 10833>, + <10348 10349 10451 10581 10744 10834>, + <10361 10433 10462 10588 10735 10837>, + <10354 10516 10482 10588 10734 10833>, + <10267 10617 10525 10585 10733 10822>, + <10196 10671 10577 10591 10733 10816>, + <9993 10677 10646 10622 10733 10824>, + <9724 10679 10709 10670 10734 10837>, + <9677 10682 10732 10741 10732 10847>, + <9671 10689 10745 10841 10729 10857>, + <9668 10692 10750 10877 10736 10873>, + <9666 10695 10747 10828 10833 10914>, + <9664 10701 10743 10775 10940 10965>, + <9663 10698 10754 10784 10956 10999>, + <9661 10676 10777 10824 10960 11030>, + <9660 10640 10792 10857 10965 11054>, + <9659 10551 10798 10880 10972 11078>, + <9658 10416 10805 10900 10980 11102>, + <9657 10287 10820 10916 10994 11121>, + <9656 10134 10847 10930 11021 11137>, + <9656 10010 10858 10948 11048 11156>, + <9655 9913 10844 10989 11077 11185>, + <9655 9833 10824 11022 11105 11210>, + <9654 9791 10807 11021 11137 11220>, + <9654 9761 10786 11011 11170 11226>, + <9654 9737 10768 11005 11177 11228>, + <9654 9716 10753 11011 11139 11200>, + <9654 9699 10737 11017 11102 11170>, + <9653 9689 10712 11012 11096 11161>, + <9653 9681 10675 10996 11093 11144>, + <9653 9675 10616 10980 11081 11118>, + <9653 9671 10491 10961 11032 11066>, + <9653 9667 10377 10936 11009 11056>, + <9653 9664 10284 10902 11002 11096>, + <9653 9661 10205 10867 11000 10997>, + <9652 9659 10189 10820 10935 10941>, + <9652 9659 10170 10842 10880 10907>, + <9652 9658 10266 10786 10907 10898>, + <9652 9657 10342 10819 10926 10908>, + <9652 9656 10250 10823 10875 10851>, + <9652 9655 10037 10750 10829 10802>, + <9652 9654 9972 10651 10750 10766>, + <9651 9653 9891 10735 10690 10675>, + <9650 9653 10171 10679 10569 10544>, + <9650 9653 10171 10679 10569 10544>, + <9650 9653 10171 10679 10569 10544>; + }; + + qcom,pc-temp-y3-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <14020 13485 13348 13290 13276 13269>, + <13912 13484 13350 13290 13276 13270>, + <13847 13482 13351 13290 13277 13271>, + <13814 13481 13352 13290 13277 13272>, + <13802 13479 13353 13290 13278 13274>, + <13800 13477 13353 13290 13278 13274>, + <13846 13474 13353 13290 13278 13275>, + <13915 13471 13353 13289 13279 13275>, + <13881 13472 13353 13290 13279 13275>, + <13646 13477 13352 13291 13279 13275>, + <13499 13480 13351 13292 13280 13275>, + <13535 13470 13351 13294 13280 13276>, + <13592 13454 13351 13296 13280 13277>, + <13605 13449 13352 13297 13281 13277>, + <13589 13442 13356 13297 13282 13277>, + <13574 13436 13358 13298 13282 13277>, + <13544 13434 13352 13298 13282 13277>, + <13507 13429 13343 13300 13283 13277>, + <13503 13421 13341 13301 13284 13278>, + <13510 13403 13340 13302 13285 13280>, + <13517 13385 13338 13303 13286 13281>, + <13521 13372 13331 13298 13282 13278>, + <13523 13361 13323 13291 13278 13275>, + <13523 13352 13319 13288 13277 13274>, + <13533 13345 13316 13286 13277 13273>, + <13553 13338 13314 13285 13276 13272>, + <13593 13320 13311 13285 13277 13273>, + <13646 13299 13309 13285 13277 13273>, + <13696 13288 13308 13285 13276 13273>, + <13750 13271 13307 13286 13276 13273>, + <13806 13266 13305 13286 13275 13273>, + <13866 13268 13303 13285 13275 13273>, + <13929 13271 13301 13285 13275 13272>, + <13994 13274 13301 13285 13275 13272>, + <14060 13278 13303 13284 13276 13272>, + <14134 13284 13305 13284 13277 13272>, + <14220 13295 13307 13283 13276 13273>, + <14312 13311 13309 13282 13275 13273>, + <14405 13332 13311 13282 13275 13273>, + <14501 13362 13312 13282 13276 13274>, + <14596 13393 13313 13282 13276 13274>, + <14687 13416 13313 13282 13277 13274>, + <14781 13443 13314 13283 13277 13274>, + <14884 13488 13317 13284 13276 13273>, + <14998 13565 13322 13285 13276 13274>, + <14988 13596 13326 13288 13278 13276>, + <15059 13649 13330 13289 13279 13277>, + <15152 13712 13339 13294 13283 13279>, + <15247 13784 13351 13296 13282 13277>, + <15340 13847 13352 13295 13280 13276>, + <15443 13922 13355 13295 13281 13277>, + <15627 14060 13367 13298 13284 13279>, + <15865 14258 13384 13304 13286 13283>, + <16661 14530 13427 13312 13291 13287>, + <16661 14530 13427 13312 13291 13287>, + <16661 14530 13427 13312 13291 13287>; + }; + + qcom,pc-temp-y4-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <18008 16999 16718 16500 16460 16456>, + <18072 17065 16719 16497 16459 16454>, + <18111 17109 16717 16493 16457 16452>, + <18131 17135 16714 16489 16455 16451>, + <18138 17148 16709 16486 16453 16449>, + <18139 17152 16703 16485 16453 16448>, + <18029 17137 16693 16486 16452 16448>, + <17863 17112 16683 16486 16452 16447>, + <17896 17097 16681 16488 16452 16448>, + <18235 17083 16680 16490 16454 16449>, + <18508 17077 16680 16492 16455 16450>, + <18619 17111 16683 16496 16457 16451>, + <18700 17180 16689 16501 16461 16452>, + <18607 17260 16712 16509 16466 16453>, + <18107 17384 16786 16522 16473 16457>, + <17766 17446 16846 16538 16481 16462>, + <17718 17379 16883 16554 16487 16468>, + <17687 17259 16908 16574 16496 16475>, + <17629 17174 16905 16613 16516 16490>, + <17534 17108 16880 16675 16554 16516>, + <17407 17042 16841 16697 16568 16526>, + <17159 16963 16746 16628 16535 16505>, + <16891 16889 16644 16542 16492 16476>, + <16806 16845 16607 16507 16473 16463>, + <16770 16818 16587 16484 16461 16454>, + <16755 16786 16580 16478 16457 16452>, + <16753 16727 16578 16479 16457 16452>, + <16753 16673 16578 16480 16457 16452>, + <16756 16669 16579 16483 16459 16453>, + <16763 16685 16581 16490 16462 16455>, + <16771 16697 16581 16497 16467 16458>, + <16783 16705 16558 16506 16473 16464>, + <16797 16717 16535 16512 16481 16470>, + <16813 16732 16538 16515 16488 16475>, + <16831 16753 16552 16517 16495 16479>, + <16846 16769 16568 16515 16495 16479>, + <16858 16781 16587 16493 16474 16465>, + <16869 16791 16601 16473 16454 16451>, + <16877 16794 16600 16470 16450 16451>, + <16883 16792 16599 16468 16449 16452>, + <16885 16788 16599 16469 16448 16452>, + <16876 16770 16608 16474 16449 16451>, + <16865 16757 16618 16479 16448 16448>, + <16860 16757 16628 16481 16442 16435>, + <16879 16761 16645 16484 16444 16435>, + <16891 16789 16652 16498 16455 16453>, + <16943 16827 16682 16511 16475 16497>, + <17014 16881 16733 16537 16536 16562>, + <17081 16976 16802 16590 16557 16530>, + <17089 17020 16800 16563 16478 16467>, + <17047 16991 16801 16554 16477 16469>, + <17042 17006 16834 16584 16500 16488>, + <17105 17082 16903 16649 16553 16544>, + <17555 17233 17100 16828 16767 16718>, + <17555 17233 17100 16828 16767 16718>, + <17555 17233 17100 16828 16767 16718>; + }; + + qcom,pc-temp-y5-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <11727 11942 13506 16264 17485 13743>, + <11187 12181 13834 16304 17713 15443>, + <10948 12440 14154 16154 17943 16969>, + <10946 12689 14439 15889 18142 18238>, + <11119 12897 14661 15580 18277 19164>, + <11403 13035 14792 15300 18315 19661>, + <12465 13100 14855 14911 18249 19739>, + <13822 13150 14864 14518 18113 19553>, + <13670 13301 14746 14395 17867 19106>, + <11695 13714 14420 14341 17361 18217>, + <10462 13958 14096 14326 16853 17639>, + <11501 13114 13863 14506 16406 17596>, + <13219 11865 13624 14722 15945 17611>, + <13884 11823 13278 14498 15435 17295>, + <13848 12774 12797 13693 14834 16535>, + <13691 13748 12589 13309 14470 15845>, + <13167 14554 12751 13334 14271 15143>, + <12586 15195 13107 13390 14142 14574>, + <13020 15258 13900 13564 14152 14504>, + <14413 15027 15523 14068 14254 14631>, + <15535 14881 16342 14723 14446 14876>, + <15575 14923 16444 15913 15152 15787>, + <15061 15014 16478 16911 16165 16899>, + <14339 15197 16434 16931 17201 17475>, + <12334 15627 16343 16746 18331 17902>, + <11314 15978 16268 16667 18791 18109>, + <11399 15505 16100 16581 18776 18180>, + <11512 14520 15934 16533 18615 18169>, + <11525 13737 16028 16730 18175 18053>, + <11550 12045 16380 17082 17340 17858>, + <11588 11352 16565 17187 16713 17565>, + <11718 11445 16382 17060 16198 16814>, + <11865 11550 16160 16944 15883 16183>, + <11908 11637 16198 17254 16375 16323>, + <11980 11737 16327 17954 17689 16949>, + <12075 11818 16423 18152 18505 17767>, + <12422 11915 16495 17982 18987 19240>, + <12794 12071 16540 17734 19303 20755>, + <12843 12334 16444 17425 19669 21829>, + <12812 12824 16116 17020 20264 22723>, + <12740 13086 15663 16654 20463 22879>, + <12356 12741 14862 16171 20541 22449>, + <11882 12264 14369 16034 20626 22711>, + <11570 11949 14152 16151 21020 24835>, + <11487 11951 14006 15816 18734 20674>, + <11662 11903 13943 16003 17805 20181>, + <11655 12101 13682 15426 17094 17583>, + <11840 12432 13801 16015 16324 15006>, + <12476 12948 14155 15430 14898 14594>, + <12752 13151 14323 16256 17791 17272>, + <12081 13073 14285 16869 17629 17625>, + <11734 12858 14199 16707 19166 17889>, + <11770 12567 13945 17145 18317 18429>, + <11976 12244 15223 16959 17784 17367>, + <11976 12244 15223 16959 17784 17367>, + <11976 12244 15223 16959 17784 17367>; + }; + + qcom,pc-temp-y6-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <6551 5600 5220 4990 4943 4930>, + <6534 5605 5216 4988 4942 4931>, + <6511 5605 5211 4986 4942 4931>, + <6488 5601 5205 4984 4942 4931>, + <6470 5594 5199 4983 4942 4932>, + <6461 5584 5193 4982 4942 4932>, + <6460 5570 5186 4981 4942 4932>, + <6461 5554 5179 4980 4942 4932>, + <6450 5545 5174 4981 4942 4932>, + <6403 5538 5169 4981 4942 4933>, + <6375 5535 5166 4982 4943 4933>, + <6433 5536 5165 4984 4943 4933>, + <6517 5539 5164 4987 4945 4934>, + <6504 5548 5169 4989 4946 4935>, + <6362 5577 5191 4993 4949 4936>, + <6258 5593 5206 4998 4951 4938>, + <6231 5576 5210 5003 4954 4939>, + <6212 5543 5212 5009 4956 4942>, + <6209 5514 5211 5021 4962 4946>, + <6205 5486 5203 5040 4974 4955>, + <6199 5459 5190 5046 4978 4958>, + <6156 5431 5159 5023 4966 4950>, + <6101 5407 5125 4994 4951 4939>, + <6096 5397 5113 4982 4945 4934>, + <6119 5393 5107 4974 4941 4931>, + <6146 5387 5105 4972 4940 4930>, + <6186 5373 5105 4973 4940 4930>, + <6237 5359 5106 4974 4940 4931>, + <6285 5359 5108 4975 4940 4931>, + <6335 5374 5112 4978 4941 4932>, + <6386 5394 5113 4981 4942 4933>, + <6438 5418 5109 4984 4944 4934>, + <6491 5448 5106 4986 4946 4936>, + <6546 5478 5109 4988 4949 4938>, + <6603 5512 5120 4989 4952 4939>, + <6665 5547 5133 4989 4952 4939>, + <6732 5583 5145 4983 4946 4936>, + <6803 5621 5158 4978 4940 4932>, + <6876 5662 5167 4978 4940 4932>, + <6950 5708 5176 4978 4940 4933>, + <7022 5754 5186 4979 4940 4933>, + <7089 5799 5201 4982 4942 4934>, + <7157 5850 5219 4985 4942 4933>, + <7235 5915 5240 4987 4939 4929>, + <7330 6003 5272 4991 4941 4930>, + <7326 6045 5279 4998 4946 4937>, + <7395 6104 5304 5003 4952 4950>, + <7483 6173 5341 5014 4973 4970>, + <7577 6261 5385 5032 4978 4960>, + <7656 6331 5397 5024 4954 4941>, + <7727 6392 5417 5023 4955 4943>, + <7873 6517 5468 5035 4965 4950>, + <8078 6702 5539 5060 4982 4970>, + <8853 6954 5681 5120 5047 5023>, + <8853 6954 5681 5120 5047 5023>, + <8853 6954 5681 5120 5047 5023>; + }; + +}; diff --git a/qcom/sdxlemur-cdp.dtsi b/qcom/sdxlemur-cdp.dtsi index 3bac905149f5..768d9aaa521c 100644 --- a/qcom/sdxlemur-cdp.dtsi +++ b/qcom/sdxlemur-cdp.dtsi @@ -1,3 +1,5 @@ +#include "sdxlemur-pmic-overlay.dtsi" + &soc { }; diff --git a/qcom/sdxlemur-coresight.dtsi b/qcom/sdxlemur-coresight.dtsi new file mode 100644 index 000000000000..c95b7bfa8bba --- /dev/null +++ b/qcom/sdxlemur-coresight.dtsi @@ -0,0 +1,1540 @@ +&soc { + replicator_qdss: replicator@6046000 { + compatible = "arm,coresight-dynamic-replicator", + "arm,primecell"; + + reg = <0x6046000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator-qdss"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_cx_in_swao_out: endpoint { + remote-endpoint= + <&replicator_swao_out_cx_in>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + replicator0_out_tmc_etr: endpoint { + remote-endpoint= + <&tmc_etr_in_replicator0>; + }; + }; + + }; + }; + + replicator_swao: replicator@6b06000 { + compatible = "arm,coresight-dynamic-replicator", + "arm,primecell"; + + reg = <0x6b06000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator-swao"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_swao_in_tmc_etf_swao: endpoint { + remote-endpoint = + <&tmc_etf_swao_out_replicator_swao>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* Always have EUD before funnel leading to ETR. If both + * sink are active we need to give preference to EUD + * over ETR + */ + port@0 { + reg = <0>; + replicator_swao_out_cx_in: endpoint { + remote-endpoint = + <&replicator_cx_in_swao_out>; + }; + }; + + port@1 { + reg = <1>; + replicator_swao_out_eud: endpoint { + remote-endpoint = + <&eud_in_replicator_swao>; + }; + }; + }; + + }; + + dummy_eud: dummy_sink { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-eud"; + + qcom,dummy-sink; + in-ports { + port { + eud_in_replicator_swao: endpoint { + remote-endpoint = + <&replicator_swao_out_eud>; + }; + }; + }; + }; + + tmc_etf_swao: tmc@6b05000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + + reg = <0x6b05000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etf"; + coresight-csr = <&swao_csr>; + coresight-ctis = <&cti0 &cti6>; + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etf_swao_in_funnel_swao: endpoint { + remote-endpoint= + <&funnel_swao_out_tmc_etf_swao>; + }; + }; + }; + + out-ports { + port { + tmc_etf_swao_out_replicator_swao: endpoint { + remote-endpoint= + <&replicator_swao_in_tmc_etf_swao>; + }; + }; + + }; + }; + + tmc_etr: tmc@6048000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + + reg = <0x6048000 0x1000>, + <0x6064000 0x15000>; + reg-names = "tmc-base", "bam-base"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + arm,buffer-size = <0x400000>; + arm,scatter-gather; + + coresight-name = "coresight-tmc-etr"; + coresight-ctis = <&cti0 &cti6>; + coresight-csr = <&csr>; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + interrupts = ; + interrupt-names = "byte-cntr-irq"; + + in-ports { + port { + tmc_etr_in_replicator0: endpoint { + remote-endpoint = + <&replicator0_out_tmc_etr>; + }; + }; + }; + }; + + funnel_swao: funnel@6b04000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x6b04000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-swao"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + funnel_swao_in_tpda_swao: endpoint { + remote-endpoint = + <&tpda_swao_out_funnel_swao>; + }; + }; + + port@7 { + reg = <7>; + funnel_swao_in_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_out_funnel_swao>; + }; + }; + }; + + out-ports { + port { + funnel_swao_out_tmc_etf_swao: endpoint { + remote-endpoint = + <&tmc_etf_swao_in_funnel_swao>; + }; + }; + + }; + }; + + tpda_swao: tpda@6b08000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x6b08000 0x1000>; + reg-names = "tpda-base"; + coresight-name = "coresight-tpda-swao"; + + qcom,tpda-atid = <71>; + qcom,cmb-elem-size = <0 64>, + <1 64>, + <2 64>, + <3 64>; + qcom,dsb-elem-size = <4 32>; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpda_swao_out_funnel_swao: endpoint { + remote-endpoint = + <&funnel_swao_in_tpda_swao>; + }; + + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_swao_in_tpdm_swao_p0: endpoint { + remote-endpoint = + <&tpdm_swao_p0_out_tpda_swao>; + }; + }; + + port@1 { + reg = <1>; + tpda_swao_in_tpdm_swao_p1: endpoint { + remote-endpoint = + <&tpdm_swao_p1_out_tpda_swao>; + }; + }; + + port@2 { + reg = <2>; + tpda_swao_in_tpdm_swao_p2: endpoint { + remote-endpoint = + <&tpdm_swao_p2_out_tpda_swao>; + }; + }; + + port@3 { + reg = <3>; + tpda_swao_in_tpdm_swao_p3: endpoint { + remote-endpoint = + <&tpdm_swao_p3_out_tpda_swao>; + }; + }; + + port@4 { + reg = <4>; + tpda_swao_in_tpdm_swao1: endpoint { + remote-endpoint = + <&tpdm_swao1_out_tpda_swao>; + }; + }; + }; + }; + + tpdm_swao_p0: tpdm@6b09000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + + reg = <0x6b09000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-prio-0"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_p0_out_tpda_swao: endpoint { + remote-endpoint = + <&tpda_swao_in_tpdm_swao_p0>; + }; + }; + }; + }; + + tpdm_swao_p1: tpdm@6b0a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + + reg = <0x6b0a000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-prio-1"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_p1_out_tpda_swao: endpoint { + remote-endpoint = + <&tpda_swao_in_tpdm_swao_p1>; + }; + }; + }; + }; + + tpdm_swao_p2: tpdm@6b0b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + + reg = <0x6b0b000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-prio-2"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_p2_out_tpda_swao: endpoint { + remote-endpoint = + <&tpda_swao_in_tpdm_swao_p2>; + }; + }; + }; + }; + + tpdm_swao_p3: tpdm@6b0c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + + reg = <0x6b0c000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-prio-3"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_p3_out_tpda_swao: endpoint { + remote-endpoint = + <&tpda_swao_in_tpdm_swao_p3>; + }; + }; + }; + }; + + tpdm_swao1: tpdm@6b0d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6b0d000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name="coresight-tpdm-swao-1"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + out-ports { + port { + tpdm_swao1_out_tpda_swao: endpoint { + remote-endpoint = + <&tpda_swao_in_tpdm_swao1>; + }; + }; + }; + }; + + funnel_merg: funnel@6045000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x6045000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-merg"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_merg_out_funnel_swao: endpoint { + remote-endpoint = + <&funnel_swao_in_funnel_merg>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_merg_in_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_out_funnel_merg>; + }; + }; + + port@1 { + reg = <1>; + funnel_merg_in_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_out_funnel_merg>; + }; + }; + }; + }; + + stm: stm@6002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb962>; + + reg = <0x6002000 0x1000>, + <0x16280000 0x180000>, + <0x7820f0 0x4>; + reg-names = "stm-base", "stm-stimulus-base", "stm-debug-status"; + + coresight-name = "coresight-stm"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_stm>; + }; + }; + }; + }; + + csr: csr@6001000 { + compatible = "qcom,coresight-csr"; + reg = <0x6001000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-csr"; + qcom,usb-bam-support; + qcom,hwctrl-set-support; + qcom,set-byte-cntr-support; + + qcom,blk-size = <1>; + }; + + swao_csr: csr@6b0f000 { + compatible = "qcom,coresight-csr"; + reg = <0x6b0f000 0x1000>, + <0x6b0f0f8 0x50>; + reg-names = "csr-base", "msr-base"; + + coresight-name = "coresight-swao-csr"; + qcom,timestamp-support; + qcom,msr-support; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,blk-size = <1>; + }; + + funnel_in0: funnel@6041000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x6041000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in0"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_in0_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@6 { + reg = <6>; + funnel_in0_in_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_out_funnel_in0>; + }; + }; + + port@7 { + reg = <7>; + funnel_in0_in_stm: endpoint { + remote-endpoint = <&stm_out_funnel_in0>; + }; + }; + }; + }; + + funnel_in1: funnel@6042000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x6042000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in1"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_in1_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in1>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_in1_in_etm0: endpoint { + remote-endpoint = + <&etm_out_funnel_in1>; + }; + }; + + port@2 { + reg = <2>; + funnel_in1_in_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_out_funnel_in1>; + }; + }; + }; + }; + + funnel_modem: funnel@6804000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x6804000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-modem"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_modem_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_modem>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_modem_in_tpda_modem: endpoint { + remote-endpoint = + <&tpda_modem_out_funnel_modem>; + }; + }; + + port@1 { + reg = <1>; + funnel_modem_in_modem2_etm0: endpoint { + remote-endpoint = + <&modem2_etm0_out_funnel_modem>; + }; + }; + + port@2 { + reg = <2>; + funnel_modem_in_funnel_modem_q6: endpoint { + remote-endpoint = + <&funnel_modem_q6_out_funnel_modem>; + }; + }; + }; + }; + + modem2_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem2-etm0"; + qcom,inst-id = <11>; + + out-ports { + port { + modem2_etm0_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_modem2_etm0>; + }; + }; + }; + }; + + funnel_modem_q6: funnel@680c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x680c000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-modem-q6"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_modem_q6_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_funnel_modem_q6>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_modem_q6_in_modem_etm0: endpoint { + remote-endpoint = + <&modem_etm0_out_funnel_modem_q6>; + }; + }; + }; + }; + + modem_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem-etm0"; + qcom,inst-id = <2>; + + out-ports { + port { + modem_etm0_out_funnel_modem_q6: endpoint { + remote-endpoint = + <&funnel_modem_q6_in_modem_etm0>; + }; + }; + }; + }; + + tpda_modem: tpda@6803000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x6803000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-modem"; + + qcom,tpda-atid = <67>; + qcom,dsb-elem-size = <0 32>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpda_modem_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_tpda_modem>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_modem_in_tpdm_modem_0: endpoint { + remote-endpoint = + <&tpdm_modem_0_out_tpda_modem>; + }; + }; + + port@1 { + reg = <1>; + tpda_modem_in_tpdm_modem_1: endpoint { + remote-endpoint = + <&tpdm_modem_1_out_tpda_modem>; + }; + }; + }; + }; + + tpdm_modem_0: tpdm@6800000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6800000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name="coresight-tpdm-modem-0"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + out-ports { + port { + tpdm_modem_0_out_tpda_modem: endpoint { + remote-endpoint = <&tpda_modem_in_tpdm_modem_0>; + }; + }; + }; + }; + + tpdm_modem_1: tpdm@6801000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6801000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name="coresight-tpdm-modem-1"; + + status = "disabled"; + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + out-ports { + port { + tpdm_modem_1_out_tpda_modem: endpoint { + remote-endpoint = <&tpda_modem_in_tpdm_modem_1>; + }; + }; + }; + }; + + funnel_qatb: funnel@6005000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x6005000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-qatb"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_qatb_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_qatb>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_qatb_in_tpda: endpoint { + remote-endpoint = + <&tpda_out_funnel_qatb>; + }; + }; + + }; + }; + + tpda: tpda@6004000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x6004000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda"; + + qcom,tpda-atid = <65>; + qcom,bc-elem-size = <25 32>, + <31 32>; + qcom,tc-elem-size = <31 32>; + qcom,dsb-elem-size = <0 32>, + <6 32>, + <27 32>; + qcom,cmb-elem-size = <6 32>, + <25 32>, + <26 32>, + <28 32>, + <29 32>, + <30 64>, + <31 32>; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpda_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_tpda>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_in_tpdm_center2: endpoint { + remote-endpoint = + <&tpdm_center2_out_tpda>; + }; + }; + + port@6 { + reg = <6>; + tpda_in_funnel_ddr_0: endpoint { + remote-endpoint = + <&funnel_ddr_0_out_tpda>; + }; + }; + + port@19 { + reg = <25>; + tpda_in_tpdm_vsense: endpoint { + remote-endpoint = + <&tpdm_vsense_out_tpda>; + }; + }; + + port@1a { + reg = <26>; + tpda_in_tpdm_dcc: endpoint { + remote-endpoint = + <&tpdm_dcc_out_tpda>; + }; + }; + + port@1b { + reg = <27>; + tpda_in_tpdm_center1: endpoint { + remote-endpoint = + <&tpdm_center1_out_tpda>; + }; + }; + + port@1c { + reg = <28>; + tpda_in_tpdm_prng: endpoint { + remote-endpoint = + <&tpdm_prng_out_tpda>; + }; + }; + + port@1d { + reg = <29>; + tpda_in_tpdm_spdm: endpoint { + remote-endpoint = + <&tpdm_spdm_out_tpda>; + }; + }; + + port@1e { + reg = <30>; + tpda_in_tpdm_ipa: endpoint { + remote-endpoint = + <&tpdm_ipa_out_tpda>; + }; + }; + + port@1f { + reg = <31>; + tpda_in_tpdm_sdcc: endpoint { + remote-endpoint = + <&tpdm_sdcc_out_tpda>; + }; + }; + }; + }; + + tpdm_dcc: tpdm@6870000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6870000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dcc"; + + qcom,hw-enable-check; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_dcc_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_dcc>; + }; + }; + }; + }; + + tpdm_vsense: tpdm@6840000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6840000 0x1000>; + reg-names = "tpdm-base"; + + status = "disabled"; + coresight-name = "coresight-tpdm-vsense"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_vsense_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_tpdm_vsense>; + }; + }; + }; + }; + + tpdm_center1: tpdm@6c28000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x06c28000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-center-1"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_center1_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_tpdm_center1>; + }; + }; + }; + }; + + tpdm_center2: tpdm@69c1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x069c1000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-center-2"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_center2_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_tpdm_center2>; + }; + }; + }; + }; + + tpdm_ipa: tpdm@6858000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x06858000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ipa"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ipa_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_tpdm_ipa>; + }; + }; + }; + }; + + tpdm_sdcc: tpdm@69c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x069c0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-sdcc"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + out-ports { + port { + tpdm_sdcc_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_tpdm_sdcc>; + }; + }; + }; + }; + + tpdm_prng: tpdm@06990000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x06990000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-prng"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_prng_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_tpdm_prng>; + }; + }; + }; + }; + + tpdm_spdm: tpdm@600f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x600f000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-spdm"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_spdm_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_spdm>; + }; + }; + }; + }; + + funnel_ddr_0: funnel@69e2000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x069e2000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-ddr-0"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_ddr_0_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_funnel_ddr_0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_ddr_0_in_tpdm_ddr: endpoint { + remote-endpoint = + <&tpdm_ddr_out_funnel_ddr_0>; + }; + }; + }; + }; + + tpdm_ddr: tpdm@69e0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x069e0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + qcom,msr-fix-req; + + out-ports { + port { + tpdm_ddr_out_funnel_ddr_0: endpoint { + remote-endpoint = + <&funnel_ddr_0_in_tpdm_ddr>; + }; + }; + }; + }; + + etm0: etm@7002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb956>; + + reg = <0x7002000 0x1000>; + cpu = <&CPU0>; + + qcom,tupwr-disable; + coresight-name = "coresight-coresight-etm0"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_etm0>; + }; + }; + }; + }; + + hwevent { + compatible = "qcom,coresight-hwevent"; + + coresight-name = "coresight-hwevent"; + coresight-csr = <&csr>; + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + ipcb_tgu: tgu@6b0e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b999>; + reg = <0x06b0e000 0x1000>; + reg-names = "tgu-base"; + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <4>; + tgu-timer-counters = <8>; + + coresight-name = "coresight-tgu-ipcb"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_ddr0: cti@69e1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x069e1000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_0_cti_0"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_ddr1: cti@69e4000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x069e4000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_1_cti_0"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_ddr1: cti@69e5000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x069e5000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_1_cti_1"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0: cti@6010000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6010000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti0"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti1: cti@6011000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6011000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti1"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti2: cti@6012000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6012000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti2"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti3: cti@6013000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6013000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti3"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti4: cti@6014000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6014000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti4"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti5: cti@6015000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6015000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti5"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti6: cti@6016000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6016000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti6"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti7: cti@6017000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6017000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti7"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti8: cti@6018000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6018000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti8"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti9: cti@6019000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6019000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti9"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti10: cti@601a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x601a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti10"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti11: cti@601b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x601b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti11"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti12: cti@601c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x601c000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti12"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti13: cti@601d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x601d000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti13"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti14: cti@601e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x601e000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti14"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti15: cti@601f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x601f000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti15"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti_a7ss: cti@7003000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x7003000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-a7ss"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + + cti0_swao:cti@6b00000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6b00000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti0"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_swao:cti@6b01000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6b01000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti1"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti2_swao:cti@6b02000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6b02000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti2"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti3_swao:cti@6b03000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6b03000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti3"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cortex_m3:cti@6b11000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6b11000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cortex_m3"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_mss_q6:cti@680b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x0680b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-mss_q6_cti"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_mss_vq6:cti@6813000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x6813000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-mss_vq6_cti"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "apb_pclk"; + }; +}; diff --git a/qcom/sdxlemur-mtp.dtsi b/qcom/sdxlemur-mtp.dtsi index 3bac905149f5..768d9aaa521c 100644 --- a/qcom/sdxlemur-mtp.dtsi +++ b/qcom/sdxlemur-mtp.dtsi @@ -1,3 +1,5 @@ +#include "sdxlemur-pmic-overlay.dtsi" + &soc { }; diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi new file mode 100644 index 000000000000..b411c80be87f --- /dev/null +++ b/qcom/sdxlemur-pcie.dtsi @@ -0,0 +1,117 @@ +&soc { + pcie0: qcom,pcie@1c00000 { + compatible = "qcom,pci-msm"; + + reg = <0x1c00000 0x3000>, + <0x1c06000 0x2000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf"; + + cell-index = <0>; + linux,pci-domain = <0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>; + + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + + msi-parent = <&pcie0_msi>; + + perst-gpio = <&tlmm 57 0>; + wake-gpio = <&tlmm 53 0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + pinctrl-1 = <&pcie0_clkreq_sleep + &pcie0_perst_default + &pcie0_wake_default>; + + gdsc-vdd-supply = <&gcc_pcie_gdsc>; + vreg-1.8-supply = <&pmx65_l1>; + vreg-0.9-supply = <&pmx65_l4>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + qcom,vreg-1.8-voltage-level = <1200000 1200000 30000>; + qcom,vreg-0.9-voltage-level = <912000 912000 132000>; + qcom,vreg-cx-voltage-level = ; + qcom,bw-scale = + ; /* Gen4 */ + + interconnect-names = "icc_path"; + interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_RCHNG_PHY_CLK>, + <&gcc GCC_PCIE_PIPE_CLK_SRC>, + <&gcc PCIE_PIPE_CLK>; + + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", + "pcie_0_sleep_clk", "pcie_phy_refgen_clk", + "pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src"; + max-clock-frequency-hz = <0>, <0>, <0>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>, + <0>; + + resets = <&gcc GCC_PCIE_BCR>, + <&gcc GCC_PCIE_PHY_BCR>; + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + + qcom,smmu-sid-base = <0x0200>; + iommu-map = <0x0 &apps_smmu 0x0200 0x1>, + <0x100 &apps_smmu 0x0201 0x1>; + + qcom,boot-option = <0x1>; + qcom,use-19p2mhz-aux-clk; + qcom,slv-addr-space-size = <0x40000000>; + qcom,ep-latency = <10>; + + qcom,pcie-phy-ver = <0>; + qcom,phy-status-offset = <0x1214>; + qcom,phy-status-bit = <7>; + qcom,phy-power-down-offset = <0x1240>; + + pcie0_rp: pcie0_rp { + reg = <0 0 0 0 0>; + }; + }; + + pcie0_msi: qcom,pcie0_msi@a0000000 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0xa0000000 0x0>; + interrupt-parent = <&intc>; + interrupts = ; + qcom,snps; + }; +}; diff --git a/qcom/sdxlemur-pinctrl.dtsi b/qcom/sdxlemur-pinctrl.dtsi index 30f42d914e77..771cf1df3a0f 100644 --- a/qcom/sdxlemur-pinctrl.dtsi +++ b/qcom/sdxlemur-pinctrl.dtsi @@ -39,5 +39,59 @@ bias-disable; }; }; + + pcie0 { + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio56"; + function = "pcie_clkreq"; + }; + + config { + pins = "gpio56"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio57"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_clkreq_sleep: pcie0_clkreq_sleep { + mux { + pins = "gpio56"; + function = "gpio"; + }; + + config { + pins = "gpio56"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; }; }; diff --git a/qcom/sdxlemur-pmic-overlay.dtsi b/qcom/sdxlemur-pmic-overlay.dtsi new file mode 100644 index 000000000000..67995251e247 --- /dev/null +++ b/qcom/sdxlemur-pmic-overlay.dtsi @@ -0,0 +1,8 @@ +#include "pmk8350.dtsi" +#include "pmx65.dtsi" +#include "pm7250b.dtsi" + +&pm7250b_clkdiv { + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; +}; diff --git a/qcom/sdxlemur-rumi.dtsi b/qcom/sdxlemur-rumi.dtsi index e9849a017bdd..f7394765df36 100644 --- a/qcom/sdxlemur-rumi.dtsi +++ b/qcom/sdxlemur-rumi.dtsi @@ -1,3 +1,5 @@ +#include "sdxlemur-pmic-overlay.dtsi" + &soc { timer { clock-frequency = <96000>; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 78b602a8a669..9eb6143d4074 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -2,6 +2,7 @@ #include #include #include +#include #include #include #include @@ -15,7 +16,9 @@ qcom,msm-id = <458 0x10000>; interrupt-parent = <&intc>; - aliases { }; + aliases { + pci-domain0 = &pcie0; /* PCIe0 domain */ + }; chosen { }; @@ -107,6 +110,11 @@ #size-cells = <1>; ranges; + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + intc: interrupt-controller@17800000 { compatible = "qcom,msm-qgic2"; interrupt-controller; @@ -197,6 +205,17 @@ reg-names = "pshold-base", "tcsr-boot-misc-detect"; }; + dcc: dcc_v2@117f000 { + compatible = "qcom,dcc-v2"; + reg = <0x117f000 0x1000>, + <0x1100000 0x2000>; + + qcom,transaction_timeout = <0>; + + reg-names = "dcc-base", "dcc-ram-base"; + dcc-ram-offset = <0x800>; + }; + watchdog: qcom,wdt@17817000 { compatible = "qcom,msm-watchdog"; reg = <0x17817000 0x1000>; @@ -294,7 +313,7 @@ clocks { xo_board: xo-board { compatible = "fixed-clock"; - clock-frequency = <38400000>; + clock-frequency = <76800000>; clock-output-names = "xo_board"; #clock-cells = <0>; }; @@ -305,12 +324,26 @@ clock-output-names = "sleep_clk"; #clock-cells = <0>; }; + + pcie_pipe_clk: pcie-0-pipe-clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_pipe_clk"; + #clock-cells = <0>; + }; + + usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + #clock-cells = <0>; + }; }; bi_tcxo: bi_tcxo { compatible = "fixed-factor-clock"; clock-mult = <1>; - clock-div = <2>; + clock-div = <4>; clocks = <&xo_board>; #clock-cells = <0>; }; @@ -318,16 +351,16 @@ bi_tcxo_ao: bi_tcxo_ao { compatible = "fixed-factor-clock"; clock-mult = <1>; - clock-div = <2>; + clock-div = <4>; clocks = <&xo_board>; #clock-cells = <0>; }; aopcc: clock-controller@0 { - compatible = "qcom,dummycc"; - clock-output-names = "aopcc_clocks"; + compatible = "qcom,aop-qmp-clk"; + mboxes = <&qmp_aop 0>; + mbox-names = "qdss_clk"; #clock-cells = <1>; - #reset-cells = <1>; }; rpmhcc: clock-controller@1 { @@ -379,6 +412,10 @@ , ; + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; + system_pm { compatible = "qcom,system-pm"; }; @@ -408,17 +445,25 @@ system_noc: interconnect@1620000 { compatible = "qcom,sdxlemur-system_noc"; + reg = <0x1620000 0x31200>; #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; }; mem_noc: interconnect@9680000 { compatible = "qcom,sdxlemur-mem_noc"; + reg = <0x9680000 0x27200>; #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; }; mc_virt: interconnect { compatible = "qcom,sdxlemur-mc_virt"; #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos" + qcom,bcm-voters = <&apps_bcm_voter>; }; tcsr_mutex_block: syscon@1f40000 { @@ -432,6 +477,15 @@ #hwlock-cells = <1>; }; + cache-controller@9200000 { + compatible = "qcom,sdxlemur-llcc", "qcom,llcc-v2"; + reg = <0x9200000 0x50000>; + reg-names = "llcc_base"; + cap-based-alloc-and-pwr-collapse; + clocks = <&aopcc QDSS_CLK>; + clock-names = "aopcc_closks"; + }; + smem: qcom,smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; @@ -587,6 +641,28 @@ qcom-secure-buffer { compatible = "qcom,secure-buffer"; }; + + spmi_bus: qcom,spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0xd00>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>, + <0xe700000 0xa0000>, + <0xc40a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + }; + + thermal_zones: thermal-zones { + }; }; #include "sdxlemur-pinctrl.dtsi" @@ -595,3 +671,4 @@ #include "sdxlemur-ion.dtsi" #include "sdxlemur-usb.dtsi" #include "sdxlemur-pm.dtsi" +#include "sdxlemur-pcie.dtsi" diff --git a/qcom/shima-atp.dtsi b/qcom/shima-atp.dtsi index 366890de4759..6ae9ea2b9643 100644 --- a/qcom/shima-atp.dtsi +++ b/qcom/shima-atp.dtsi @@ -1 +1,21 @@ #include "shima-idp.dtsi" + +&pm8008i_chip { + status = "disabled"; +}; + +&pm8008i_ldo { + status = "disabled"; +}; + +&pm8008j_chip { + status = "disabled"; +}; + +&pm8008j_ldo { + status = "disabled"; +}; + +&pm8350c_flash { + status = "disabled"; +}; diff --git a/qcom/shima-audio-overlay.dtsi b/qcom/shima-audio-overlay.dtsi index 01dcdc9278a5..7fa2ddfaf415 100644 --- a/qcom/shima-audio-overlay.dtsi +++ b/qcom/shima-audio-overlay.dtsi @@ -57,7 +57,7 @@ qcom,mipi-sdw-block-packing-mode = <1>; swrm-io-base = <0x3230000 0x0>; interrupts-extended = - <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "swr_master_irq", "swr_wake_irq"; qcom,swr-num-ports = <3>; @@ -242,9 +242,11 @@ }; &shima_snd { - qcom,model = "shima-idp-snd-card"; + qcom,model = "lahaina-shimaidp-snd-card"; qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>; - qcom,wcn-btfm = <0>; + qcom,wcn-bt = <1>; + qcom,tdm-max-slots = <8>; + qcom,wcd-disabled = <0>; qcom,ext-disp-audio-rx = <0>; qcom,audio-routing = "AMIC1", "Analog Mic1", @@ -294,11 +296,11 @@ "VA DMIC3", "Digital Mic3", "VA DMIC4", "Digital Mic4", "VA DMIC5", "Digital Mic5", - "VA DMIC0", "VA MIC BIAS3", + "VA DMIC0", "VA MIC BIAS1", "VA DMIC1", "VA MIC BIAS3", - "VA DMIC2", "VA MIC BIAS1", + "VA DMIC2", "VA MIC BIAS4", "VA DMIC3", "VA MIC BIAS1", - "VA DMIC4", "VA MIC BIAS4", + "VA DMIC4", "VA MIC BIAS3", "VA DMIC5", "VA MIC BIAS4"; qcom,msm-mbhc-hphl-swh = <1>; qcom,msm-mbhc-gnd-swh = <1>; @@ -308,13 +310,17 @@ qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>; asoc-codec = <&stub_codec>, <&bolero>, <&wcd938x_codec>, <&swr_haptics>, - <&wsa883x_0221>, <&wsa883x_0222>, - <&ext_disp_audio_codec>; + <&wsa883x_0221>, <&wsa883x_0222>; asoc-codec-names = "msm-stub-codec.1", "bolero_codec", "wcd938x_codec", "swr-haptics", - "wsa-codec1", "wsa-codec2", - "msm-ext-disp-audio-codec-rx"; + "wsa-codec1", "wsa-codec2"; qcom,wsa-max-devs = <2>; + qcom,cps_reg_phy_addr = <0x3250300 0x3250304 0x3250318>; + qcom,cps_wsa_vbatt_temp_reg_addr = <0x0000429 0x0000422>; + qcom,cps_threshold_levels = <148 168>; + qcom,cps_normal_values = <0x8E 0x8F 0x8F>; + qcom,cps_lower1_values = <0x10 0xD0 0xD0>; + qcom,cps_lower2_values = <0x0F 0x0F 0x18>; qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>, <&bolero>; }; diff --git a/qcom/shima-audio.dtsi b/qcom/shima-audio.dtsi index 3e553b6d7e27..752938f13ecf 100644 --- a/qcom/shima-audio.dtsi +++ b/qcom/shima-audio.dtsi @@ -7,6 +7,10 @@ }; &audio_apr { + msm_audio_ion_cma: qcom,msm-audio-ion-cma { + compatible = "qcom,msm-audio-ion-cma"; + }; + q6core: qcom,q6core-audio { compatible = "qcom,q6core-audio"; #address-cells = <1>; @@ -47,8 +51,10 @@ <0x00000000>, <0x00000000>, <0x00000006>; - clock-names = "lpass_core_hw_vote"; - clocks = <&lpass_core_hw_vote 0>; + clock-names = "lpass_core_hw_vote", + "lpass_audio_hw_vote"; + clocks = <&lpass_core_hw_vote 0>, + <&lpass_audio_hw_vote 0>; }; bolero: bolero-cdc { @@ -152,7 +158,7 @@ &q6core { shima_snd: sound { compatible = "qcom,lahaina-asoc-snd"; - qcom,mi2s-audio-intf = <0>; + qcom,mi2s-audio-intf = <1>; qcom,auxpcm-audio-intf = <1>; qcom,wcn-bt = <0>; qcom,ext-disp-audio-rx = <0>; diff --git a/qcom/shima-coresight.dtsi b/qcom/shima-coresight.dtsi index 12c2d5480587..74d196646886 100644 --- a/qcom/shima-coresight.dtsi +++ b/qcom/shima-coresight.dtsi @@ -107,6 +107,7 @@ coresight-name = "coresight-tmc-etf"; coresight-csr = <&swao_csr>; + coresight-ctis = <&cti0_swao &cti3_swao>; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; @@ -153,7 +154,7 @@ qcom,sw-usb; coresight-name = "coresight-tmc-etr"; - coresight-ctis = <&cti0 &cti0>; + coresight-ctis = <&cti0 &cti3_swao>; coresight-csr = <&csr>; clocks = <&aopcc QDSS_CLK>; diff --git a/qcom/shima-gpu.dtsi b/qcom/shima-gpu.dtsi index db2ebcd2e135..18e0d559920e 100644 --- a/qcom/shima-gpu.dtsi +++ b/qcom/shima-gpu.dtsi @@ -28,13 +28,19 @@ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>, <&aopcc QDSS_CLK>, - <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>; clock-names = "gcc_gpu_memnoc_gfx", "gcc_gpu_snoc_dvm_gfx", "gpu_cc_ahb", "apb_pclk", - "gpu_cc_hlos1_vote_gpu_smmu_clk"; + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_cx_gmu", + "gpu_cc_hub_aon", + "gpu_cc_hub_cx_int"; qcom,chipid = <0x06060001>; @@ -135,12 +141,12 @@ #size-cells = <0>; qcom,speed-bin = <0>; - qcom,initial-pwrlevel = <2>; + qcom,initial-pwrlevel = <4>; qcom,gpu-pwrlevel@0 { reg = <0>; - qcom,gpu-freq = <490000000>; - qcom,level = ; + qcom,gpu-freq = <676000000>; + qcom,level = ; qcom,bus-freq-ddr7 = <11>; qcom,bus-min-ddr7 = <10>; @@ -153,6 +159,34 @@ qcom,gpu-pwrlevel@1 { reg = <1>; + qcom,gpu-freq = <608000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <10>; + qcom,bus-min-ddr7 = <9>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <9>; + qcom,bus-min-ddr8 = <8>; + qcom,bus-max-ddr8 = <11>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <540000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <9>; + qcom,bus-min-ddr7 = <8>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <8>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <10>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <443000000>; qcom,level = ; @@ -165,8 +199,8 @@ qcom,bus-max-ddr8 = <9>; }; - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <285000000>; qcom,level = ; @@ -271,24 +305,10 @@ #size-cells = <0>; qcom,speed-bin = <158>; - qcom,initial-pwrlevel = <5>; + qcom,initial-pwrlevel = <4>; qcom,gpu-pwrlevel@0 { reg = <0>; - qcom,gpu-freq = <747000000>; - qcom,level = ; - - qcom,bus-freq-ddr7 = <11>; - qcom,bus-min-ddr7 = <11>; - qcom,bus-max-ddr7 = <11>; - - qcom,bus-freq-ddr8 = <11>; - qcom,bus-min-ddr8 = <10>; - qcom,bus-max-ddr8 = <11>; - }; - - qcom,gpu-pwrlevel@1 { - reg = <1>; qcom,gpu-freq = <676000000>; qcom,level = ; @@ -296,13 +316,13 @@ qcom,bus-min-ddr7 = <10>; qcom,bus-max-ddr7 = <11>; - qcom,bus-freq-ddr8 = <10>; + qcom,bus-freq-ddr8 = <11>; qcom,bus-min-ddr8 = <9>; qcom,bus-max-ddr8 = <11>; }; - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@1 { + reg = <1>; qcom,gpu-freq = <608000000>; qcom,level = ; @@ -315,8 +335,8 @@ qcom,bus-max-ddr8 = <11>; }; - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <540000000>; qcom,level = ; @@ -329,8 +349,8 @@ qcom,bus-max-ddr8 = <10>; }; - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <443000000>; qcom,level = ; @@ -343,8 +363,8 @@ qcom,bus-max-ddr8 = <9>; }; - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <285000000>; qcom,level = ; diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index f36c41467a2d..59393be31289 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -2,6 +2,8 @@ #include #include "shima-pmic-overlay.dtsi" #include "display/shima-sde-display-idp.dtsi" +#include "shima-thermal-overlay.dtsi" +#include "shima-audio-overlay.dtsi" &soc { gpio_keys { @@ -23,6 +25,27 @@ }; }; +&qupv3_se9_i2c { + status = "ok"; + qcom,clk-freq-out = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 87 0x00>; + qcom,sn-ven = <&tlmm 62 0x00>; + qcom,sn-firm = <&tlmm 86 0x00>; + qcom,sn-clkreq = <&tlmm 63 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <87 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + &sdhc_1 { status = "ok"; @@ -155,8 +178,18 @@ pinctrl-2 = <&ts_release>; panel = <&dsi_r66451_amoled_cmd - &dsi_r66451_amoled_video>; + &dsi_r66451_amoled_video + &dsi_r66451_amoled_60hz_video>; }; }; +&dai_mi2s2 { + qcom,msm-mi2s-tx-lines = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active + &tert_mi2s_sd0_active>; + pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep + &tert_mi2s_sd0_sleep>; +}; + #include "camera/shima-camera-sensor-idp.dtsi" diff --git a/qcom/shima-idps-digital-mics.dtsi b/qcom/shima-idps-digital-mics.dtsi index 17f1e228977f..c2cd1782aca2 100644 --- a/qcom/shima-idps-digital-mics.dtsi +++ b/qcom/shima-idps-digital-mics.dtsi @@ -1,2 +1,83 @@ +#include "shima-idp.dtsi" + &soc { }; + +&shima_snd { + qcom,model = "lahaina-shimaidps-snd-card"; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>; + qcom,wcn-bt = <1>; + qcom,tdm-max-slots = <8>; + qcom,wcd-disabled = <0>; + qcom,ext-disp-audio-rx = <0>; + qcom,audio-routing = + "AMIC1", "Analog Mic1", + "Analog Mic1", "MIC BIAS3", + "AMIC2", "Analog Mic2", + "Analog Mic2", "MIC BIAS2", + "AMIC3", "Analog Mic3", + "Analog Mic3", "MIC BIAS3", + "AMIC4", "Analog Mic4", + "Analog Mic4", "MIC BIAS1", + "AMIC5", "Analog Mic5", + "Analog Mic5", "MIC BIAS4", + "TX DMIC0", "Digital Mic0", + "TX DMIC0", "MIC BIAS1", + "TX DMIC1", "Digital Mic1", + "TX DMIC1", "MIC BIAS3", + "TX DMIC2", "Digital Mic2", + "TX DMIC2", "MIC BIAS4", + "TX DMIC3", "Digital Mic3", + "TX DMIC3", "MIC BIAS1", + "TX DMIC4", "Digital Mic4", + "TX DMIC4", "MIC BIAS3", + "TX DMIC5", "Digital Mic5", + "TX DMIC5", "MIC BIAS4", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "IN3_AUX", "AUX_OUT", + "HAP_IN", "PCM_OUT", + "WSA SRC0_INP", "SRC0", + "WSA_TX DEC0_INP", "TX DEC0 MUX", + "WSA_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "TX SWR_INPUT", "WCD_TX_OUTPUT", + "VA SWR_INPUT", "VA_SWR_CLK", + "VA SWR_INPUT", "WCD_TX_OUTPUT", + "VA_AIF1 CAP", "VA_SWR_CLK", + "VA_AIF2 CAP", "VA_SWR_CLK", + "VA_AIF3 CAP", "VA_SWR_CLK", + "VA DMIC0", "Digital Mic0", + "VA DMIC1", "Digital Mic1", + "VA DMIC2", "Digital Mic2", + "VA DMIC3", "Digital Mic3", + "VA DMIC4", "Digital Mic4", + "VA DMIC5", "Digital Mic5", + "VA DMIC0", "VA MIC BIAS3", + "VA DMIC1", "VA MIC BIAS3", + "VA DMIC2", "VA MIC BIAS1", + "VA DMIC3", "VA MIC BIAS1", + "VA DMIC4", "VA MIC BIAS4", + "VA DMIC5", "VA MIC BIAS4"; + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + qcom,swr-dmic-max-devs = <0>; + qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; + qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; + qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>; + asoc-codec = <&stub_codec>, <&bolero>, + <&wcd938x_codec>, <&swr_haptics>, + <&wsa883x_0221>, <&wsa883x_0222>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec", + "wcd938x_codec", "swr-haptics", + "wsa-codec1", "wsa-codec2"; + qcom,wsa-max-devs = <2>; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>, + <&bolero>; +}; + diff --git a/qcom/shima-ion.dtsi b/qcom/shima-ion.dtsi index cadb13713077..fc45b51bedde 100644 --- a/qcom/shima-ion.dtsi +++ b/qcom/shima-ion.dtsi @@ -16,6 +16,15 @@ qcom,ion-heap-type = "SYSTEM_SECURE"; }; + qcom,ion-heap@14 { /* SECURE CARVEOUT HEAP */ + reg = ; + qcom,ion-heap-type = "SECURE_CARVEOUT"; + cdsp { + memory-region = <&cdsp_secure_heap_mem>; + token = <0x20000000>; + }; + }; + qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */ reg = ; memory-region = <&secure_display_memory>; @@ -39,5 +48,10 @@ memory-region = <&qseecom_mem>; qcom,ion-heap-type = "DMA"; }; + qcom,ion-heap@5 { /* AUDIO ML HEAP */ + reg = ; + memory-region = <&audio_cma_mem>; + qcom,ion-heap-type = "DMA"; + }; }; }; diff --git a/qcom/shima-pcie.dtsi b/qcom/shima-pcie.dtsi index fb61f3ce64f8..4a05eff1809e 100644 --- a/qcom/shima-pcie.dtsi +++ b/qcom/shima-pcie.dtsi @@ -62,6 +62,7 @@ interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, @@ -73,7 +74,7 @@ <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, <&pcie_0_pipe_clk>; - clock-names = "pcie_0_pipe_clk", + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", diff --git a/qcom/shima-pinctrl.dtsi b/qcom/shima-pinctrl.dtsi index 54245d65a6d6..68fb424daa34 100644 --- a/qcom/shima-pinctrl.dtsi +++ b/qcom/shima-pinctrl.dtsi @@ -151,6 +151,66 @@ }; }; + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* GPIO 87: NFC Read Interrupt */ + pins = "gpio87"; + function = "gpio"; + }; + + config { + pins = "gpio87"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 87: NFC Read Interrupt */ + pins = "gpio87"; + function = "gpio"; + }; + + config { + pins = "gpio87"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + + nfc_enable_active: nfc_enable_active { + mux { + /* 62: Enable,86: Firmware,63: CLOCK */ + pins = "gpio62", "gpio86", "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio62", "gpio86", "gpio63"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + mux { + /* 62: Enable,86: Firmware,63: CLOCK */ + pins = "gpio62", "gpio86", "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio62", "gpio86", "gpio63"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + qupv3_se9_spi_pins: qupv3_se9_spi_pins { qupv3_se9_spi_active: qupv3_se9_spi_active { mux { diff --git a/qcom/shima-pmic-overlay.dtsi b/qcom/shima-pmic-overlay.dtsi index f09283d5d130..6ac9ba92edd4 100644 --- a/qcom/shima-pmic-overlay.dtsi +++ b/qcom/shima-pmic-overlay.dtsi @@ -270,7 +270,7 @@ #size-cells = <0>; status = "ok"; - pm8008i@8 { + pm8008i_chip: pm8008i@8 { compatible = "qcom,i2c-pmic"; reg = <0x8>; #address-cells = <1>; @@ -294,7 +294,7 @@ }; }; - pm8008i@9 { + pm8008i_ldo: pm8008i@9 { compatible = "qcom,i2c-pmic"; reg = <0x9>; #address-cells = <1>; @@ -315,7 +315,7 @@ L1I: pm8008i_l1: regulator@4000 { reg = <0x4000>; regulator-name = "pm8008i_l1"; - regulator-min-microvolt = <1000000>; + regulator-min-microvolt = <224000>; regulator-max-microvolt = <1200000>; qcom,min-dropout-voltage = <225000>; qcom,hpm-min-load = <30000>; @@ -324,7 +324,7 @@ L2I: pm8008i_l2: regulator@4100 { reg = <0x4100>; regulator-name = "pm8008i_l2"; - regulator-min-microvolt = <950000>; + regulator-min-microvolt = <264000>; regulator-max-microvolt = <1150000>; qcom,min-dropout-voltage = <184000>; qcom,hpm-min-load = <30000>; @@ -349,7 +349,7 @@ L5I: pm8008i_l5: regulator@4400 { reg = <0x4400>; regulator-name = "pm8008i_l5"; - regulator-min-microvolt = <1700000>; + regulator-min-microvolt = <1544000>; regulator-max-microvolt = <1900000>; qcom,min-dropout-voltage = <152000>; }; @@ -372,7 +372,7 @@ }; }; - pm8008j@c { + pm8008j_chip: pm8008j@c { compatible = "qcom,i2c-pmic"; reg = <0xc>; #address-cells = <1>; @@ -396,7 +396,7 @@ }; }; - pm8008j@d { + pm8008j_ldo: pm8008j@d { compatible = "qcom,i2c-pmic"; reg = <0xd>; #address-cells = <1>; @@ -417,7 +417,7 @@ L1J: pm8008j_l1: regulator@4000 { reg = <0x4000>; regulator-name = "pm8008j_l1"; - regulator-min-microvolt = <950000>; + regulator-min-microvolt = <288000>; regulator-max-microvolt = <1150000>; qcom,min-dropout-voltage = <160000>; qcom,hpm-min-load = <30000>; @@ -426,7 +426,7 @@ L2J: pm8008j_l2: regulator@4100 { reg = <0x4100>; regulator-name = "pm8008j_l2"; - regulator-min-microvolt = <950000>; + regulator-min-microvolt = <448000>; regulator-max-microvolt = <1150000>; qcom,min-dropout-voltage = <0>; qcom,hpm-min-load = <30000>; @@ -435,7 +435,7 @@ L3J: pm8008j_l3: regulator@4200 { reg = <0x4200>; regulator-name = "pm8008j_l3"; - regulator-min-microvolt = <1650000>; + regulator-min-microvolt = <1592000>; regulator-max-microvolt = <1950000>; qcom,min-dropout-voltage = <56000>; }; @@ -501,3 +501,11 @@ io-channels = <&pmk8350_vadc PMR735B_ADC7_DIE_TEMP>; io-channel-names = "thermal"; }; + +&soc { + reboot_reason { + compatible = "qcom,reboot-reason"; + nvmem-cells = <&restart_reason>; + nvmem-cell-names = "restart_reason"; + }; +}; diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index a185ce337341..35beafd3de2e 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -1,6 +1,9 @@ #include #include #include "shima-pmic-overlay.dtsi" +#include "shima-thermal-overlay.dtsi" +#include "shima-audio-overlay.dtsi" +#include "display/shima-sde-display-qrd.dtsi" &soc { gpio_keys { @@ -22,6 +25,27 @@ }; }; +&qupv3_se9_i2c { + status = "ok"; + qcom,clk-freq-out = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 87 0x00>; + qcom,sn-ven = <&tlmm 62 0x00>; + qcom,sn-firm = <&tlmm 86 0x00>; + qcom,sn-clkreq = <&tlmm 63 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <87 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + &sdhc_1 { status = "ok"; @@ -166,3 +190,104 @@ 5000000 4500000 4000000 3500000 3000000 2500000 2000000 1500000 1000000 500000>; }; + +&qupv3_se10_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + qcom,i2c-touch-active = "focaltech,fts_ts"; + + focaltech@38 { + compatible = "focaltech,fts_ts"; + reg = <0x38>; + interrupt-parent = <&tlmm>; + interrupts = <23 0x2008>; + focaltech,reset-gpio = <&tlmm 22 0x00>; + focaltech,irq-gpio = <&tlmm 23 0x2008>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 2340>; + + vdd-supply = <&L3C>; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend","pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + + panel = <&dsi_r66451_amoled_cmd + &dsi_r66451_amoled_video>; + }; +}; + +&shima_snd { + qcom,model = "lahaina-shimaqrd-snd-card"; + + qcom,audio-routing = + "TX DMIC0", "Digital Mic0", + "Digital Mic0", "MIC BIAS1", + "TX DMIC1", "Digital Mic1", + "Digital Mic1", "MIC BIAS1", + "TX DMIC2", "Digital Mic2", + "Digital Mic2", "MIC BIAS3", + "TX DMIC3", "Digital Mic3", + "Digital Mic3", "MIC BIAS3", + "TX DMIC4", "Digital Mic4", + "Digital Mic4", "MIC BIAS4", + "TX DMIC5", "Digital Mic5", + "Digital Mic5", "MIC BIAS4", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "IN3_AUX", "AUX_OUT", + "HAP_IN", "PCM_OUT", + "WSA SRC0_INP", "SRC0", + "WSA_TX DEC0_INP", "TX DEC0 MUX", + "WSA_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "TX SWR_INPUT", "WCD_TX_OUTPUT", + "VA SWR_INPUT", "VA_SWR_CLK", + "VA SWR_INPUT", "WCD_TX_OUTPUT", + "VA_AIF1 CAP", "VA_SWR_CLK", + "VA_AIF2 CAP", "VA_SWR_CLK", + "VA_AIF3 CAP", "VA_SWR_CLK", + "VA DMIC0", "Digital Mic0", + "VA DMIC1", "Digital Mic1", + "VA DMIC2", "Digital Mic2", + "VA DMIC3", "Digital Mic3", + "VA DMIC4", "Digital Mic4", + "VA DMIC5", "Digital Mic5"; + + qcom,swr-dmic-max-devs = <0>; + + qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; + qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; + qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>; + + qcom,msm-mbhc-usbc-audio-supported = <1>; + qcom,msm-mbhc-hphl-swh = <0>; + qcom,msm-mbhc-gnd-swh = <0>; + + asoc-codec = <&stub_codec>, <&bolero>, + <&wcd938x_codec>, <&swr_haptics>, + <&wsa883x_0221>, <&wsa883x_0222>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec", + "wcd938x_codec", "swr-haptics", + "wsa-codec1", "wsa-codec2"; + qcom,wsa-max-devs = <1>; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>, + <&bolero>; +}; + +&dai_mi2s2 { + qcom,msm-mi2s-tx-lines = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active + &tert_mi2s_sd0_active>; + pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep + &tert_mi2s_sd0_sleep>; +}; diff --git a/qcom/shima-qupv3.dtsi b/qcom/shima-qupv3.dtsi index d1d54be460b5..3c5999d267ac 100644 --- a/qcom/shima-qupv3.dtsi +++ b/qcom/shima-qupv3.dtsi @@ -60,6 +60,23 @@ status = "ok"; }; + /* Debug UART Instance */ + qupv3_se13_2uart: qcom,qup_uart@994000 { + compatible = "qcom,msm-geni-console"; + reg = <0x994000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_2uart_active>; + pinctrl-1 = <&qupv3_se13_2uart_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "ok"; + }; + qupv3_se8_i2c: i2c@980000 { compatible = "qcom,i2c-geni"; reg = <0x980000 0x4000>; @@ -270,23 +287,6 @@ status = "disabled"; }; - /* Debug UART Instance */ - qupv3_se13_2uart: qcom,qup_uart@994000 { - compatible = "qcom,msm-geni-console"; - reg = <0x994000 0x4000>; - reg-names = "se_phys"; - interrupts = ; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>, - <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se13_2uart_active>; - pinctrl-1 = <&qupv3_se13_2uart_sleep>; - qcom,wrapper-core = <&qupv3_0>; - status = "ok"; - }; - qupv3_se14_i2c: i2c@998000 { compatible = "qcom,i2c-geni"; reg = <0x998000 0x4000>; diff --git a/qcom/shima-regulators.dtsi b/qcom/shima-regulators.dtsi index ddb480f0f7b8..deb4771646b5 100644 --- a/qcom/shima-regulators.dtsi +++ b/qcom/shima-regulators.dtsi @@ -150,9 +150,9 @@ pm8350_s9: regulator-pm8350-s9 { regulator-name = "pm8350_s9"; qcom,set = ; - regulator-min-microvolt = <950000>; + regulator-min-microvolt = <450000>; regulator-max-microvolt = <1500000>; - qcom,init-voltage = <950000>; + qcom,init-voltage = <952000>; }; }; @@ -165,7 +165,7 @@ qcom,set = ; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <2040000>; - qcom,init-voltage = <1200000>; + qcom,init-voltage = <1800000>; }; }; @@ -178,7 +178,7 @@ qcom,set = ; regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2040000>; - qcom,init-voltage = <1700000>; + qcom,init-voltage = <1880000>; }; }; @@ -191,7 +191,7 @@ qcom,set = ; regulator-min-microvolt = <382000>; regulator-max-microvolt = <1654000>; - qcom,init-voltage = <382000>; + qcom,init-voltage = <1256000>; }; }; @@ -209,7 +209,7 @@ qcom,set = ; regulator-min-microvolt = <825000>; regulator-max-microvolt = <925000>; - qcom,init-voltage = <825000>; + qcom,init-voltage = <912000>; qcom,init-mode = ; }; }; @@ -228,7 +228,7 @@ qcom,set = ; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; - qcom,init-voltage = <2700000>; + qcom,init-voltage = <3072000>; qcom,init-mode = ; }; }; @@ -247,7 +247,7 @@ qcom,set = ; regulator-min-microvolt = <470000>; regulator-max-microvolt = <910000>; - qcom,init-voltage = <470000>; + qcom,init-voltage = <504000>; qcom,init-mode = ; }; }; @@ -299,7 +299,7 @@ qcom,set = ; regulator-min-microvolt = <1140000>; regulator-max-microvolt = <1260000>; - qcom,init-voltage = <1140000>; + qcom,init-voltage = <1200000>; qcom,init-mode = ; }; }; @@ -318,7 +318,7 @@ qcom,set = ; regulator-min-microvolt = <2400000>; regulator-max-microvolt = <3544000>; - qcom,init-voltage = <2400000>; + qcom,init-voltage = <2952000>; qcom,init-mode = ; }; }; @@ -337,7 +337,7 @@ qcom,set = ; regulator-min-microvolt = <870000>; regulator-max-microvolt = <970000>; - qcom,init-voltage = <870000>; + qcom,init-voltage = <904000>; qcom,init-mode = ; }; }; @@ -357,7 +357,7 @@ qcom,set = ; regulator-min-microvolt = <1080000>; regulator-max-microvolt = <1304000>; - qcom,init-voltage = <1080000>; + qcom,init-voltage = <1200000>; qcom,init-mode = ; }; }; @@ -412,7 +412,7 @@ qcom,set = ; regulator-min-microvolt = <3008000>; regulator-max-microvolt = <3960000>; - qcom,init-voltage = <3008000>; + qcom,init-voltage = <3296000>; }; }; @@ -430,9 +430,28 @@ qcom,set = ; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <1980000>; - qcom,init-voltage = <1620000>; + qcom,init-voltage = <1800000>; qcom,init-mode = ; }; + + L1C_AO: pm8350c_l1_ao: regulator-pm8350c-l1-ao { + regulator-name = "pm8350c_l1_ao"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + + L1C_SO: pm8350c_l1_so: regulator-pm8350c-l1-so { + regulator-name = "pm8350c_l1_so"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + qcom,init-enable = <0>; + }; }; rpmh-regulator-ldoc2 { @@ -525,7 +544,7 @@ qcom,set = ; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <3544000>; - qcom,init-voltage = <1650000>; + qcom,init-voltage = <2960000>; qcom,init-mode = ; }; }; @@ -582,7 +601,7 @@ qcom,set = ; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; - qcom,init-voltage = <2700000>; + qcom,init-voltage = <2960000>; qcom,init-mode = ; }; }; @@ -601,9 +620,30 @@ qcom,set = ; regulator-min-microvolt = <720000>; regulator-max-microvolt = <1050000>; - qcom,init-voltage = <720000>; + qcom,init-voltage = <880000>; qcom,init-mode = ; }; + + L10C_AO: + pm8350c_l10_ao: regulator-pm8350c-l10-ao { + regulator-name = "pm8350c_l10_ao"; + qcom,set = ; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + + L10C_SO: + pm8350c_l10_so: regulator-pm8350c-l10-so { + regulator-name = "pm8350c_l10_so"; + qcom,set = ; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + qcom,init-enable = <0>; + }; }; rpmh-regulator-ldoc11 { diff --git a/qcom/shima-thermal-overlay.dtsi b/qcom/shima-thermal-overlay.dtsi new file mode 100644 index 000000000000..aa352a783037 --- /dev/null +++ b/qcom/shima-thermal-overlay.dtsi @@ -0,0 +1,254 @@ +#include + +&mdss_mdp { + #cooling-cells = <2>; +}; + +&battery_charger { + #cooling-cells = <2>; +}; + +&thermal_zones { + socd { + cooling-maps { + socd_cpu4 { + trip = <&socd_trip>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + socd_cpu5 { + trip = <&socd_trip>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + socd_cpu6 { + trip = <&socd_trip>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + socd_cpu7 { + trip = <&socd_trip>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + pm8350b-bcl-lvl0 { + cooling-maps { + vbat_cpu4 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + vbat_cpu5 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + vbat_gpu0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pm8350b-bcl-lvl1 { + cooling-maps { + vbat_cpu6 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + vbat_cpu7 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu7_isolate 1 1>; + }; + + vbat_gpu1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + }; + }; + + pm8350b-bcl-lvl2 { + cooling-maps { + vbat_gpu2 { + trip = <&b_bcl_lvl2>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm8350c-bcl-lvl0 { + disable-thermal-zone; + cooling-maps { + vph_cpu4 { + trip = <&c_bcl_lvl0>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + vph_cpu5 { + trip = <&c_bcl_lvl0>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + vph_gpu0 { + trip = <&c_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pm8350c-bcl-lvl1 { + disable-thermal-zone; + cooling-maps { + vph_cpu6 { + trip = <&c_bcl_lvl1>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + vph_cpu7 { + trip = <&c_bcl_lvl1>; + cooling-device = <&cpu7_isolate 1 1>; + }; + + vph_gpu1 { + trip = <&c_bcl_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + }; + }; + + pm8350c-bcl-lvl2 { + disable-thermal-zone; + cooling-maps { + vph_gpu2 { + trip = <&c_bcl_lvl2>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm8350b_tz { + cooling-maps { + battery_cdev { + trip = <&pm8350b_trip0>; + cooling-device = <&battery_charger + THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm8350_tz { + cooling-maps { + pm8350_gpu { + trip = <&pm8350_trip0>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pm8350_cpu0_freq { + trip = <&pm8350_trip0>; + cooling-device = <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pm8350_cpu1 { + trip = <&pm8350_trip0>; + cooling-device = <&cpu1_isolate 1 1>; + }; + + pm8350_cpu2 { + trip = <&pm8350_trip0>; + cooling-device = <&cpu2_isolate 1 1>; + }; + + pm8350_cpu3 { + trip = <&pm8350_trip0>; + cooling-device = <&cpu3_isolate 1 1>; + }; + + pm8350_cpu4 { + trip = <&pm8350_trip0>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + pm8350_cpu5 { + trip = <&pm8350_trip0>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + pm8350_cpu6 { + trip = <&pm8350_trip0>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + pm8350_cpu7 { + trip = <&pm8350_trip0>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + pm8350c_tz { + cooling-maps { + pm8350c_mdm { + trip = <&pm8350c_trip0>; + cooling-device = <&modem_tj THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pm8350c_nsp { + trip = <&pm8350c_trip0>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pmr735b_tz { + cooling-maps { + pmr735b_pa { + trip = <&pmr735b_trip0>; + cooling-device = <&modem_pa_dsc + THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735b_pa_fr1 { + trip = <&pmr735b_trip0>; + cooling-device = <&modem_pa_fr1_dsc + THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735b_mmw0 { + trip = <&pmr735b_trip0>; + cooling-device = <&modem_mmw0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735b_mmw1 { + trip = <&pmr735b_trip0>; + cooling-device = <&modem_mmw1 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735b_mmw2 { + trip = <&pmr735b_trip0>; + cooling-device = <&modem_mmw2 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735b_mmw3 { + trip = <&pmr735b_trip0>; + cooling-device = <&modem_mmw3 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; +}; diff --git a/qcom/shima-thermal.dtsi b/qcom/shima-thermal.dtsi index bb3fb6bcadbc..400c81e2b65a 100644 --- a/qcom/shima-thermal.dtsi +++ b/qcom/shima-thermal.dtsi @@ -60,6 +60,18 @@ #cooling-cells = <2>; }; }; + + qcom,cpu-voltage-cdev { + compatible = "qcom,cc-cooling-devices"; + apc1_cluster: qcom,apc1-cluster { + qcom,cpus = <&CPU4 &CPU7>; + #cooling-cells = <2>; + }; + }; +}; + +&msm_gpu { + #cooling-cells = <2>; }; &thermal_zones { @@ -643,99 +655,6 @@ }; }; - nspss-0-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 3>; - thermal-governor = "step_wise"; - trips { - nspss0_trip0: nspss0-trip0 { - temperature = <100000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - - cooling-maps { - cdsp-cdev { - trip = <&nspss0_trip0>; - cooling-device = <&cdsp_sw 3 3>; - }; - - modem-pa-cdev { - trip = <&nspss0_trip0>; - cooling-device = <&modem_pa 3 3>; - }; - - modem-tj-cdev { - trip = <&nspss0_trip0>; - cooling-device = <&modem_tj 3 3>; - }; - }; - }; - - nspss-1-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 4>; - thermal-governor = "step_wise"; - trips { - nspss1_trip0: nspss1-trip0 { - temperature = <100000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - - cooling-maps { - cdsp-cdev { - trip = <&nspss1_trip0>; - cooling-device = <&cdsp_sw 3 3>; - }; - - modem-pa-cdev { - trip = <&nspss1_trip0>; - cooling-device = <&modem_pa 3 3>; - }; - - modem-tj-cdev { - trip = <&nspss1_trip0>; - cooling-device = <&modem_tj 3 3>; - }; - }; - }; - - nspss-2-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 5>; - thermal-governor = "step_wise"; - trips { - nspss2_trip0: nspss2-trip0 { - temperature = <100000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - - cooling-maps { - cdsp-cdev { - trip = <&nspss2_trip0>; - cooling-device = <&cdsp_sw 3 3>; - }; - - modem-pa-cdev { - trip = <&nspss2_trip0>; - cooling-device = <&modem_pa 3 3>; - }; - - modem-tj-cdev { - trip = <&nspss2_trip0>; - cooling-device = <&modem_tj 3 3>; - }; - }; - }; - cpu-0-0-step { polling-delay-passive = <0>; polling-delay = <0>; @@ -1033,10 +952,168 @@ trips { gpuss_config: active-config0 { temperature = <95000>; - hysteresis = <20000>; + hysteresis = <0>; type = "passive"; }; }; + + cooling-maps { + gpu_cdev { + trip = <&gpuss_config>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + nspss-0-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 3>; + trips { + nspss0_trip0: nspss0-trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + nspss0_trip1: nspss0-trip1 { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cdsp-cdev0 { + trip = <&nspss0_trip0>; + cooling-device = <&cdsp_sw THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + + cdsp-cdev1 { + trip = <&nspss0_trip1>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + gpu_cdev { + trip = <&nspss0_trip1>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + + modem-pa-cdev { + trip = <&nspss0_trip1>; + cooling-device = <&modem_pa 3 3>; + }; + + modem-tj-cdev { + trip = <&nspss0_trip1>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + nspss-1-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 4>; + trips { + nspss1_trip0: nspss1-trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + nspss1_trip1: nspss1-trip1 { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cdsp-cdev0 { + trip = <&nspss1_trip0>; + cooling-device = <&cdsp_sw THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + + cdsp-cdev1 { + trip = <&nspss1_trip1>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + gpu_cdev { + trip = <&nspss1_trip1>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + + modem-pa-cdev { + trip = <&nspss1_trip1>; + cooling-device = <&modem_pa 3 3>; + }; + + modem-tj-cdev { + trip = <&nspss1_trip1>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + nspss-2-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 5>; + trips { + nspss2_trip0: nspss2-trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + nspss2_trip1: nspss2-trip1 { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cdsp-cdev0 { + trip = <&nspss2_trip0>; + cooling-device = <&cdsp_sw THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + + cdsp-cdev1 { + trip = <&nspss2_trip1>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + gpu_cdev { + trip = <&nspss2_trip1>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + + modem-pa-cdev { + trip = <&nspss2_trip1>; + cooling-device = <&modem_pa 3 3>; + }; + + modem-tj-cdev { + trip = <&nspss2_trip1>; + cooling-device = <&modem_tj 3 3>; + }; + }; }; }; diff --git a/qcom/shima-vm-atp.dts b/qcom/shima-vm-atp.dts new file mode 100644 index 000000000000..3cf446ded4ec --- /dev/null +++ b/qcom/shima-vm-atp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "shima-vm.dtsi" +#include "shima-vm-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Shima VM ATP"; + compatible = "qcom,shima-atp", "qcom,shima", "qcom,atp"; + qcom,board-id = <0x10021 0>; +}; diff --git a/qcom/shima-vm-atp.dtsi b/qcom/shima-vm-atp.dtsi new file mode 100644 index 000000000000..17f1e228977f --- /dev/null +++ b/qcom/shima-vm-atp.dtsi @@ -0,0 +1,2 @@ +&soc { +}; diff --git a/qcom/shima-vm-idp.dts b/qcom/shima-vm-idp.dts new file mode 100644 index 000000000000..1662e107f70e --- /dev/null +++ b/qcom/shima-vm-idp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "shima-vm.dtsi" +#include "shima-vm-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Shima VM IDP"; + compatible = "qcom,shima-idp", "qcom,shima", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/shima-vm-idp.dtsi b/qcom/shima-vm-idp.dtsi new file mode 100644 index 000000000000..17f1e228977f --- /dev/null +++ b/qcom/shima-vm-idp.dtsi @@ -0,0 +1,2 @@ +&soc { +}; diff --git a/qcom/shima-vm-ion.dtsi b/qcom/shima-vm-ion.dtsi new file mode 100644 index 000000000000..010dec0a5607 --- /dev/null +++ b/qcom/shima-vm-ion.dtsi @@ -0,0 +1,15 @@ +#include + +/ { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + tui_heap: qcom,ion-heap-tui { /* TRUSTED UI CARVEOUT HEAP */ + reg = ; + qcom,dynamic-heap; + qcom,ion-heap-type = "MSM_CARVEOUT"; + }; + }; +}; diff --git a/qcom/shima-vm-qrd.dts b/qcom/shima-vm-qrd.dts new file mode 100644 index 000000000000..5ab499f2c1ed --- /dev/null +++ b/qcom/shima-vm-qrd.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "shima-vm.dtsi" +#include "shima-vm-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Shima VM QRD"; + compatible = "qcom,shima-qrd", "qcom,shima", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/shima-vm-qrd.dtsi b/qcom/shima-vm-qrd.dtsi new file mode 100644 index 000000000000..17f1e228977f --- /dev/null +++ b/qcom/shima-vm-qrd.dtsi @@ -0,0 +1,2 @@ +&soc { +}; diff --git a/qcom/shima-vm-rumi.dts b/qcom/shima-vm-rumi.dts new file mode 100644 index 000000000000..07baa3b0a801 --- /dev/null +++ b/qcom/shima-vm-rumi.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/memreserve/ 0x90000000 0x00000100; + +#include "shima-vm.dtsi" +#include "shima-vm-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Shima SVM RUMI"; + compatible = "qcom,shima-rumi", "qcom,shima", "qcom,rumi"; + qcom,board-id = <0x1000f 0>; +}; diff --git a/qcom/shima-vm-rumi.dtsi b/qcom/shima-vm-rumi.dtsi new file mode 100644 index 000000000000..48c92e0c09e8 --- /dev/null +++ b/qcom/shima-vm-rumi.dtsi @@ -0,0 +1,5 @@ +&soc { + timer { + clock-frequency = <5000000>; + }; +}; diff --git a/qcom/shima-vm.dtsi b/qcom/shima-vm.dtsi new file mode 100644 index 000000000000..360c435790da --- /dev/null +++ b/qcom/shima-vm.dtsi @@ -0,0 +1,228 @@ +#include + +/ { + #address-cells = <0x2>; + #size-cells = <0x2>; + qcom,msm-id = <450 0x10000>; + interrupt-parent = <&vgic>; + + qcom-mem-buf { + compatible = "qcom,mem-buf"; + qcom,mem-buf-capabilities = "consumer"; + }; + + chosen { + bootargs = "nokaslr no_console_suspend root=/dev/ram rw init=/init console=hvc0 loglevel=8"; + linux,initrd-start = <0x2a900000>; + linux,initrd-end = <0x2b100000>; /* 8 MB */ + kaslr-seed = <0xfeedbeef 0xc0def00d>; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + CPU0: cpu@0 { + compatible = "arm,armv8"; + reg = <0x0 0x0>; + device_type = "cpu"; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWR_DWN>; + }; + + CPU1: cpu@100 { + compatible = "arm,armv8"; + reg = <0x0 0x100>; + device_type = "cpu"; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWR_DWN>; + }; + }; + + idle-states { + CPU_PWR_DWN: c4 { /* Using Gold C4 latencies */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <702>; + exit-latency-us = <1061>; + min-residency-us = <4488>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + }; + + neuron-client-block { + compatible = "qcom,neuron-service"; + #address-cells = <1>; + #size-cells = <0>; + + protocol { + compatible = "qcom,neuron-protocol-block"; + processes = "client"; + }; + + application { + compatible = "qcom,neuron-block-client"; + }; + + channel@0 { + reg = <0>; + compatible = "qcom,neuron-channel-haven-shmem"; + class = "message-queue"; + direction = "send"; + max-size = <0 65536>; + haven-label = <1>; + }; + + channel@1 { + reg = <1>; + compatible = "qcom,neuron-channel-haven-shmem"; + class = "message-queue"; + direction = "receive"; + max-size = <0 65536>; + haven-label = <2>; + }; + }; + + qrtr-haven { + compatible = "qcom,qrtr-haven"; + haven-label = <3>; + }; + + qcom,vm-config { + compatible = "qcom,vm-1.0"; + vm-type = "aarch64-guest"; + boot-config = "fdt,unified"; + os-type = "linux"; + kernel-entry-segment = "kernel"; + kernel-entry-offset = <0x0 0x0>; + vendor = "Qualcomm Technologies, Inc."; + image-name = "qcom,trustedvm"; + qcom,pasid = <0x0 0x1c>; + + iomemory-ranges = <0x0 0x92c000 0x0 0x92c000 0x0 0x4000 0x0 + 0x0 0xc400000 0x0 0xc400000 0x0 0x30000 0x1 + 0x0 0xc440000 0x0 0xc440000 0x0 0x10000 0x1 + 0x0 0xc600000 0x0 0xc600000 0x0 0x2000000 0x1 + 0x0 0xe600000 0x0 0xe600000 0x0 0x100000 0x1 + 0x0 0xe700000 0x0 0xe700000 0x0 0xa0000 0x1 + 0x0 0xae8f000 0x0 0xae8f000 0x0 0x1000 0x0>; + + gic-irq-ranges = <283 283>; /* PVM->SVM IRQ transfer */ + + memory { + #address-cells = <0x2>; + #size-cells = <0x0>; + base-address = <0x0 0xD0800000>; + size-min = <0x0 0x76f7000>; /* 118 MB */ + }; + + segments { + ramdisk = <2>; /* 8MB */ + }; + + vcpus { + config = "/cpus"; + affinity = "static"; + affinity-map = <0x4 0x5>; + sched-priority = <0>; /* relative to PVM */ + sched-timeslice = <2000>; /* in ms */ + }; + + interrupts { + config = &vgic; + }; + + vdevices { + generate = "/hypervisor"; + rm-rpc { + vdevice-type = "rm-rpc"; + generate = "/hypervisor/qcom,resource-mgr"; + console-dev; + message-size = <0x000000f0>; + queue-depth = <0x00000008>; + qcom,label = <0x1>; + }; + + mem-buf-message-queue-pair { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/membuf-msgq-pair"; + message-size = <0x000000f0>; + queue-depth = <0x00000008>; + peer-default; + qcom,label = <0x0000001>; + }; + + neuron-ch1-shm { + vdevice-type = "shm-doorbell"; + generate = "/hypervisor/neuron-ch1-shm"; + push-compatible = "qcom,neuron-channel-haven-shmem-gen"; + peer-default; + memory { + qcom,label = <0x1>; + allocate-base; + }; + }; + + neuron-ch2-shm { + vdevice-type = "shm-doorbell"; + generate = "/hypervisor/neuron-ch2-shm"; + push-compatible = "qcom,neuron-channel-haven-shmem-gen"; + peer-default; + memory { + qcom,label = <0x2>; + allocate-base; + }; + }; + + qrtr-shm { + vdevice-type = "shm-doorbell"; + generate = "/hypervisor/qrtr-shm"; + push-compatible = "qcom,qrtr-haven-gen"; + peer-default; + memory { + qcom,label = <0x3>; + allocate-base; + }; + }; + }; + }; + + firmware: firmware { + scm { + compatible = "qcom,scm"; + }; + }; + + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + vgic: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <0x3>; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17a60000 0x100000>; /* GICR * 8 */ + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + always-on; + interrupts = , + , + , + ; + }; +}; +#include "shima-vm-ion.dtsi" diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index ed3798d034b0..eb6782df00d1 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -40,6 +40,8 @@ swr0 = &swr0; swr1 = &swr1; swr2 = &swr2; + serial0 = &qupv3_se13_2uart; + hsuart0 = &qupv3_se15_4uart; }; cpus { @@ -258,6 +260,11 @@ reg = <0x0 0x80860000 0x0 0x20000>; }; + reserved_xbl_uefi: reserved_xbl_uefi@80880000 { + no-map; + reg = <0x0 0x80880000 0x0 0x14000>; + }; + smem_mem: smem@80900000 { no-map; reg = <0x0 0x80900000 0x0 0x200000>; @@ -336,9 +343,24 @@ reg = <0x0 0xc0000000 0x0 0x5100000>; }; - pil_trustedvm_mem: pil_trustedvm_region@d0000000 { + pil_trustedvm_mem: pil_trustedvm_region@d0800000 { no-map; - reg = <0x0 0xd0000000 0x0 0xa600000>; + reg = <0x0 0xd0800000 0x0 0x76f7000>; + }; + + qrtr_shbuf: qrtr-shmem { + no-map; + reg = <0x0 0xd7ef7000 0x0 0x9000>; + }; + + chan0_shbuf: neuron_block@0 { + no-map; + reg = <0x0 0xd7f00000 0x0 0x80000>; + }; + + chan1_shbuf: neuron_block@1 { + no-map; + reg = <0x0 0xd7f80000 0x0 0x80000>; }; user_contig_mem: user_contig_region { @@ -406,10 +428,18 @@ size = <0 0x2c00000>; }; + audio_cma_mem: audio_cma_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1C00000>; + }; + }; chosen { - bootargs = "earlycon=msm_geni_serial,0x994000"; + bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000"; }; soc: soc { }; @@ -417,6 +447,7 @@ firmware: firmware { scm { compatible = "qcom,scm"; + qcom,dload-mode = <&tcsr 0x13000>; }; android { @@ -506,12 +537,7 @@ compatible = "qcom,msm-watchdog"; reg = <0x17c10000 0x1000>; reg-names = "wdt-base"; - interrupts = , - ; - qcom,bark-time = <11000>; - qcom,pet-time = <9360>; - qcom,ipi-ping; - qcom,wakeup-enable; + interrupts = ; }; arch_timer: timer { @@ -624,6 +650,11 @@ compatible = "qcom,secure-buffer"; }; + qcom-mem-buf { + compatible = "qcom,mem-buf"; + qcom,mem-buf-capabilities = "supplier"; + }; + qcom,memshare { compatible = "qcom,memshare"; @@ -688,6 +719,11 @@ reg = <0x94c 0xc8>; }; + pil@6dc { + compatible = "qcom,msm-imem-pil-disable-timeout"; + reg = <0x6dc 0x4>; + }; + diag_dload@c8 { compatible = "qcom,msm-imem-diag-dload"; reg = <0xc8 0xc8>; @@ -975,6 +1011,65 @@ #interrupt-cells = <3>; #mbox-cells = <2>; }; + qcom,trustedvm@d0800000 { + compatible = "qcom,pil-tz-generic"; + status = "ok"; + qcom,pas-id = <28>; + qcom,firmware-name = "trustedvm"; + memory-region = <&pil_trustedvm_mem>; + }; + + qcom,guestvm_loader { + compatible = "qcom,guestvm-loader"; + image_to_be_loaded = "trustedvm"; + }; + + + qcom,svm_neuron_block { + compatible = "qcom,neuron-service"; + #address-cells = <1>; + #size-cells = <0>; + protocol { + compatible = "qcom,neuron-protocol-block"; + processes = "server"; + }; + + application { + compatible = "qcom,neuron-block-server"; + }; + + channel@0 { + compatible = "qcom,neuron-channel-haven-shmem"; + reg = <0>; + class = "message-queue"; + direction = "receive"; + max-size = <0 65536>; + shared-buffer = <&chan0_shbuf>; + qcom,primary; + haven-label = <1>; + peer-name = <2>; + }; + + channel@1 { + compatible = "qcom,neuron-channel-haven-shmem"; + reg = <1>; + class = "message-queue"; + direction = "send"; + max-size = <0 65536>; + shared-buffer = <&chan1_shbuf>; + qcom,primary; + haven-label = <2>; + peer-name = <2>; + }; + }; + + qrtr-haven { + compatible = "qcom,qrtr-haven"; + qcom,master; + haven-label = <3>; + peer-name = <2>; + shared-buffer = <&qrtr_shbuf>; + }; tcsr_mutex_block: syscon@1f40000 { compatible = "syscon"; @@ -987,6 +1082,11 @@ #hwlock-cells = <1>; }; + tcsr: syscon@1fc0000 { + compatible = "syscon"; + reg = <0x1fc0000 0x30000>; + }; + smem: qcom,smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; @@ -1175,7 +1275,8 @@ qcom,adsp_glink_ssr { qcom,glink-channels = "glink_ssr"; - qcom,notify-edges = <&glink_modem>; + qcom,notify-edges = <&glink_modem>, + <&glink_cdsp>; }; qcom,pmic_glink_rpmsg { @@ -1209,6 +1310,11 @@ 0x2000 3 0x4400 2>; }; + + qcom,cdsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>; + }; }; }; @@ -1318,6 +1424,7 @@ reg = <0x0 0x280000>; reg-names = "rmtfs"; qcom,client-id = <0x00000001>; + qcom,vm-nav-path; }; qcom_hwkm: hwkm@10c0000 { @@ -1461,8 +1568,9 @@ qcom,iommu-dma = "bypass"; dma-coherent; - rpm-level = <3>; - spm-level = <5>; + qcom,disable-lpm; + rpm-level = <0>; + spm-level = <0>; status = "disabled"; @@ -1491,8 +1599,12 @@ ; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; - clock-names = "core", "iface"; + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "core", "iface", "ice_core"; + + qcom,ice-clk-rates = <300000000 100000000>; interconnects = <&aggre1_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDC_1>; @@ -1521,7 +1633,7 @@ 100000000 200000000 400000000 4294967295>; /* DLL HSR settings. Refer go/hsr - DLL settings */ - qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x00010800 0x80040868>; + qcom,dll-hsr-list = <0x000f642c 0x0 0x1 0x2C010800 0x80040868>; mmc-ddr-1_8v; mmc-hs200-1_8v; @@ -1578,7 +1690,7 @@ 100000000 200000000 4294967295>; /* DLL HSR settings. Refer go/hsr - DLL settings */ - qcom,dll-hsr-list = <0x0007642c 0x0 0x0 0x00010800 0x80040868>; + qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; status = "disabled"; }; @@ -1787,10 +1899,8 @@ 0x18040060 0x18050060 0x18060060 0x18070060>; }; - restart: restart@c264000 { - compatible = "qcom,pshold"; - reg = <0xc264000 0x4>, <0x1fd3000 0x4>; - reg-names = "pshold-base", "tcsr-boot-misc-detect"; + dload_mode { + compatible = "qcom,dload-mode"; }; cache-controller@9200000 { @@ -1895,12 +2005,11 @@ epss_l3_cpu: l3_cpu@18590000 { reg = <0x18590000 0x4000>; - compatible = "qcom,shima-epss-l3-cpu"; + compatible = "qcom,lahaina-epss-l3-cpu"; #interconnect-cells = <1>; clock-names = "xo", "alternate"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; - status = "disabled"; }; llcc_pmu: llcc-pmu@9095000 { @@ -2568,6 +2677,11 @@ mbox-names = "cdsp-pil"; }; + qcom,msm-cdsp-loader { + compatible = "qcom,cdsp-loader"; + qcom,proc-img-to-load = "cdsp"; + }; + qcom,msm-adsprpc-mem { compatible = "qcom,msm-adsprpc-mem-region"; memory-region = <&adsp_mem>; @@ -2617,6 +2731,8 @@ qcom,fastrpc-adsp-audio-pdr; qcom,fastrpc-adsp-sensors-pdr; qcom,rpc-latency-us = <235>; + qcom,fastrpc-gids = <2908>; + qcom,qos-cores = <0 1 2 3>; qcom,msm_fastrpc_compute_cb1 { compatible = "qcom,msm-fastrpc-compute-cb"; @@ -2844,22 +2960,22 @@ }; c400_scandump { - qcom,dump-size = <0x1a4c0>; + qcom,dump-size = <0x40000>; qcom,dump-id = <0x134>; }; c500_scandump { - qcom,dump-size = <0x1a4c0>; + qcom,dump-size = <0x40000>; qcom,dump-id = <0x135>; }; c600_scandump { - qcom,dump-size = <0x1a4c0>; + qcom,dump-size = <0x40000>; qcom,dump-id = <0x136>; }; c700_scandump { - qcom,dump-size = <0x1a4c0>; + qcom,dump-size = <0x40000>; qcom,dump-id = <0x137>; }; @@ -3294,7 +3410,7 @@ pinctrl-names = "default"; pinctrl-0 = <&bt_en_sleep>; qcom,bt-reset-gpio = <&tlmm 65 0>; /* BT_EN */ - qcom,bt-sw-ctrl-gpio = <&tlmm 66 0>; /* SW_CTRL */ + qcom,bt-sw-ctrl-gpio = <&tlmm 91 0>; /* SW_CTRL */ qcom,bt-vdd-io-supply = <&S10B>; qcom,bt-vdd-aon-supply = <&S2C>; @@ -3464,10 +3580,10 @@ #include "msm-arm-smmu-shima.dtsi" #include "shima-vidc.dtsi" #include "shima-cvp.dtsi" -#include "shima-thermal.dtsi" #include "shima-gpu.dtsi" #include "display/shima-sde.dtsi" #include "shima-audio.dtsi" +#include "shima-thermal.dtsi" &pcie0_rp { #address-cells = <5>; diff --git a/qcom/trustedvm.dts b/qcom/trustedvm.dts deleted file mode 100644 index e8db5262cc91..000000000000 --- a/qcom/trustedvm.dts +++ /dev/null @@ -1,7 +0,0 @@ -/dts-v1/; - -#include "trustedvm.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. Secondary Virtual Machine"; -};