From 55484e035730d2dcf53e90879768024950c62179 Mon Sep 17 00:00:00 2001
From: Manuel Gomez <gomez@quicinc.com>
Date: Mon, 20 Sep 2021 17:12:27 -0700
Subject: [PATCH] ARM: dts: msm: Pin config for AQR on MBB

Make a pin control for eth0 on AQR PHY for MBB platforms.
This pinctrl is necessary to configure the GPIO pin on
SDX65 for WoL interrupts.

Change-Id: I0c65b02bd7a85aa14fa20391a9007b0a6e40e655
---
 qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi
index a6e249a6eac5..004fbbf42322 100644
--- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi
+++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi
@@ -118,6 +118,9 @@
 				interrupts-extended = <&tlmm 103 IRQ_TYPE_EDGE_FALLING>;
 				interrupt-names = "wol_irq";
 
+				pinctrl-names = "default";
+				pinctrl-0 = <&aqr_intn_wol_sig>;
+
 				#address-cells = <1>;
 				#size-cells = <1>;
 			};