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qcacld-3.0: Relocate legacy DP INI items

Browse source 
Relocate below legacy  DP ini items as per
converged infrastructure.

1. maxMSDUsPerRxInd
2. gEnableTxSchedWrrVO
3. gEnableTxSchedWrrVI
4. gEnableTxSchedWrrBE
5. gEnableTxSchedWrrBK

Change-Id: Iebded11869c55c1797f0521af05585284f46f544
CRs-Fixed: 2351663
This commit is contained in:
jitiphil 2018-11-16 18:05:34 +05:30 • committed by nshrivas
commit 8e15ea6d1e
4 changed files with 106 additions and 126 deletions
Download patch file Download diff file Expand all files Collapse all files

78
core/dp/ol/inc/cfg_legacy_dp.h
View file

@ -43,12 +43,88 @@
false, \
"")
/*
* <ini>
* Max number of MSDUs per HTT RX IN ORDER INDICATION msg.
* Note that this has a direct impact on the size of source CE rings.
* It is possible to go below 8, but would require testing; so we are
* restricting the lower limit to 8 artificially
*
* It is recommended that this value is a POWER OF 2.
*
* Values lower than 8 are for experimental purposes only.
*/
#define CFG_DP_MAX_MSDUS_PER_RXIND \
CFG_INI_UINT("maxMSDUsPerRxInd", \
4, 32, 32, CFG_VALUE_OR_DEFAULT, \
"Max number of MSDUs per HTT RX INORDER IND msg")
/*
* <ini>
* gEnableTxSchedWrrVO - Set TX sched parameters for VO
* @Default:
*
* This key is mapping to VO defined in data path module through
* OL_TX_SCHED_WRR_ADV_CAT_CFG_SPEC. The user can tune the
* WRR TX sched parameters such as skip, credit, limit, credit, disc for VO.
* e.g., gEnableTxSchedWrrVO = 10, 9, 8, 1, 8
*/
#define CFG_DP_ENABLE_TX_SCHED_WRR_VO \
CFG_INI_STRING("gEnableTxSchedWrrVO", \
0, 50, "", "et TX sched parameters for VO")
/*
* <ini>
* gEnableTxSchedWrrVI - Set TX sched parameters for VI
* @Default:
*
* This key is mapping to VI defined in data path module through
* OL_TX_SCHED_WRR_ADV_CAT_CFG_SPEC. The user can tune the
* WRR TX sched parameters such as skip, credit, limit, credit, disc for VI.
* e.g., gEnableTxSchedWrrVI = 10, 9, 8, 1, 8
*/
#define CFG_DP_ENABLE_TX_SCHED_WRR_VI \
CFG_INI_STRING("gEnableTxSchedWrrVI", \
0, 50, "", "Set TX sched parameters for VI")
/*
* <ini>
* gEnableTxSchedWrrBE - Set TX sched parameters for BE
* @Default:
*
* This key is mapping to BE defined in data path module through
* OL_TX_SCHED_WRR_ADV_CAT_CFG_SPEC. The user can tune the
* WRR TX sched parameters such as skip, credit, limit, credit, disc for BE.
* e.g., gEnableTxSchedWrrBE = 10, 9, 8, 1, 8
*/
#define CFG_DP_ENABLE_TX_SCHED_WRR_BE \
CFG_INI_STRING("gEnableTxSchedWrrBE", \
0, 50, "", "Set TX sched parameters for BE")
/*
* <ini>
* gEnableTxSchedWrrBK - Set TX sched parameters for BK
* @Default:
*
* This key is mapping to BK defined in data path module through
* OL_TX_SCHED_WRR_ADV_CAT_CFG_SPEC. The user can tune the
* WRR TX sched parameters such as skip, credit, limit, credit, disc for BK.
* e.g., gEnableTxSchedWrrBK = 10, 9, 8, 1, 8
*/
#define CFG_DP_ENABLE_TX_SCHED_WRR_BK \
CFG_INI_STRING("gEnableTxSchedWrrBK", \
0, 50, "", "Set TX sched parameters for BK")
#define CFG_DP_CE_CLASSIFY_ENABLE \
CFG_INI_BOOL("gCEClassifyEnable", \
true, "enable CE classify")
#define CFG_LEGACY_DP_ALL \
CFG(CFG_DP_FLOW_STEERING_ENABLED) \
CFG(CFG_DP_CE_CLASSIFY_ENABLE)
CFG(CFG_DP_CE_CLASSIFY_ENABLE) \
CFG(CFG_DP_MAX_MSDUS_PER_RXIND) \
CFG(CFG_DP_ENABLE_TX_SCHED_WRR_VO) \
CFG(CFG_DP_ENABLE_TX_SCHED_WRR_VI) \
CFG(CFG_DP_ENABLE_TX_SCHED_WRR_BE) \
CFG(CFG_DP_ENABLE_TX_SCHED_WRR_BK)
#endif

78
core/hdd/inc/wlan_hdd_cfg.h
View file

@ -4212,22 +4212,6 @@ enum hdd_link_speed_rpt_type {
#define CFG_ENABLE_NON_DFS_CHAN_ON_RADAR_MAX (1)
#define CFG_ENABLE_NON_DFS_CHAN_ON_RADAR_DEFAULT (0)
/*
* <ini>
* Max number of MSDUs per HTT RX IN ORDER INDICATION msg.
* Note that this has a direct impact on the size of source CE rings.
* It is possible to go below 8, but would require testing; so we are
* restricting the lower limit to 8 artificially
*
* It is recommended that this value is a POWER OF 2.
*
* Values lower than 8 are for experimental purposes only.
*/
#define CFG_MAX_MSDUS_PER_RXIND_NAME "maxMSDUsPerRxInd"
#define CFG_MAX_MSDUS_PER_RXIND_MIN (4)
#define CFG_MAX_MSDUS_PER_RXIND_MAX (32)
#define CFG_MAX_MSDUS_PER_RXIND_DEFAULT (32)
/*
* set the self gen power value from
* 0 to 0xffff
@ -4456,58 +4440,6 @@ enum hdd_link_speed_rpt_type {
#define CFG_SET_TSF_PTP_OPT_DEFAULT (0xf)
#endif
/*
* <ini>
* gEnableTxSchedWrrVO - Set TX sched parameters for VO
* @Default:
*
* This key is mapping to VO defined in data path module through
* OL_TX_SCHED_WRR_ADV_CAT_CFG_SPEC. The user can tune the
* WRR TX sched parameters such as skip, credit, limit, credit, disc for VO.
* e.g., gEnableTxSchedWrrVO = 10, 9, 8, 1, 8
*/
#define CFG_ENABLE_TX_SCHED_WRR_VO_NAME "gEnableTxSchedWrrVO"
#define CFG_ENABLE_TX_SCHED_WRR_VO_DEFAULT ""
/*
* <ini>
* gEnableTxSchedWrrVI - Set TX sched parameters for VI
* @Default:
*
* This key is mapping to VI defined in data path module through
* OL_TX_SCHED_WRR_ADV_CAT_CFG_SPEC. The user can tune the
* WRR TX sched parameters such as skip, credit, limit, credit, disc for VI.
* e.g., gEnableTxSchedWrrVI = 10, 9, 8, 1, 8
*/
#define CFG_ENABLE_TX_SCHED_WRR_VI_NAME "gEnableTxSchedWrrVI"
#define CFG_ENABLE_TX_SCHED_WRR_VI_DEFAULT ""
/*
* <ini>
* gEnableTxSchedWrrBE - Set TX sched parameters for BE
* @Default:
*
* This key is mapping to BE defined in data path module through
* OL_TX_SCHED_WRR_ADV_CAT_CFG_SPEC. The user can tune the
* WRR TX sched parameters such as skip, credit, limit, credit, disc for BE.
* e.g., gEnableTxSchedWrrBE = 10, 9, 8, 1, 8
*/
#define CFG_ENABLE_TX_SCHED_WRR_BE_NAME "gEnableTxSchedWrrBE"
#define CFG_ENABLE_TX_SCHED_WRR_BE_DEFAULT ""
/*
* <ini>
* gEnableTxSchedWrrBK - Set TX sched parameters for BK
* @Default:
*
* This key is mapping to BK defined in data path module through
* OL_TX_SCHED_WRR_ADV_CAT_CFG_SPEC. The user can tune the
* WRR TX sched parameters such as skip, credit, limit, credit, disc for BK.
* e.g., gEnableTxSchedWrrBK = 10, 9, 8, 1, 8
*/
#define CFG_ENABLE_TX_SCHED_WRR_BK_NAME "gEnableTxSchedWrrBK"
#define CFG_ENABLE_TX_SCHED_WRR_BK_DEFAULT ""
#ifdef CONFIG_DP_TRACE
/*
* Enable/disable DPTRACE
@ -6585,7 +6517,6 @@ struct hdd_config {
uint8_t sap_11ac_override;
uint8_t go_11ac_override;
uint8_t prefer_non_dfs_on_radar;
uint8_t max_msdus_per_rxinorderind;
/* parameter for defer timer for enabling TDLS on p2p listen */
uint32_t fine_time_meas_cap;
uint8_t max_scan_count;
@ -6619,15 +6550,6 @@ struct hdd_config {
uint32_t roam_trigger_reason_bitmask;
uint32_t roam_bg_scan_client_bitmap;
/* Tuning TX sched parameters for VO (skip credit limit credit disc) */
uint8_t tx_sched_wrr_vo[TX_SCHED_WRR_PARAM_STRING_LENGTH];
/* Tuning TX sched parameters for VI (skip credit limit credit disc) */
uint8_t tx_sched_wrr_vi[TX_SCHED_WRR_PARAM_STRING_LENGTH];
/* Tuning TX sched parameters for BE (skip credit limit credit disc) */
uint8_t tx_sched_wrr_be[TX_SCHED_WRR_PARAM_STRING_LENGTH];
/* Tuning TX sched parameters for BK (skip credit limit credit disc) */
uint8_t tx_sched_wrr_bk[TX_SCHED_WRR_PARAM_STRING_LENGTH];
bool apf_enabled;
#ifdef CONFIG_DP_TRACE
bool enable_dp_trace;

31
core/hdd/src/wlan_hdd_cfg.c
View file

@ -1649,13 +1649,6 @@ struct reg_table_entry g_registry_table[] = {
CFG_ENABLE_NON_DFS_CHAN_ON_RADAR_MIN,
CFG_ENABLE_NON_DFS_CHAN_ON_RADAR_MAX),
REG_VARIABLE(CFG_MAX_MSDUS_PER_RXIND_NAME, WLAN_PARAM_Integer,
struct hdd_config, max_msdus_per_rxinorderind,
VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT,
CFG_MAX_MSDUS_PER_RXIND_DEFAULT,
CFG_MAX_MSDUS_PER_RXIND_MIN,
CFG_MAX_MSDUS_PER_RXIND_MAX),
REG_VARIABLE(CFG_FINE_TIME_MEAS_CAPABILITY, WLAN_PARAM_HexInteger,
struct hdd_config, fine_time_meas_cap,
VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT,
@ -1798,30 +1791,6 @@ struct reg_table_entry g_registry_table[] = {
CFG_ROAM_SCAN_TRIGGER_REASON_BITMASK_MIN,
CFG_ROAM_SCAN_TRIGGER_REASON_BITMASK_MAX),
REG_VARIABLE_STRING(CFG_ENABLE_TX_SCHED_WRR_VO_NAME,
WLAN_PARAM_String,
struct hdd_config, tx_sched_wrr_vo,
VAR_FLAGS_OPTIONAL,
(void *) CFG_ENABLE_TX_SCHED_WRR_VO_DEFAULT),
REG_VARIABLE_STRING(CFG_ENABLE_TX_SCHED_WRR_VI_NAME,
WLAN_PARAM_String,
struct hdd_config, tx_sched_wrr_vi,
VAR_FLAGS_OPTIONAL,
(void *) CFG_ENABLE_TX_SCHED_WRR_VI_DEFAULT),
REG_VARIABLE_STRING(CFG_ENABLE_TX_SCHED_WRR_BE_NAME,
WLAN_PARAM_String,
struct hdd_config, tx_sched_wrr_be,
VAR_FLAGS_OPTIONAL,
(void *) CFG_ENABLE_TX_SCHED_WRR_BE_DEFAULT),
REG_VARIABLE_STRING(CFG_ENABLE_TX_SCHED_WRR_BK_NAME,
WLAN_PARAM_String,
struct hdd_config, tx_sched_wrr_bk,
VAR_FLAGS_OPTIONAL,
(void *) CFG_ENABLE_TX_SCHED_WRR_BK_DEFAULT),
REG_VARIABLE(CFG_CREATE_BUG_REPORT_FOR_SCAN, WLAN_PARAM_Integer,
struct hdd_config, bug_report_for_no_scan_results,
VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT,

45
core/hdd/src/wlan_hdd_main.c
View file

@ -2488,9 +2488,8 @@ void hdd_update_hw_sw_info(struct hdd_context *hdd_ctx)
static void
hdd_update_cds_ac_specs_params(struct hdd_context *hdd_ctx)
{
uint8_t num_entries = 0;
uint8_t tx_sched_wrr_param[TX_SCHED_WRR_PARAMS_NUM];
uint8_t *tx_sched_wrr_ac;
uint8_t tx_sched_wrr_param[TX_SCHED_WRR_PARAMS_NUM] = {0};
qdf_size_t out_size = 0;
int i;
struct cds_context *cds_ctx;
@ -2513,28 +2512,42 @@ hdd_update_cds_ac_specs_params(struct hdd_context *hdd_ctx)
for (i = 0; i < OL_TX_NUM_WMM_AC; i++) {
switch (i) {
case OL_TX_WMM_AC_BE:
tx_sched_wrr_ac = hdd_ctx->config->tx_sched_wrr_be;
qdf_uint8_array_parse(
cfg_get(hdd_ctx->psoc,
CFG_DP_ENABLE_TX_SCHED_WRR_BE),
tx_sched_wrr_param,
sizeof(tx_sched_wrr_param),
&out_size);
break;
case OL_TX_WMM_AC_BK:
tx_sched_wrr_ac = hdd_ctx->config->tx_sched_wrr_bk;
qdf_uint8_array_parse(
cfg_get(hdd_ctx->psoc,
CFG_DP_ENABLE_TX_SCHED_WRR_BK),
tx_sched_wrr_param,
sizeof(tx_sched_wrr_param),
&out_size);
break;
case OL_TX_WMM_AC_VI:
tx_sched_wrr_ac = hdd_ctx->config->tx_sched_wrr_vi;
qdf_uint8_array_parse(
cfg_get(hdd_ctx->psoc,
CFG_DP_ENABLE_TX_SCHED_WRR_VI),
tx_sched_wrr_param,
sizeof(tx_sched_wrr_param),
&out_size);
break;
case OL_TX_WMM_AC_VO:
tx_sched_wrr_ac = hdd_ctx->config->tx_sched_wrr_vo;
qdf_uint8_array_parse(
cfg_get(hdd_ctx->psoc,
CFG_DP_ENABLE_TX_SCHED_WRR_VO),
tx_sched_wrr_param,
sizeof(tx_sched_wrr_param),
&out_size);
break;
default:
tx_sched_wrr_ac = NULL;
break;
}
hdd_string_to_u8_array(tx_sched_wrr_ac,
tx_sched_wrr_param,
&num_entries,
sizeof(tx_sched_wrr_param));
if (num_entries == TX_SCHED_WRR_PARAMS_NUM) {
if (out_size == TX_SCHED_WRR_PARAMS_NUM) {
cds_ctx->ac_specs[i].wrr_skip_weight =
tx_sched_wrr_param[0];
cds_ctx->ac_specs[i].credit_threshold =
@ -2547,7 +2560,7 @@ hdd_update_cds_ac_specs_params(struct hdd_context *hdd_ctx)
tx_sched_wrr_param[4];
}
num_entries = 0;
out_size = 0;
}
}
@ -9751,7 +9764,7 @@ static int hdd_update_cds_config(struct hdd_context *hdd_ctx)
cds_cfg->max_station = value;
cds_cfg->sub_20_channel_width = WLAN_SUB_20_CH_WIDTH_NONE;
cds_cfg->max_msdus_per_rxinorderind =
hdd_ctx->config->max_msdus_per_rxinorderind;
cfg_get(hdd_ctx->psoc, CFG_DP_MAX_MSDUS_PER_RXIND);
cds_cfg->self_recovery_enabled = self_recovery;
cds_cfg->fw_timeout_crash = fw_timeout_crash;
cds_cfg->active_uc_apf_mode = hdd_ctx->config->active_uc_apf_mode;