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msm: kgsl: Update A660 variant GPU revision number

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A660 variant GPU correct revision number is A642. Update
the revision and revision checks to reflect correct value.

Change-Id: I6cc295c35c5a5d0ed5045271cbf50adc74cb15c3
Signed-off-by: Deepak Kumar <dkumar@codeaurora.org>
This commit is contained in:
Deepak Kumar 2021-04-12 14:24:23 +05:30
commit 8eaf5dc0ac
4 changed files with 20 additions and 19 deletions
Download patch file Download diff file Expand all files Collapse all files

8
drivers/gpu/msm/adreno-gpulist.h
View file

@ -1681,10 +1681,10 @@ static const struct adreno_a6xx_core adreno_gpu_core_a660v2 = {
.ctxt_record_size = 2496 * 1024,
};
static const struct adreno_a6xx_core adreno_gpu_core_a660_shima = {
static const struct adreno_a6xx_core adreno_gpu_core_a642 = {
.base = {
DEFINE_ADRENO_REV(ADRENO_REV_A660, 6, 6, 0, ANY_ID),
.compatible = "qcom,adreno-gpu-a660-shima",
DEFINE_ADRENO_REV(ADRENO_REV_A642, ANY_ID, ANY_ID, ANY_ID, ANY_ID),
.compatible = "qcom,adreno-gpu-a642",
.features = ADRENO_RPMH | ADRENO_GPMU | ADRENO_APRIV |
ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |
ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_ACD |
@ -1861,6 +1861,6 @@ static const struct adreno_gpu_core *adreno_gpulist[] = {
&adreno_gpu_core_a612.base,
&adreno_gpu_core_a616.base,
&adreno_gpu_core_a610.base,
&adreno_gpu_core_a660_shima.base,
&adreno_gpu_core_a642.base,
&adreno_gpu_core_a702.base,
};

18
drivers/gpu/msm/adreno.h
View file

@ -202,6 +202,7 @@ enum adreno_gpurev {
ADRENO_REV_A630 = 630,
ADRENO_REV_A635 = 635,
ADRENO_REV_A640 = 640,
ADRENO_REV_A642 = 642,
ADRENO_REV_A650 = 650,
ADRENO_REV_A660 = 660,
ADRENO_REV_A680 = 680,
@ -1053,12 +1054,11 @@ static inline int adreno_is_a6xx(struct adreno_device *adreno_dev)
ADRENO_GPUREV(adreno_dev) <= 702;
}
static inline int adreno_is_a660_shima(struct adreno_device *adreno_dev)
static inline int adreno_is_a642(struct adreno_device *adreno_dev)
{
return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A660) &&
(adreno_dev->gpucore->compatible &&
return (adreno_dev->gpucore->compatible &&
!strcmp(adreno_dev->gpucore->compatible,
"qcom,adreno-gpu-a660-shima"));
"qcom,adreno-gpu-a642"));
}
ADRENO_TARGET(a610, ADRENO_REV_A610)
@ -1073,12 +1073,13 @@ ADRENO_TARGET(a650, ADRENO_REV_A650)
ADRENO_TARGET(a680, ADRENO_REV_A680)
ADRENO_TARGET(a702, ADRENO_REV_A702)
/* A635 is derived from A660 and shares same logic */
/* A635 and A642 are derived from A660 and shares same logic */
static inline int adreno_is_a660(struct adreno_device *adreno_dev)
{
unsigned int rev = ADRENO_GPUREV(adreno_dev);
return (rev == ADRENO_REV_A660 || rev == ADRENO_REV_A635);
return (rev == ADRENO_REV_A660 || rev == ADRENO_REV_A635 ||
adreno_is_a642(adreno_dev));
}
/*
@ -1107,7 +1108,7 @@ static inline int adreno_is_a640_family(struct adreno_device *adreno_dev)
/*
* Derived GPUs from A650 needs to be added to this list.
* A650 is derived from A640 but register specs has been
* changed hence do not belongs to A640 family. A620,
* changed hence do not belongs to A640 family. A620, A642,
* A660, A690 follows the register specs of A650.
*
*/
@ -1116,7 +1117,8 @@ static inline int adreno_is_a650_family(struct adreno_device *adreno_dev)
unsigned int rev = ADRENO_GPUREV(adreno_dev);
return (rev == ADRENO_REV_A650 || rev == ADRENO_REV_A620 ||
rev == ADRENO_REV_A660 || rev == ADRENO_REV_A635);
rev == ADRENO_REV_A660 || rev == ADRENO_REV_A635 ||
adreno_is_a642(adreno_dev));
}
static inline int adreno_is_a619_holi(struct adreno_device *adreno_dev)

2
drivers/gpu/msm/adreno_a6xx.c
View file

@ -169,7 +169,7 @@ int a6xx_init(struct adreno_device *adreno_dev)
/* If the memory type is DDR 4, override the existing configuration */
if (of_fdt_get_ddrtype() == 0x7) {
if (adreno_is_a660_shima(adreno_dev) ||
if (adreno_is_a642(adreno_dev) ||
adreno_is_a635(adreno_dev))
adreno_dev->highest_bank_bit = 14;
else if ((adreno_is_a650(adreno_dev) ||

11
drivers/gpu/msm/adreno_a6xx_gmu.c
View file

@ -1354,11 +1354,10 @@ void a6xx_gmu_register_config(struct adreno_device *adreno_dev)
| ((ADRENO_CHIPID_PATCH(adreno_dev->chipid) & 0xf) << 8);
/*
* For A660 GPU variant, GMU firmware expects chipid as per below
* format to differentiate between A660 and A660 variant. In device
* tree, target version is specified as high nibble of patch to align
* with usermode driver expectation. Format the chipid according to
* firmware requirement.
* For A642 GPU, GMU firmware expects chipid as per below format.
* In device tree, target version is specified as high nibble of
* patch to align with usermode driver expectation. Format the
* chipid according to firmware requirement.
*
* Bit 11-8: patch version
* Bit 15-12: minor version
@ -1366,7 +1365,7 @@ void a6xx_gmu_register_config(struct adreno_device *adreno_dev)
* Bit 27-24: core version
* Bit 31-28: target version
*/
if (adreno_is_a660_shima(adreno_dev))
if (adreno_is_a642(adreno_dev))
chipid |= ((ADRENO_CHIPID_PATCH(adreno_dev->chipid) >> 4) << 28);
gmu_core_regwrite(device, A6XX_GMU_HFI_SFR_ADDR, chipid);