mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-08 21:22:09 -04:00
Merge "msm: camera: isp: Support all patterns for TOP TPG" into camera-kernel.lnx.4.0
This commit is contained in:
commit
8ef61574d0
9 changed files with 101 additions and 10 deletions
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@ -3252,6 +3252,17 @@ static int cam_tfe_mgr_start_hw(void *hw_mgr_priv, void *start_hw_args)
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if (ctx->init_done && start_isp->start_only)
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goto start_only;
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/* set tpg debug information for top tpg */
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for (i = 0; i < CAM_TOP_TPG_HW_NUM_MAX; i++) {
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if (g_tfe_hw_mgr.tpg_devices[i]) {
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rc = g_tfe_hw_mgr.tpg_devices[i]->hw_ops.process_cmd(
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g_tfe_hw_mgr.tpg_devices[i]->hw_priv,
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CAM_ISP_HW_CMD_TPG_SET_PATTERN,
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&g_tfe_hw_mgr.debug_cfg.set_tpg_pattern,
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sizeof(g_tfe_hw_mgr.debug_cfg.set_tpg_pattern));
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}
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}
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list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, list) {
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for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) {
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if (!hw_mgr_res->hw_res[i])
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@ -5813,9 +5824,10 @@ static int cam_tfe_hw_mgr_debug_register(void)
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int rc = 0;
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struct dentry *dbgfileptr = NULL;
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g_tfe_hw_mgr.debug_cfg.set_tpg_pattern = CAM_TOP_TPG_DEFAULT_PATTERN;
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dbgfileptr = debugfs_create_dir("camera_tfe", NULL);
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if (!dbgfileptr) {
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CAM_ERR(CAM_ISP,"DebugFS could not create directory!");
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CAM_ERR(CAM_ISP, "DebugFS could not create directory!");
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rc = -ENOENT;
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goto end;
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}
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@ -5833,6 +5845,9 @@ static int cam_tfe_hw_mgr_debug_register(void)
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dbgfileptr = debugfs_create_u32("enable_csid_recovery", 0644,
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g_tfe_hw_mgr.debug_cfg.dentry,
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&g_tfe_hw_mgr.debug_cfg.enable_csid_recovery);
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dbgfileptr = debugfs_create_u32("set_tpg_pattern", 0644,
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g_tfe_hw_mgr.debug_cfg.dentry,
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&g_tfe_hw_mgr.debug_cfg.set_tpg_pattern);
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dbgfileptr = debugfs_create_file("tfe_camif_debug", 0644,
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g_tfe_hw_mgr.debug_cfg.dentry, NULL, &cam_tfe_camif_debug);
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dbgfileptr = debugfs_create_u32("per_req_reg_dump", 0644,
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _CAM_TFE_HW_MGR_H_
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@ -30,6 +30,7 @@
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* @enable_recovery: enable recovery
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* @enable_csid_recovery: enable csid recovery
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* @camif_debug: enable sensor diagnosis status
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* @set_tpg_pattern: tpg pattern information
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* @enable_reg_dump: enable reg dump on error;
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* @per_req_reg_dump: Enable per request reg dump
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*
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@ -40,6 +41,7 @@ struct cam_tfe_hw_mgr_debug {
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uint32_t enable_recovery;
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uint32_t enable_csid_recovery;
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uint32_t camif_debug;
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uint32_t set_tpg_pattern;
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uint32_t enable_reg_dump;
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uint32_t per_req_reg_dump;
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};
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@ -138,6 +138,7 @@ enum cam_isp_hw_cmd_type {
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CAM_ISP_HW_CMD_GET_CLOCK_RATE,
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CAM_ISP_HW_CMD_DYNAMIC_CLOCK_UPDATE,
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CAM_ISP_HW_DUMP_HW_SRC_CLK_RATE,
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CAM_ISP_HW_CMD_TPG_SET_PATTERN,
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CAM_ISP_HW_CMD_MAX,
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};
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _CAM_TOP_TPG_HW_INTF_H_
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@ -14,7 +14,8 @@
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#define CAM_TOP_TPG_HW_NUM_MAX 3
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/* Max supported number of DT for TPG */
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#define CAM_TOP_TPG_MAX_SUPPORTED_DT 4
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/* TPG default pattern should be color bar */
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#define CAM_TOP_TPG_DEFAULT_PATTERN 0x8
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/**
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* enum cam_top_tpg_id - top tpg hw instance id
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*/
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _CAM_TOP_TPG101_H_
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@ -49,6 +49,7 @@ static struct cam_top_tpg_ver1_reg_offset cam_top_tpg101_reg = {
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.tpg_payload_mode_color = 0x8,
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.tpg_split_en_shift = 5,
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.top_mux_reg_offset = 0x1C,
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.top_unicolor_bar_shift = 2,
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};
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struct cam_top_tpg_hw_info cam_top_tpg101_hw_info = {
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
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*/
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#include <linux/iopoll.h>
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@ -282,6 +282,19 @@ irqreturn_t cam_top_tpg_irq(int irq_num, void *data)
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return IRQ_HANDLED;
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}
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static int cam_top_tpg_set_top_tpg_pattern(struct cam_top_tpg_hw *tpg_hw,
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void *cmd_args)
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{
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uint32_t *top_tpg_pattern;
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top_tpg_pattern = (uint32_t *) cmd_args;
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tpg_hw->tpg_pattern = *top_tpg_pattern;
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CAM_DBG(CAM_ISP, "TPG:%d set tpg debug value:%d",
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tpg_hw->hw_intf->hw_idx, tpg_hw->tpg_pattern);
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return 0;
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}
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static int cam_top_tpg_process_cmd(void *hw_priv,
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uint32_t cmd_type, void *cmd_args, uint32_t arg_size)
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{
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@ -301,6 +314,9 @@ static int cam_top_tpg_process_cmd(void *hw_priv,
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case CAM_ISP_HW_CMD_TPG_PHY_CLOCK_UPDATE:
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rc = cam_top_tpg_set_phy_clock(tpg_hw, cmd_args);
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break;
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case CAM_ISP_HW_CMD_TPG_SET_PATTERN:
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rc = cam_top_tpg_set_top_tpg_pattern(tpg_hw, cmd_args);
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break;
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default:
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CAM_ERR(CAM_ISP, "TPG:%d unsupported cmd:%d",
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tpg_hw->hw_intf->hw_idx, cmd_type);
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _CAM_TOP_TPG_CORE_H_
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@ -106,7 +106,7 @@ struct cam_top_tpg_cfg {
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* @hw_info: tpg hw device information
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* @tpg_info: tpg hw specific information
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* @tpg_res: tpg resource
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* @tpg_cfg: tpg configuration
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* @tpg_pattern: tpg pattern configuration
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* @clk_rate clock rate
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* @lock_state lock state
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* @tpg_complete tpg completion
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@ -117,6 +117,7 @@ struct cam_top_tpg_hw {
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struct cam_hw_info *hw_info;
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struct cam_top_tpg_hw_info *tpg_info;
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struct cam_isp_resource_node tpg_res;
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uint32_t tpg_pattern;
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uint64_t clk_rate;
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spinlock_t lock_state;
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struct completion tpg_complete;
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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*/
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#include <linux/iopoll.h>
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@ -204,6 +204,7 @@ static int cam_top_tpg_ver1_start(
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struct cam_top_tpg_ver1_reg_offset *tpg_reg;
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struct cam_top_tpg_cfg *tpg_data;
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uint32_t i, val;
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uint32_t in_format = 0;
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if (!hw_priv || !start_args ||
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(arg_size != sizeof(struct cam_isp_resource_node))) {
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@ -244,6 +245,7 @@ static int cam_top_tpg_ver1_start(
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tpg_reg->tpg_dt_0_cfg_2 + 0x10 * i);
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}
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/* configure one DT, infinite frames */
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val = (tpg_num_dt_map[tpg_data->num_active_dts-1] <<
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tpg_reg->tpg_num_dts_shift_val) | tpg_data->vc_num[0];
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cam_io_w_mb(val, soc_info->reg_map[0].mem_base + tpg_reg->tpg_vc_cfg0);
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@ -260,6 +262,57 @@ static int cam_top_tpg_ver1_start(
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cam_io_w_mb(0x2581F4,
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soc_info->reg_map[0].mem_base + tpg_reg->tpg_vc_cfg1);
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/* configure tpg pattern */
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in_format = tpg_data->dt_cfg[0].encode_format & 0xF;
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val = in_format << tpg_reg->tpg_dt_encode_format_shift;
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switch (tpg_hw->tpg_pattern) {
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case 0x0:
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val = val | tpg_hw->tpg_pattern;
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break;
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case 0x1:
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val = val | tpg_hw->tpg_pattern;
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break;
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case 0x2:
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val = val | tpg_hw->tpg_pattern;
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break;
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case 0x3:
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val = val | tpg_hw->tpg_pattern;
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break;
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case 0x4:
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val = val | tpg_hw->tpg_pattern;
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break;
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case 0x5:
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val = val | tpg_hw->tpg_pattern;
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break;
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case 0x6:
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val = val | tpg_hw->tpg_pattern;
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break;
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case 0x7:
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val = val | tpg_hw->tpg_pattern;
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break;
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case 0x8:
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/* unicolor bar selection */
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val = 0x1 | (1 << tpg_reg->top_unicolor_bar_shift);
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cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
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tpg_reg->tpg_color_bar_cfg);
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val = (in_format << tpg_reg->tpg_dt_encode_format_shift) |
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tpg_hw->tpg_pattern;
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break;
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default:
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/* frame with split color bar */
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val = 1 << tpg_reg->tpg_split_en_shift;
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cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
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tpg_reg->tpg_color_bar_cfg);
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val = (in_format << tpg_reg->tpg_dt_encode_format_shift) |
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CAM_TOP_TPG_DEFAULT_PATTERN;
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break;
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}
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cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
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tpg_reg->tpg_dt_0_cfg_2);
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/* config pix pattern */
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val = (1 << tpg_reg->tpg_split_en_shift);
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cam_io_w_mb(tpg_data->pix_pattern, soc_info->reg_map[0].mem_base +
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tpg_reg->tpg_common_gen_cfg);
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _CAM_TOP_TPG_VER1_H_
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@ -48,6 +48,7 @@ struct cam_top_tpg_ver1_reg_offset {
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uint32_t tpg_payload_mode_color;
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uint32_t tpg_split_en_shift;
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uint32_t top_mux_reg_offset;
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uint32_t top_unicolor_bar_shift;
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};
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int cam_top_tpg_ver1_init(struct cam_top_tpg_hw *tpg_hw);
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