mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 03:01:39 -04:00
USB patches for 4.12-rc1
Here is the big USB patchset for 4.12-rc1. Lots of good stuff here, after many many many attempts, the kernel finally has a working typeC interface, many thanks to the Heikki and Guenter and others who have taken the time to get this merged. It wasn't an easy path for them at all. There's also a staging driver that uses this new api, which is why it's coming in through this tree. Along with that, there's the usual huge number of changes for gadget drivers, xhci, and other stuff. Johan also finally refactored pretty much every driver that was looking at USB endpoints to do it in a common way, which will help prevent any "badly-formed" devices from causing problems in drivers. That too wasn't a simple task. All of these have been in linux-next for a while with no reported issues. Signed-off-by: Greg Kroah-Hartman <[email protected]> -----BEGIN PGP SIGNATURE----- iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCWQvEIQ8cZ3JlZ0Brcm9h aC5jb20ACgkQMUfUDdst+yny4gCePCXxnrQdMWE+IMXf1H1hMubLkVkAn0ZWgQkq BspgO7ZmGb+9Fpf6YvNz =nwAu -----END PGP SIGNATURE----- Merge tag 'usb-4.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB updates from Greg KH: "Here is the big USB patchset for 4.12-rc1. Lots of good stuff here, after many many many attempts, the kernel finally has a working typeC interface, many thanks to Heikki and Guenter and others who have taken the time to get this merged. It wasn't an easy path for them at all. There's also a staging driver that uses this new api, which is why it's coming in through this tree. Along with that, there's the usual huge number of changes for gadget drivers, xhci, and other stuff. Johan also finally refactored pretty much every driver that was looking at USB endpoints to do it in a common way, which will help prevent any "badly-formed" devices from causing problems in drivers. That too wasn't a simple task. All of these have been in linux-next for a while with no reported issues" * tag 'usb-4.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (263 commits) staging: typec: Fairchild FUSB302 Type-c chip driver staging: typec: Type-C Port Controller Interface driver (tcpci) staging: typec: USB Type-C Port Manager (tcpm) usb: host: xhci: remove #ifdef around PM functions usb: musb: don't mark of_dev_auxdata as initdata usb: misc: legousbtower: Fix buffers on stack USB: Revert "cdc-wdm: fix "out-of-sync" due to missing notifications" usb: Make sure usb/phy/of gets built-in USB: storage: e-mail update in drivers/usb/storage/unusual_devs.h usb: host: xhci: print correct command ring address usb: host: xhci: delete sp_dma_buffers for scratchpad usb: host: xhci: using correct specification chapter reference for DCBAAP xhci: switch to pci_alloc_irq_vectors usb: host: xhci-plat: set resume_quirk() for R-Car controllers usb: host: xhci-plat: add resume_quirk() usb: host: xhci-plat: enable clk in resume timing usb: host: plat: Enable xHCI plat runtime PM USB: serial: ftdi_sio: add device ID for Microsemi/Arrow SF2PLUS Dev Kit USB: serial: constify static arrays usb: fix some references for /proc/bus/usb ...
This commit is contained in:
Linus Torvalds
commit
8f28472a73
230 changed files with 15570 additions and 3809 deletions
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@ -6,12 +6,11 @@ This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC.
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Required properties (controller (parent) node):
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- compatible : should be one of
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"mediatek,mt2701-u3phy"
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"mediatek,mt2712-u3phy"
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"mediatek,mt8173-u3phy"
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- reg : offset and length of register for phy, exclude port's
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register.
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- clocks : a list of phandle + clock-specifier pairs, one for each
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entry in clock-names
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- clock-names : must contain
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- clocks : (deprecated, use port's clocks instead) a list of phandle +
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clock-specifier pairs, one for each entry in clock-names
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- clock-names : (deprecated, use port's one instead) must contain
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"u3phya_ref": for reference clock of usb3.0 analog phy.
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Required nodes : a sub-node is required for each port the controller
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@ -19,8 +18,19 @@ Required nodes : a sub-node is required for each port the controller
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'reg' property is used inside these nodes to describe
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the controller's topology.
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Optional properties (controller (parent) node):
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- reg : offset and length of register shared by multiple ports,
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exclude port's private register. It is needed on mt2701
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and mt8173, but not on mt2712.
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Required properties (port (child) node):
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- reg : address and length of the register set for the port.
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- clocks : a list of phandle + clock-specifier pairs, one for each
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entry in clock-names
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- clock-names : must contain
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"ref": 48M reference clock for HighSpeed analog phy; and 26M
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reference clock for SuperSpeed analog phy, sometimes is
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24M, 25M or 27M, depended on platform.
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- #phy-cells : should be 1 (See second example)
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cell after port phandle is phy type from:
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- PHY_TYPE_USB2
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@ -31,21 +41,31 @@ Example:
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u3phy: usb-phy@11290000 {
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compatible = "mediatek,mt8173-u3phy";
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reg = <0 0x11290000 0 0x800>;
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clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
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clock-names = "u3phya_ref";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "okay";
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phy_port0: port@11290800 {
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reg = <0 0x11290800 0 0x800>;
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u2port0: usb-phy@11290800 {
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reg = <0 0x11290800 0 0x100>;
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clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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phy_port1: port@11291000 {
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reg = <0 0x11291000 0 0x800>;
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u3port0: usb-phy@11290900 {
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reg = <0 0x11290800 0 0x700>;
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clocks = <&clk26m>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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u2port1: usb-phy@11291000 {
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reg = <0 0x11291000 0 0x100>;
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clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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@ -64,7 +84,54 @@ Example:
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usb30: usb@11270000 {
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...
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phys = <&phy_port0 PHY_TYPE_USB3>;
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phy-names = "usb3-0";
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phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
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phy-names = "usb2-0", "usb3-0";
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...
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};
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Layout differences of banks between mt8173/mt2701 and mt2712
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-------------------------------------------------------------
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mt8173 and mt2701:
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port offset bank
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shared 0x0000 SPLLC
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0x0100 FMREG
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u2 port0 0x0800 U2PHY_COM
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u3 port0 0x0900 U3PHYD
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0x0a00 U3PHYD_BANK2
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0x0b00 U3PHYA
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0x0c00 U3PHYA_DA
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u2 port1 0x1000 U2PHY_COM
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u3 port1 0x1100 U3PHYD
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0x1200 U3PHYD_BANK2
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0x1300 U3PHYA
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0x1400 U3PHYA_DA
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u2 port2 0x1800 U2PHY_COM
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...
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mt2712:
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port offset bank
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u2 port0 0x0000 MISC
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0x0100 FMREG
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0x0300 U2PHY_COM
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u3 port0 0x0700 SPLLC
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0x0800 CHIP
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0x0900 U3PHYD
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0x0a00 U3PHYD_BANK2
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0x0b00 U3PHYA
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0x0c00 U3PHYA_DA
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u2 port1 0x1000 MISC
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0x1100 FMREG
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0x1300 U2PHY_COM
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u3 port1 0x1700 SPLLC
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0x1800 CHIP
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0x1900 U3PHYD
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0x1a00 U3PHYD_BANK2
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0x1b00 U3PHYA
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0x1c00 U3PHYA_DA
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u2 port2 0x2000 MISC
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...
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SPLLC shared by u3 ports and FMREG shared by u2 ports on
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mt8173/mt2701 are put back into each port; a new bank MISC for
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u2 ports and CHIP for u3 ports are added on mt2712.
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@ -2,6 +2,7 @@ ROCKCHIP USB2.0 PHY WITH INNO IP BLOCK
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Required properties (phy (parent) node):
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- compatible : should be one of the listed compatibles:
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* "rockchip,rk3328-usb2phy"
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* "rockchip,rk3366-usb2phy"
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* "rockchip,rk3399-usb2phy"
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- reg : the address offset of grf for usb-phy configuration.
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@ -11,6 +12,11 @@ Required properties (phy (parent) node):
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Optional properties:
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- clocks : phandle + phy specifier pair, for the input clock of phy.
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- clock-names : input clock name of phy, must be "phyclk".
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- assigned-clocks : phandle of usb 480m clock.
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- assigned-clock-parents : parent of usb 480m clock, select between
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usb-phy output 480m and xin24m.
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Refer to clk/clock-bindings.txt for generic clock
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consumer properties.
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Required nodes : a sub-node is required for each port the phy provides.
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The sub-node name is used to identify host or otg port,
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106
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
Normal file
106
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
Normal file
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@ -0,0 +1,106 @@
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Qualcomm QMP PHY controller
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===========================
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QMP phy controller supports physical layer functionality for a number of
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controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
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Required properties:
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- compatible: compatible list, contains:
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"qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
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"qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
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- reg: offset and length of register set for PHY's common serdes block.
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- #clock-cells: must be 1
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- Phy pll outputs a bunch of clocks for Tx, Rx and Pipe
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interface (for pipe based PHYs). These clock are then gate-controlled
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by gcc.
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- #address-cells: must be 1
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- #size-cells: must be 1
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- ranges: must be present
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- clocks: a list of phandles and clock-specifier pairs,
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one for each entry in clock-names.
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- clock-names: "cfg_ahb" for phy config clock,
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"aux" for phy aux clock,
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"ref" for 19.2 MHz ref clk,
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For "qcom,msm8996-qmp-pcie-phy" must contain:
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"aux", "cfg_ahb", "ref".
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For "qcom,msm8996-qmp-usb3-phy" must contain:
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"aux", "cfg_ahb", "ref".
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- resets: a list of phandles and reset controller specifier pairs,
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one for each entry in reset-names.
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- reset-names: "phy" for reset of phy block,
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"common" for phy common block reset,
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"cfg" for phy's ahb cfg block reset (Optional).
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For "qcom,msm8996-qmp-pcie-phy" must contain:
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"phy", "common", "cfg".
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For "qcom,msm8996-qmp-usb3-phy" must contain
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"phy", "common".
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- vdda-phy-supply: Phandle to a regulator supply to PHY core block.
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- vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
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Optional properties:
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- vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
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pll block.
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Required nodes:
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- Each device node of QMP phy is required to have as many child nodes as
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the number of lanes the PHY has.
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Required properties for child node:
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- reg: list of offset and length pairs of register sets for PHY blocks -
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tx, rx and pcs.
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- #phy-cells: must be 0
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- clocks: a list of phandles and clock-specifier pairs,
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one for each entry in clock-names.
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- clock-names: Must contain following for pcie and usb qmp phys:
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"pipe<lane-number>" for pipe clock specific to each lane.
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- resets: a list of phandles and reset controller specifier pairs,
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one for each entry in reset-names.
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- reset-names: Must contain following for pcie qmp phys:
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"lane<lane-number>" for reset specific to each lane.
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Example:
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phy@34000 {
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compatible = "qcom,msm8996-qmp-pcie-phy";
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reg = <0x34000 0x488>;
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#clock-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
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<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_CLKREF_CLK>;
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clock-names = "aux", "cfg_ahb", "ref";
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vdda-phy-supply = <&pm8994_l28>;
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vdda-pll-supply = <&pm8994_l12>;
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resets = <&gcc GCC_PCIE_PHY_BCR>,
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<&gcc GCC_PCIE_PHY_COM_BCR>,
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<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
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reset-names = "phy", "common", "cfg";
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pciephy_0: lane@35000 {
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reg = <0x35000 0x130>,
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<0x35200 0x200>,
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<0x35400 0x1dc>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
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clock-names = "pipe0";
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resets = <&gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "lane0";
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};
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pciephy_1: lane@36000 {
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...
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...
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};
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43
Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
Normal file
43
Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
Normal file
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@ -0,0 +1,43 @@
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Qualcomm QUSB2 phy controller
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=============================
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QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
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Required properties:
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- compatible: compatible list, contains "qcom,msm8996-qusb2-phy".
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- reg: offset and length of the PHY register set.
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- #phy-cells: must be 0.
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- clocks: a list of phandles and clock-specifier pairs,
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one for each entry in clock-names.
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- clock-names: must be "cfg_ahb" for phy config clock,
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"ref" for 19.2 MHz ref clk,
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"iface" for phy interface clock (Optional).
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- vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
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- vdda-phy-dpdm-supply: Phandle to 3.1V regulator supply to Dp/Dm port signals.
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- resets: Phandle to reset to phy block.
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Optional properties:
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- nvmem-cells: Phandle to nvmem cell that contains 'HS Tx trim'
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tuning parameter value for qusb2 phy.
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- qcom,tcsr-syscon: Phandle to TCSR syscon register region.
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Example:
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hsusb_phy: phy@7411000 {
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compatible = "qcom,msm8996-qusb2-phy";
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reg = <0x7411000 0x180>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
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<&gcc GCC_RX1_USB2_CLKREF_CLK>,
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clock-names = "cfg_ahb", "ref";
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vdda-pll-supply = <&pm8994_l12>;
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vdda-phy-dpdm-supply = <&pm8994_l24>;
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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nvmem-cells = <&qusb2p_hstx_trim>;
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};
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@ -30,6 +30,7 @@ Optional Properties:
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- reset-names: Only allow the following entries:
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- phy-reset
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- resets: Must contain an entry for each entry in reset-names.
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- vbus-supply: power-supply phandle for vbus power source
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Example:
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@ -15,6 +15,7 @@ Required properties:
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- reg : a list of offset + length pairs
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- reg-names :
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* "phy_ctrl"
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* "pmu0" for H3, V3s and A64
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* "pmu1"
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* "pmu2" for sun4i, sun6i or sun7i
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- #phy-cells : from the generic phy bindings, must be 1
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@ -8,6 +8,8 @@ From RK3368 SoCs, the GRF is divided into two sections,
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- SGRF, used for general secure system,
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- PMUGRF, used for always on system
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On RK3328 SoCs, the GRF adds a section for USB2PHYGRF,
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Required Properties:
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- compatible: GRF should be one of the following:
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@ -23,6 +25,8 @@ Required Properties:
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- "rockchip,rk3399-pmugrf", "syscon": for rk3399
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- compatible: SGRF should be one of the following
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- "rockchip,rk3288-sgrf", "syscon": for rk3288
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- compatible: USB2PHYGRF should be one of the followings
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- "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328
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- reg: physical base address of the controller and length of memory mapped
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region.
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@ -1,7 +1,9 @@
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* EHCI controller, Orion Marvell variants
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Required properties:
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- compatible: must be "marvell,orion-ehci"
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- compatible: must be one of the following
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"marvell,orion-ehci"
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"marvell,armada-3700-ehci"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- interrupts: The EHCI interrupt
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@ -22,6 +22,7 @@ Optional properties:
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property is used if any real OTG features(HNP/SRP/ADP)
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is enabled, if ADP is required, otg-rev should be
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0x0200 or above.
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- companion: phandle of a companion
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- hnp-disable: tells OTG controllers we want to disable OTG HNP, normally HNP
|
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is the basic function of real OTG except you want it
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||||
to be a srp-capable only B device.
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|
|
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Loading…
Reference in a new issue