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Merge "net: cnss2: Update CNSS2 driver"

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This commit is contained in:
qctecmdr 2019-12-17 03:26:00 -08:00 • committed by Gerrit - the friendly Code Review server
commit 8f4fbfd66a
14 changed files with 2158 additions and 422 deletions
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79
drivers/net/wireless/cnss2/bus.c
View file

@ -186,6 +186,36 @@ int cnss_bus_force_fw_assert_hdlr(struct cnss_plat_data *plat_priv)
}
}
int cnss_bus_qmi_send_get(struct cnss_plat_data *plat_priv)
{
if (!plat_priv)
return -ENODEV;
switch (plat_priv->bus_type) {
case CNSS_BUS_PCI:
return cnss_pci_qmi_send_get(plat_priv->bus_priv);
default:
cnss_pr_err("Unsupported bus type: %d\n",
plat_priv->bus_type);
return -EINVAL;
}
}
int cnss_bus_qmi_send_put(struct cnss_plat_data *plat_priv)
{
if (!plat_priv)
return -ENODEV;
switch (plat_priv->bus_type) {
case CNSS_BUS_PCI:
return cnss_pci_qmi_send_put(plat_priv->bus_priv);
default:
cnss_pr_err("Unsupported bus type: %d\n",
plat_priv->bus_type);
return -EINVAL;
}
}
void cnss_bus_fw_boot_timeout_hdlr(struct timer_list *t)
{
struct cnss_plat_data *plat_priv =
@ -372,3 +402,52 @@ int cnss_bus_update_status(struct cnss_plat_data *plat_priv,
return -EINVAL;
}
}
int cnss_bus_is_device_down(struct cnss_plat_data *plat_priv)
{
if (!plat_priv)
return -ENODEV;
switch (plat_priv->bus_type) {
case CNSS_BUS_PCI:
return cnss_pcie_is_device_down(plat_priv->bus_priv);
default:
cnss_pr_dbg("Unsupported bus type: %d\n",
plat_priv->bus_type);
return 0;
}
}
int cnss_bus_debug_reg_read(struct cnss_plat_data *plat_priv, u32 offset,
u32 *val)
{
if (!plat_priv)
return -ENODEV;
switch (plat_priv->bus_type) {
case CNSS_BUS_PCI:
return cnss_pci_debug_reg_read(plat_priv->bus_priv, offset,
val);
default:
cnss_pr_dbg("Unsupported bus type: %d\n",
plat_priv->bus_type);
return 0;
}
}
int cnss_bus_debug_reg_write(struct cnss_plat_data *plat_priv, u32 offset,
u32 val)
{
if (!plat_priv)
return -ENODEV;
switch (plat_priv->bus_type) {
case CNSS_BUS_PCI:
return cnss_pci_debug_reg_write(plat_priv->bus_priv, offset,
val);
default:
cnss_pr_dbg("Unsupported bus type: %d\n",
plat_priv->bus_type);
return 0;
}
}

7
drivers/net/wireless/cnss2/bus.h
View file

@ -30,6 +30,8 @@ int cnss_bus_alloc_qdss_mem(struct cnss_plat_data *plat_priv);
void cnss_bus_free_qdss_mem(struct cnss_plat_data *plat_priv);
u32 cnss_bus_get_wake_irq(struct cnss_plat_data *plat_priv);
int cnss_bus_force_fw_assert_hdlr(struct cnss_plat_data *plat_priv);
int cnss_bus_qmi_send_get(struct cnss_plat_data *plat_priv);
int cnss_bus_qmi_send_put(struct cnss_plat_data *plat_priv);
void cnss_bus_fw_boot_timeout_hdlr(struct timer_list *t);
void cnss_bus_collect_dump_info(struct cnss_plat_data *plat_priv,
bool in_panic);
@ -45,5 +47,10 @@ int cnss_bus_call_driver_modem_status(struct cnss_plat_data *plat_priv,
int modem_current_status);
int cnss_bus_update_status(struct cnss_plat_data *plat_priv,
enum cnss_driver_status status);
int cnss_bus_is_device_down(struct cnss_plat_data *plat_priv);
int cnss_bus_debug_reg_read(struct cnss_plat_data *plat_priv, u32 offset,
u32 *val);
int cnss_bus_debug_reg_write(struct cnss_plat_data *plat_priv, u32 offset,
u32 val);
#endif /* _CNSS_BUS_H */

72
drivers/net/wireless/cnss2/debug.c
View file

@ -5,9 +5,12 @@
#include <linux/seq_file.h>
#include <linux/debugfs.h>
#include "main.h"
#include "bus.h"
#include "debug.h"
#include "pci.h"
#define MMIO_REG_ACCESS_MEM_TYPE 0xFF
void *cnss_ipc_log_context;
void *cnss_ipc_log_long_context;
@ -107,6 +110,9 @@ static int cnss_stats_show_state(struct seq_file *s,
case CNSS_IN_SUSPEND_RESUME:
seq_puts(s, "IN_SUSPEND_RESUME");
continue;
case CNSS_IN_REBOOT:
seq_puts(s, "IN_REBOOT");
continue;
}
seq_printf(s, "UNKNOWN-%d", i);
@ -194,7 +200,7 @@ static ssize_t cnss_dev_boot_debug_write(struct file *fp,
ret = -EINVAL;
}
if (ret)
if (ret < 0)
return ret;
return count;
@ -238,6 +244,8 @@ static int cnss_reg_read_debug_show(struct seq_file *s, void *data)
mutex_lock(&plat_priv->dev_lock);
if (!plat_priv->diag_reg_read_buf) {
seq_puts(s, "\nUsage: echo <mem_type> <offset> <data_len> > <debugfs_path>/cnss/reg_read\n");
seq_puts(s, "Use mem_type = 0xff for register read by IO access, data_len will be ignored\n");
seq_puts(s, "Use other mem_type for register read by QMI\n");
mutex_unlock(&plat_priv->dev_lock);
return 0;
}
@ -269,16 +277,11 @@ static ssize_t cnss_reg_read_debug_write(struct file *fp,
char *sptr, *token;
unsigned int len = 0;
u32 reg_offset, mem_type;
u32 data_len = 0;
u32 data_len = 0, reg_val = 0;
u8 *reg_buf = NULL;
const char *delim = " ";
int ret = 0;
if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
cnss_pr_err("Firmware is not ready yet\n");
return -EINVAL;
}
len = min(count, sizeof(buf) - 1);
if (copy_from_user(buf, user_buf, len))
return -EFAULT;
@ -313,6 +316,20 @@ static ssize_t cnss_reg_read_debug_write(struct file *fp,
if (kstrtou32(token, 0, &data_len))
return -EINVAL;
if (mem_type == MMIO_REG_ACCESS_MEM_TYPE) {
ret = cnss_bus_debug_reg_read(plat_priv, reg_offset, &reg_val);
if (ret)
return ret;
cnss_pr_dbg("Read 0x%x from register offset 0x%x\n", reg_val,
reg_offset);
return count;
}
if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
cnss_pr_err("Firmware is not ready yet\n");
return -EINVAL;
}
mutex_lock(&plat_priv->dev_lock);
kfree(plat_priv->diag_reg_read_buf);
plat_priv->diag_reg_read_buf = NULL;
@ -357,6 +374,8 @@ static const struct file_operations cnss_reg_read_debug_fops = {
static int cnss_reg_write_debug_show(struct seq_file *s, void *data)
{
seq_puts(s, "\nUsage: echo <mem_type> <offset> <reg_val> > <debugfs_path>/cnss/reg_write\n");
seq_puts(s, "Use mem_type = 0xff for register write by IO access\n");
seq_puts(s, "Use other mem_type for register write by QMI\n");
return 0;
}
@ -374,11 +393,6 @@ static ssize_t cnss_reg_write_debug_write(struct file *fp,
const char *delim = " ";
int ret = 0;
if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
cnss_pr_err("Firmware is not ready yet\n");
return -EINVAL;
}
len = min(count, sizeof(buf) - 1);
if (copy_from_user(buf, user_buf, len))
return -EFAULT;
@ -413,6 +427,20 @@ static ssize_t cnss_reg_write_debug_write(struct file *fp,
if (kstrtou32(token, 0, &reg_val))
return -EINVAL;
if (mem_type == MMIO_REG_ACCESS_MEM_TYPE) {
ret = cnss_bus_debug_reg_write(plat_priv, reg_offset, reg_val);
if (ret)
return ret;
cnss_pr_dbg("Wrote 0x%x to register offset 0x%x\n", reg_val,
reg_offset);
return count;
}
if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
cnss_pr_err("Firmware is not ready yet\n");
return -EINVAL;
}
ret = cnss_wlfw_athdiag_write_send_sync(plat_priv, reg_offset, mem_type,
sizeof(u32),
(u8 *)&reg_val);
@ -477,12 +505,16 @@ static ssize_t cnss_runtime_pm_debug_write(struct file *fp,
cnss_pci_pm_runtime_put_noidle(pci_priv);
} else if (sysfs_streq(cmd, "mark_last_busy")) {
cnss_pci_pm_runtime_mark_last_busy(pci_priv);
} else if (sysfs_streq(cmd, "resume_bus")) {
cnss_pci_resume_bus(pci_priv);
} else if (sysfs_streq(cmd, "suspend_bus")) {
cnss_pci_suspend_bus(pci_priv);
} else {
cnss_pr_err("Runtime PM debugfs command is invalid\n");
ret = -EINVAL;
}
if (ret)
if (ret < 0)
return ret;
return count;
@ -493,11 +525,15 @@ static int cnss_runtime_pm_debug_show(struct seq_file *s, void *data)
seq_puts(s, "\nUsage: echo <action> > <debugfs_path>/cnss/runtime_pm\n");
seq_puts(s, "<action> can be one of below:\n");
seq_puts(s, "usage_count: get runtime PM usage count\n");
seq_puts(s, "reques_resume: do async runtime PM resume\n");
seq_puts(s, "resume: do sync runtime PM resume\n");
seq_puts(s, "get: do runtime PM get\n");
seq_puts(s, "get_noresume: do runtime PM get noresume\n");
seq_puts(s, "put_noidle: do runtime PM put noidle\n");
seq_puts(s, "put_autosuspend: do runtime PM put autosuspend\n");
seq_puts(s, "mark_last_busy: do runtime PM mark last busy\n");
seq_puts(s, "resume_bus: do bus resume only\n");
seq_puts(s, "suspend_bus: do bus suspend only\n");
return 0;
}
@ -555,6 +591,8 @@ static ssize_t cnss_control_params_debug_write(struct file *fp,
plat_priv->ctrl_params.quirks = val;
else if (strcmp(cmd, "mhi_timeout") == 0)
plat_priv->ctrl_params.mhi_timeout = val;
else if (strcmp(cmd, "mhi_m2_timeout") == 0)
plat_priv->ctrl_params.mhi_m2_timeout = val;
else if (strcmp(cmd, "qmi_timeout") == 0)
plat_priv->ctrl_params.qmi_timeout = val;
else if (strcmp(cmd, "bdf_type") == 0)
@ -613,6 +651,12 @@ static int cnss_show_quirks_state(struct seq_file *s,
case DISABLE_DRV:
seq_puts(s, "DISABLE_DRV");
continue;
case DISABLE_IO_COHERENCY:
seq_puts(s, "DISABLE_IO_COHERENCY");
continue;
case IGNORE_PCI_LINK_FAILURE:
seq_puts(s, "IGNORE_PCI_LINK_FAILURE");
continue;
}
seq_printf(s, "UNKNOWN-%d", i);
@ -636,6 +680,8 @@ static int cnss_control_params_debug_show(struct seq_file *s, void *data)
seq_puts(s, "\nCurrent value:\n");
cnss_show_quirks_state(s, cnss_priv);
seq_printf(s, "mhi_timeout: %u\n", cnss_priv->ctrl_params.mhi_timeout);
seq_printf(s, "mhi_m2_timeout: %u\n",
cnss_priv->ctrl_params.mhi_m2_timeout);
seq_printf(s, "qmi_timeout: %u\n", cnss_priv->ctrl_params.qmi_timeout);
seq_printf(s, "bdf_type: %u\n", cnss_priv->ctrl_params.bdf_type);
seq_printf(s, "time_sync_period: %u\n",

14
drivers/net/wireless/cnss2/genl.c
View file

@ -5,6 +5,7 @@
#include <linux/err.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <net/netlink.h>
#include <net/genetlink.h>
@ -161,6 +162,7 @@ int cnss_genl_send_msg(void *buff, u8 type, char *file_name, u32 total_size)
u32 seg_id = 0;
u32 data_len = 0;
u8 end = 0;
u8 retry;
cnss_pr_dbg("type: %u, total_size: %x\n", type, total_size);
@ -171,8 +173,16 @@ int cnss_genl_send_msg(void *buff, u8 type, char *file_name, u32 total_size)
data_len = remaining;
end = 1;
}
ret = cnss_genl_send_data(type, file_name, total_size,
seg_id, end, data_len, msg_buff);
for (retry = 0; retry < 2; retry++) {
ret = cnss_genl_send_data(type, file_name, total_size,
seg_id, end, data_len,
msg_buff);
if (ret >= 0)
break;
msleep(100);
}
if (ret < 0) {
cnss_pr_err("fail to send genl data, ret %d\n", ret);
return ret;

199
drivers/net/wireless/cnss2/main.c
View file

@ -7,9 +7,11 @@
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pm_wakeup.h>
#include <linux/reboot.h>
#include <linux/rwsem.h>
#include <linux/suspend.h>
#include <linux/timer.h>
#include <soc/qcom/minidump.h>
#include <soc/qcom/ramdump.h>
#include <soc/qcom/subsystem_notif.h>
@ -29,13 +31,15 @@
#define FW_READY_TIMEOUT 20000
#define FW_ASSERT_TIMEOUT 5000
#define CNSS_EVENT_PENDING 2989
#define COLD_BOOT_CAL_SHUTDOWN_DELAY_MS 50
#define CNSS_QUIRKS_DEFAULT 0
#define CNSS_QUIRKS_DEFAULT BIT(DISABLE_IO_COHERENCY)
#ifdef CONFIG_CNSS_EMULATION
#define CNSS_MHI_TIMEOUT_DEFAULT 90000
#else
#define CNSS_MHI_TIMEOUT_DEFAULT 0
#endif
#define CNSS_MHI_M2_TIMEOUT_DEFAULT 25
#define CNSS_QMI_TIMEOUT_DEFAULT 10000
#define CNSS_BDF_TYPE_DEFAULT CNSS_BDF_ELF
#define CNSS_TIME_SYNC_PERIOD_DEFAULT 900000
@ -283,6 +287,7 @@ EXPORT_SYMBOL(cnss_wlan_enable);
int cnss_wlan_disable(struct device *dev, enum cnss_driver_mode mode)
{
struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
int ret = 0;
if (plat_priv->device_id == QCA6174_DEVICE_ID)
return 0;
@ -290,7 +295,10 @@ int cnss_wlan_disable(struct device *dev, enum cnss_driver_mode mode)
if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
return 0;
return cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
cnss_bus_free_qdss_mem(plat_priv);
return ret;
}
EXPORT_SYMBOL(cnss_wlan_disable);
@ -1063,6 +1071,12 @@ static int cnss_driver_recovery_hdlr(struct cnss_plat_data *plat_priv,
goto out;
}
if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
cnss_pr_err("Reboot is in progress, ignore recovery\n");
ret = -EINVAL;
goto out;
}
if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
cnss_pr_err("Recovery is already in progress\n");
ret = -EINVAL;
@ -1153,7 +1167,7 @@ int cnss_force_fw_assert(struct device *dev)
return -EOPNOTSUPP;
}
if (cnss_pci_is_device_down(dev)) {
if (cnss_bus_is_device_down(plat_priv)) {
cnss_pr_info("Device is already in bad state, ignore force assert\n");
return 0;
}
@ -1189,7 +1203,7 @@ int cnss_force_collect_rddm(struct device *dev)
return -EOPNOTSUPP;
}
if (cnss_pci_is_device_down(dev)) {
if (cnss_bus_is_device_down(plat_priv)) {
cnss_pr_info("Device is already in bad state, ignore force collect rddm\n");
return 0;
}
@ -1222,6 +1236,54 @@ int cnss_force_collect_rddm(struct device *dev)
}
EXPORT_SYMBOL(cnss_force_collect_rddm);
int cnss_qmi_send_get(struct device *dev)
{
struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
return 0;
return cnss_bus_qmi_send_get(plat_priv);
}
EXPORT_SYMBOL(cnss_qmi_send_get);
int cnss_qmi_send_put(struct device *dev)
{
struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
return 0;
return cnss_bus_qmi_send_put(plat_priv);
}
EXPORT_SYMBOL(cnss_qmi_send_put);
int cnss_qmi_send(struct device *dev, int type, void *cmd,
int cmd_len, void *cb_ctx,
int (*cb)(void *ctx, void *event, int event_len))
{
struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
int ret;
if (!plat_priv)
return -ENODEV;
if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
return -EINVAL;
plat_priv->get_info_cb = cb;
plat_priv->get_info_cb_ctx = cb_ctx;
ret = cnss_wlfw_get_info_send_sync(plat_priv, type, cmd, cmd_len);
if (ret) {
plat_priv->get_info_cb = NULL;
plat_priv->get_info_cb_ctx = NULL;
}
return ret;
}
EXPORT_SYMBOL(cnss_qmi_send);
static int cnss_cold_boot_cal_start_hdlr(struct cnss_plat_data *plat_priv)
{
int ret = 0;
@ -1268,8 +1330,10 @@ static int cnss_cold_boot_cal_done_hdlr(struct cnss_plat_data *plat_priv,
}
cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
cnss_bus_free_qdss_mem(plat_priv);
cnss_release_antenna_sharing(plat_priv);
cnss_bus_dev_shutdown(plat_priv);
msleep(COLD_BOOT_CAL_SHUTDOWN_DELAY_MS);
complete(&plat_priv->cal_complete);
clear_bit(CNSS_COLD_BOOT_CAL, &plat_priv->driver_state);
@ -1516,6 +1580,25 @@ static void cnss_driver_event_work(struct work_struct *work)
cnss_pm_relax(plat_priv);
}
int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
phys_addr_t *pa, unsigned long attrs)
{
struct sg_table sgt;
int ret;
ret = dma_get_sgtable_attrs(dev, &sgt, va, dma, size, attrs);
if (ret) {
cnss_pr_err("Failed to get sgtable for va: 0x%pK, dma: %pa, size: 0x%zx, attrs: 0x%x\n",
va, &dma, size, attrs);
return -EINVAL;
}
*pa = page_to_phys(sg_page(sgt.sgl));
sg_free_table(&sgt);
return 0;
}
int cnss_register_subsys(struct cnss_plat_data *plat_priv)
{
int ret = 0;
@ -1766,6 +1849,87 @@ void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
}
}
int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
enum cnss_fw_dump_type type, int seg_no,
void *va, phys_addr_t pa, size_t size)
{
struct md_region md_entry;
int ret;
switch (type) {
case CNSS_FW_IMAGE:
snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
seg_no);
break;
case CNSS_FW_RDDM:
snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
seg_no);
break;
case CNSS_FW_REMOTE_HEAP:
snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
seg_no);
break;
default:
cnss_pr_err("Unknown dump type ID: %d\n", type);
return -EINVAL;
}
md_entry.phys_addr = pa;
md_entry.virt_addr = (uintptr_t)va;
md_entry.size = size;
md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
cnss_pr_dbg("Mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
md_entry.name, va, &pa, size);
ret = msm_minidump_add_region(&md_entry);
if (ret)
cnss_pr_err("Failed to add mini dump region, err = %d\n", ret);
return ret;
}
int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
enum cnss_fw_dump_type type, int seg_no,
void *va, phys_addr_t pa, size_t size)
{
struct md_region md_entry;
int ret;
switch (type) {
case CNSS_FW_IMAGE:
snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
seg_no);
break;
case CNSS_FW_RDDM:
snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
seg_no);
break;
case CNSS_FW_REMOTE_HEAP:
snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
seg_no);
break;
default:
cnss_pr_err("Unknown dump type ID: %d\n", type);
return -EINVAL;
}
md_entry.phys_addr = pa;
md_entry.virt_addr = (uintptr_t)va;
md_entry.size = size;
md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
cnss_pr_dbg("Remove mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
md_entry.name, va, &pa, size);
ret = msm_minidump_remove_region(&md_entry);
if (ret)
cnss_pr_err("Failed to remove mini dump region, err = %d\n",
ret);
return ret;
}
static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
{
int ret = 0;
@ -1835,7 +1999,7 @@ static ssize_t fs_ready_store(struct device *dev,
if (fs_ready == FILE_SYSTEM_READY) {
cnss_driver_event_post(plat_priv,
CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
CNSS_EVENT_SYNC, NULL);
0, NULL);
}
return count;
@ -1884,6 +2048,19 @@ static void cnss_event_work_deinit(struct cnss_plat_data *plat_priv)
destroy_workqueue(plat_priv->event_wq);
}
static int cnss_reboot_notifier(struct notifier_block *nb,
unsigned long action,
void *data)
{
struct cnss_plat_data *plat_priv =
container_of(nb, struct cnss_plat_data, reboot_nb);
set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
cnss_pr_dbg("Reboot is in progress with action %d\n", action);
return NOTIFY_DONE;
}
static int cnss_misc_init(struct cnss_plat_data *plat_priv)
{
int ret;
@ -1891,7 +2068,15 @@ static int cnss_misc_init(struct cnss_plat_data *plat_priv)
timer_setup(&plat_priv->fw_boot_timer,
cnss_bus_fw_boot_timeout_hdlr, 0);
register_pm_notifier(&cnss_pm_notifier);
ret = register_pm_notifier(&cnss_pm_notifier);
if (ret)
cnss_pr_err("Failed to register PM notifier, err = %d\n", ret);
plat_priv->reboot_nb.notifier_call = cnss_reboot_notifier;
ret = register_reboot_notifier(&plat_priv->reboot_nb);
if (ret)
cnss_pr_err("Failed to register reboot notifier, err = %d\n",
ret);
ret = device_init_wakeup(&plat_priv->plat_dev->dev, true);
if (ret)
@ -1914,6 +2099,7 @@ static void cnss_misc_deinit(struct cnss_plat_data *plat_priv)
complete_all(&plat_priv->cal_complete);
complete_all(&plat_priv->power_up_complete);
device_init_wakeup(&plat_priv->plat_dev->dev, false);
unregister_reboot_notifier(&plat_priv->reboot_nb);
unregister_pm_notifier(&cnss_pm_notifier);
del_timer(&plat_priv->fw_boot_timer);
}
@ -1922,6 +2108,7 @@ static void cnss_init_control_params(struct cnss_plat_data *plat_priv)
{
plat_priv->ctrl_params.quirks = CNSS_QUIRKS_DEFAULT;
plat_priv->ctrl_params.mhi_timeout = CNSS_MHI_TIMEOUT_DEFAULT;
plat_priv->ctrl_params.mhi_m2_timeout = CNSS_MHI_M2_TIMEOUT_DEFAULT;
plat_priv->ctrl_params.qmi_timeout = CNSS_QMI_TIMEOUT_DEFAULT;
plat_priv->ctrl_params.bdf_type = CNSS_BDF_TYPE_DEFAULT;
plat_priv->ctrl_params.time_sync_period = CNSS_TIME_SYNC_PERIOD_DEFAULT;

18
drivers/net/wireless/cnss2/main.h
View file

@ -18,6 +18,7 @@
#define MAX_NO_OF_MAC_ADDR 4
#define QMI_WLFW_MAX_TIMESTAMP_LEN 32
#define QMI_WLFW_MAX_NUM_MEM_SEG 32
#define QMI_WLFW_MAX_BUILD_ID_LEN 128
#define CNSS_RDDM_TIMEOUT_MS 20000
#define RECOVERY_TIMEOUT 60000
#define TIME_CLOCK_FREQ_HZ 19200000
@ -133,6 +134,7 @@ struct cnss_fw_mem {
phys_addr_t pa;
u8 valid;
u32 type;
unsigned long attrs;
};
struct wlfw_rf_chip_info {
@ -207,6 +209,7 @@ enum cnss_driver_state {
CNSS_COEX_CONNECTED,
CNSS_IMS_CONNECTED,
CNSS_IN_SUSPEND_RESUME,
CNSS_IN_REBOOT,
};
struct cnss_recovery_data {
@ -243,6 +246,8 @@ enum cnss_debug_quirks {
FBC_BYPASS,
ENABLE_DAEMON_SUPPORT,
DISABLE_DRV,
DISABLE_IO_COHERENCY,
IGNORE_PCI_LINK_FAILURE,
};
enum cnss_bdf_type {
@ -264,6 +269,7 @@ struct cnss_cal_info {
struct cnss_control_params {
unsigned long quirks;
unsigned int mhi_timeout;
unsigned int mhi_m2_timeout;
unsigned int qmi_timeout;
unsigned int bdf_type;
unsigned int time_sync_period;
@ -307,6 +313,7 @@ struct cnss_plat_data {
struct cnss_esoc_info esoc_info;
struct cnss_bus_bw_info bus_bw_info;
struct notifier_block modem_nb;
struct notifier_block reboot_nb;
struct cnss_platform_cap cap;
struct pm_qos_request qos_request;
struct cnss_device_version device_version;
@ -323,6 +330,7 @@ struct cnss_plat_data {
struct wlfw_rf_board_info board_info;
struct wlfw_soc_info soc_info;
struct wlfw_fw_version_info fw_version_info;
char fw_build_id[QMI_WLFW_MAX_BUILD_ID_LEN + 1];
u32 otp_version;
u32 fw_mem_seg_len;
struct cnss_fw_mem fw_mem[QMI_WLFW_MAX_NUM_MEM_SEG];
@ -355,6 +363,8 @@ struct cnss_plat_data {
struct qmi_handle ims_qmi;
struct qmi_txn txn;
u64 dynamic_feature;
void *get_info_cb_ctx;
int (*get_info_cb)(void *ctx, void *event, int event_len);
};
#ifdef CONFIG_ARCH_QCOM
@ -404,5 +414,13 @@ void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv);
void cnss_set_pin_connect_status(struct cnss_plat_data *plat_priv);
int cnss_get_cpr_info(struct cnss_plat_data *plat_priv);
int cnss_update_cpr_info(struct cnss_plat_data *plat_priv);
int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
phys_addr_t *pa, unsigned long attrs);
int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
enum cnss_fw_dump_type type, int seg_no,
void *va, phys_addr_t pa, size_t size);
int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
enum cnss_fw_dump_type type, int seg_no,
void *va, phys_addr_t pa, size_t size);
#endif /* _CNSS_MAIN_H */

1471
drivers/net/wireless/cnss2/pci.c
View file

File diff suppressed because it is too large Load diff

25
drivers/net/wireless/cnss2/pci.h
View file

@ -16,6 +16,7 @@ enum cnss_mhi_state {
CNSS_MHI_INIT,
CNSS_MHI_DEINIT,
CNSS_MHI_POWER_ON,
CNSS_MHI_POWERING_OFF,
CNSS_MHI_POWER_OFF,
CNSS_MHI_FORCE_POWER_OFF,
CNSS_MHI_SUSPEND,
@ -53,6 +54,12 @@ struct cnss_pci_debug_reg {
u32 val;
};
struct cnss_misc_reg {
u8 wr;
u32 offset;
u32 val;
};
struct cnss_pci_data {
struct pci_dev *pci_dev;
struct cnss_plat_data *plat_priv;
@ -65,6 +72,8 @@ struct cnss_pci_data {
struct pci_saved_state *saved_state;
struct pci_saved_state *default_state;
struct msm_pcie_register_event msm_pci_event;
struct notifier_block pm_qos_nb;
u8 runtime_pm_prevented;
atomic_t auto_suspended;
atomic_t drv_connected;
u8 drv_connected_last;
@ -86,7 +95,14 @@ struct cnss_pci_data {
struct timer_list dev_rddm_timer;
struct delayed_work time_sync_work;
u8 disable_pc;
struct mutex bus_lock; /* mutex for suspend and resume bus */
struct cnss_pci_debug_reg *debug_reg;
struct cnss_misc_reg *wcss_reg;
u32 wcss_reg_size;
struct cnss_misc_reg *pcie_reg;
u32 pcie_reg_size;
struct cnss_misc_reg *wlaon_reg;
u32 wlaon_reg_size;
};
static inline void cnss_set_pci_priv(struct pci_dev *pci_dev, void *data)
@ -161,6 +177,8 @@ void cnss_pci_collect_dump_info(struct cnss_pci_data *pci_priv, bool in_panic);
void cnss_pci_clear_dump_info(struct cnss_pci_data *pci_priv);
u32 cnss_pci_get_wake_msi(struct cnss_pci_data *pci_priv);
int cnss_pci_force_fw_assert_hdlr(struct cnss_pci_data *pci_priv);
int cnss_pci_qmi_send_get(struct cnss_pci_data *pci_priv);
int cnss_pci_qmi_send_put(struct cnss_pci_data *pci_priv);
void cnss_pci_fw_boot_timeout_hdlr(struct cnss_pci_data *pci_priv);
int cnss_pci_call_driver_probe(struct cnss_pci_data *pci_priv);
int cnss_pci_call_driver_remove(struct cnss_pci_data *pci_priv);
@ -183,5 +201,12 @@ void cnss_pci_pm_runtime_put_noidle(struct cnss_pci_data *pci_priv);
void cnss_pci_pm_runtime_mark_last_busy(struct cnss_pci_data *pci_priv);
int cnss_pci_update_status(struct cnss_pci_data *pci_priv,
enum cnss_driver_status status);
int cnss_pcie_is_device_down(struct cnss_pci_data *pci_priv);
int cnss_pci_suspend_bus(struct cnss_pci_data *pci_priv);
int cnss_pci_resume_bus(struct cnss_pci_data *pci_priv);
int cnss_pci_debug_reg_read(struct cnss_pci_data *pci_priv, u32 offset,
u32 *val);
int cnss_pci_debug_reg_write(struct cnss_pci_data *pci_priv, u32 offset,
u32 val);
#endif /* _CNSS_PCI_H */

221
drivers/net/wireless/cnss2/qmi.c
View file

@ -92,6 +92,8 @@ static int cnss_wlfw_ind_register_send_sync(struct cnss_plat_data *plat_priv)
req->qdss_trace_save_enable = 1;
req->qdss_trace_free_enable_valid = 1;
req->qdss_trace_free_enable = 1;
req->respond_get_info_enable_valid = 1;
req->respond_get_info_enable = 1;
ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
wlfw_ind_register_resp_msg_v01_ei, resp);
@ -399,6 +401,9 @@ int cnss_wlfw_tgt_cap_send_sync(struct cnss_plat_data *plat_priv)
resp->fw_version_info.fw_build_timestamp,
QMI_WLFW_MAX_TIMESTAMP_LEN + 1);
}
if (resp->fw_build_id_valid)
strlcpy(plat_priv->fw_build_id, resp->fw_build_id,
QMI_WLFW_MAX_BUILD_ID_LEN + 1);
if (resp->voltage_mv_valid) {
plat_priv->cpr_info.voltage = resp->voltage_mv;
cnss_pr_dbg("Voltage for CPR: %dmV\n",
@ -413,12 +418,13 @@ int cnss_wlfw_tgt_cap_send_sync(struct cnss_plat_data *plat_priv)
if (resp->otp_version_valid)
plat_priv->otp_version = resp->otp_version;
cnss_pr_dbg("Target capability: chip_id: 0x%x, chip_family: 0x%x, board_id: 0x%x, soc_id: 0x%x, fw_version: 0x%x, fw_build_timestamp: %s, otp_version: 0x%x\n",
cnss_pr_dbg("Target capability: chip_id: 0x%x, chip_family: 0x%x, board_id: 0x%x, soc_id: 0x%x, fw_version: 0x%x, fw_build_timestamp: %s, fw_build_id: %s, otp_version: 0x%x\n",
plat_priv->chip_info.chip_id,
plat_priv->chip_info.chip_family,
plat_priv->board_info.board_id, plat_priv->soc_info.soc_id,
plat_priv->fw_version_info.fw_version,
plat_priv->fw_version_info.fw_build_timestamp,
plat_priv->fw_build_id,
plat_priv->otp_version);
kfree(req);
@ -432,6 +438,56 @@ out:
return ret;
}
static int cnss_get_bdf_file_name(struct cnss_plat_data *plat_priv,
u32 bdf_type, char *filename,
u32 filename_len)
{
int ret = 0;
switch (bdf_type) {
case CNSS_BDF_ELF:
if (plat_priv->board_info.board_id == 0xFF)
snprintf(filename, filename_len, ELF_BDF_FILE_NAME);
else if (plat_priv->board_info.board_id < 0xFF)
snprintf(filename, filename_len,
ELF_BDF_FILE_NAME_PREFIX "%02x",
plat_priv->board_info.board_id);
else
snprintf(filename, filename_len,
BDF_FILE_NAME_PREFIX "%02x.e%02x",
plat_priv->board_info.board_id >> 8 & 0xFF,
plat_priv->board_info.board_id & 0xFF);
break;
case CNSS_BDF_BIN:
if (plat_priv->board_info.board_id == 0xFF)
snprintf(filename, filename_len, BIN_BDF_FILE_NAME);
else if (plat_priv->board_info.board_id < 0xFF)
snprintf(filename, filename_len,
BIN_BDF_FILE_NAME_PREFIX "%02x",
plat_priv->board_info.board_id);
else
snprintf(filename, filename_len,
BDF_FILE_NAME_PREFIX "%02x.b%02x",
plat_priv->board_info.board_id >> 8 & 0xFF,
plat_priv->board_info.board_id & 0xFF);
break;
case CNSS_BDF_REGDB:
snprintf(filename, filename_len, REGDB_FILE_NAME);
break;
case CNSS_BDF_DUMMY:
cnss_pr_dbg("CNSS_BDF_DUMMY is set, sending dummy BDF\n");
snprintf(filename, filename_len, DUMMY_BDF_FILE_NAME);
ret = MAX_BDF_FILE_NAME;
break;
default:
cnss_pr_err("Invalid BDF type: %d\n",
plat_priv->ctrl_params.bdf_type);
ret = -EINVAL;
break;
}
return ret;
}
int cnss_wlfw_bdf_dnld_send_sync(struct cnss_plat_data *plat_priv,
u32 bdf_type)
{
@ -439,7 +495,7 @@ int cnss_wlfw_bdf_dnld_send_sync(struct cnss_plat_data *plat_priv,
struct wlfw_bdf_download_resp_msg_v01 *resp;
struct qmi_txn txn;
char filename[MAX_BDF_FILE_NAME];
const struct firmware *fw_entry;
const struct firmware *fw_entry = NULL;
const u8 *temp;
unsigned int remaining;
int ret = 0;
@ -457,46 +513,13 @@ int cnss_wlfw_bdf_dnld_send_sync(struct cnss_plat_data *plat_priv,
return -ENOMEM;
}
switch (bdf_type) {
case CNSS_BDF_ELF:
if (plat_priv->board_info.board_id == 0xFF)
snprintf(filename, sizeof(filename), ELF_BDF_FILE_NAME);
else if (plat_priv->board_info.board_id < 0xFF)
snprintf(filename, sizeof(filename),
ELF_BDF_FILE_NAME_PREFIX "%02x",
plat_priv->board_info.board_id);
else
snprintf(filename, sizeof(filename),
BDF_FILE_NAME_PREFIX "%02x.e%02x",
plat_priv->board_info.board_id >> 8 & 0xFF,
plat_priv->board_info.board_id & 0xFF);
break;
case CNSS_BDF_BIN:
if (plat_priv->board_info.board_id == 0xFF)
snprintf(filename, sizeof(filename), BIN_BDF_FILE_NAME);
else if (plat_priv->board_info.board_id < 0xFF)
snprintf(filename, sizeof(filename),
BIN_BDF_FILE_NAME_PREFIX "%02x",
plat_priv->board_info.board_id);
else
snprintf(filename, sizeof(filename),
BDF_FILE_NAME_PREFIX "%02x.b%02x",
plat_priv->board_info.board_id >> 8 & 0xFF,
plat_priv->board_info.board_id & 0xFF);
break;
case CNSS_BDF_REGDB:
snprintf(filename, sizeof(filename), REGDB_FILE_NAME);
break;
case CNSS_BDF_DUMMY:
cnss_pr_dbg("CNSS_BDF_DUMMY is set, sending dummy BDF\n");
snprintf(filename, sizeof(filename), DUMMY_BDF_FILE_NAME);
ret = cnss_get_bdf_file_name(plat_priv, bdf_type,
filename, sizeof(filename));
if (ret > 0) {
temp = DUMMY_BDF_FILE_NAME;
remaining = MAX_BDF_FILE_NAME;
goto bypass_bdf;
default:
cnss_pr_err("Invalid BDF type: %d\n",
plat_priv->ctrl_params.bdf_type);
ret = -EINVAL;
} else if (ret < 0) {
goto err_req_fw;
}
@ -522,7 +545,7 @@ bypass_bdf:
req->data_valid = 1;
req->end_valid = 1;
req->bdf_type_valid = 1;
req->bdf_type = plat_priv->ctrl_params.bdf_type;
req->bdf_type = bdf_type;
if (remaining > QMI_WLFW_MAX_DATA_SIZE_V01) {
req->data_len = QMI_WLFW_MAX_DATA_SIZE_V01;
@ -572,12 +595,15 @@ bypass_bdf:
req->seg_id++;
}
if (bdf_type != CNSS_BDF_DUMMY)
release_firmware(fw_entry);
kfree(req);
kfree(resp);
return 0;
err_send:
if (plat_priv->ctrl_params.bdf_type != CNSS_BDF_DUMMY)
if (bdf_type != CNSS_BDF_DUMMY)
release_firmware(fw_entry);
err_req_fw:
if (bdf_type != CNSS_BDF_REGDB)
@ -758,12 +784,12 @@ int cnss_wlfw_wlan_cfg_send_sync(struct cnss_plat_data *plat_priv,
u32 i;
int ret = 0;
cnss_pr_dbg("Sending WLAN config message, state: 0x%lx\n",
plat_priv->driver_state);
if (!plat_priv)
return -ENODEV;
cnss_pr_dbg("Sending WLAN config message, state: 0x%lx\n",
plat_priv->driver_state);
req = kzalloc(sizeof(*req), GFP_KERNEL);
if (!req)
return -ENOMEM;
@ -1441,6 +1467,77 @@ out:
return ret;
}
int cnss_wlfw_get_info_send_sync(struct cnss_plat_data *plat_priv, int type,
void *cmd, int cmd_len)
{
struct wlfw_get_info_req_msg_v01 *req;
struct wlfw_get_info_resp_msg_v01 *resp;
struct qmi_txn txn;
int ret = 0;
cnss_pr_vdbg("Sending get info message, type: %d, cmd length: %d, state: 0x%lx\n",
type, cmd_len, plat_priv->driver_state);
if (cmd_len > QMI_WLFW_MAX_DATA_SIZE_V01)
return -EINVAL;
req = kzalloc(sizeof(*req), GFP_KERNEL);
if (!req)
return -ENOMEM;
resp = kzalloc(sizeof(*resp), GFP_KERNEL);
if (!resp) {
kfree(req);
return -ENOMEM;
}
req->type = type;
req->data_len = cmd_len;
memcpy(req->data, cmd, req->data_len);
ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
wlfw_get_info_resp_msg_v01_ei, resp);
if (ret < 0) {
cnss_pr_err("Failed to initialize txn for get info request, err: %d\n",
ret);
goto out;
}
ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
QMI_WLFW_GET_INFO_REQ_V01,
WLFW_GET_INFO_REQ_MSG_V01_MAX_MSG_LEN,
wlfw_get_info_req_msg_v01_ei, req);
if (ret < 0) {
qmi_txn_cancel(&txn);
cnss_pr_err("Failed to send get info request, err: %d\n",
ret);
goto out;
}
ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
if (ret < 0) {
cnss_pr_err("Failed to wait for response of get info request, err: %d\n",
ret);
goto out;
}
if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
cnss_pr_err("Get info request failed, result: %d, err: %d\n",
resp->resp.result, resp->resp.error);
ret = -resp->resp.result;
goto out;
}
kfree(req);
kfree(resp);
return 0;
out:
kfree(req);
kfree(resp);
return ret;
}
unsigned int cnss_get_qmi_timeout(struct cnss_plat_data *plat_priv)
{
cnss_pr_dbg("QMI timeout is %u ms\n", QMI_WLFW_TIMEOUT_MS);
@ -1470,6 +1567,9 @@ static void cnss_wlfw_request_mem_ind_cb(struct qmi_handle *qmi_wlfw,
ind_msg->mem_seg[i].size, ind_msg->mem_seg[i].type);
plat_priv->fw_mem[i].type = ind_msg->mem_seg[i].type;
plat_priv->fw_mem[i].size = ind_msg->mem_seg[i].size;
if (plat_priv->fw_mem[i].type == CNSS_MEM_TYPE_DDR)
plat_priv->fw_mem[i].attrs |=
DMA_ATTR_FORCE_CONTIGUOUS;
}
cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_REQUEST_MEM,
@ -1700,6 +1800,31 @@ static void cnss_wlfw_qdss_trace_free_ind_cb(struct qmi_handle *qmi_wlfw,
0, NULL);
}
static void cnss_wlfw_respond_get_info_ind_cb(struct qmi_handle *qmi_wlfw,
struct sockaddr_qrtr *sq,
struct qmi_txn *txn,
const void *data)
{
struct cnss_plat_data *plat_priv =
container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
const struct wlfw_respond_get_info_ind_msg_v01 *ind_msg = data;
cnss_pr_vdbg("Received QMI WLFW respond get info indication\n");
if (!txn) {
cnss_pr_err("Spurious indication\n");
return;
}
cnss_pr_vdbg("Extract message with event length: %d, type: %d, is last: %d, seq no: %d\n",
ind_msg->data_len, ind_msg->type,
ind_msg->is_last, ind_msg->seq_no);
if (plat_priv->get_info_cb_ctx && plat_priv->get_info_cb)
plat_priv->get_info_cb(plat_priv->get_info_cb_ctx,
(void *)ind_msg->data,
ind_msg->data_len);
}
static struct qmi_msg_handler qmi_wlfw_msg_handlers[] = {
{
.type = QMI_INDICATION,
@ -1768,6 +1893,14 @@ static struct qmi_msg_handler qmi_wlfw_msg_handlers[] = {
sizeof(struct wlfw_qdss_trace_free_ind_msg_v01),
.fn = cnss_wlfw_qdss_trace_free_ind_cb
},
{
.type = QMI_INDICATION,
.msg_id = QMI_WLFW_RESPOND_GET_INFO_IND_V01,
.ei = wlfw_respond_get_info_ind_msg_v01_ei,
.decoded_size =
sizeof(struct wlfw_respond_get_info_ind_msg_v01),
.fn = cnss_wlfw_respond_get_info_ind_cb
},
{}
};

2
drivers/net/wireless/cnss2/qmi.h
View file

@ -59,6 +59,8 @@ int cnss_wlfw_ini_send_sync(struct cnss_plat_data *plat_priv,
int cnss_wlfw_antenna_switch_send_sync(struct cnss_plat_data *plat_priv);
int cnss_wlfw_antenna_grant_send_sync(struct cnss_plat_data *plat_priv);
int cnss_wlfw_dynamic_feature_mask_send_sync(struct cnss_plat_data *plat_priv);
int cnss_wlfw_get_info_send_sync(struct cnss_plat_data *plat_priv, int type,
void *cmd, int cmd_len);
int cnss_register_coex_service(struct cnss_plat_data *plat_priv);
void cnss_unregister_coex_service(struct cnss_plat_data *plat_priv);
int coex_antenna_switch_to_wlan_send_sync_msg(struct cnss_plat_data *plat_priv);

267
drivers/net/wireless/cnss2/reg.h Normal file
View file

@ -0,0 +1,267 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2019, The Linux Foundation. All rights reserved. */
#ifndef _CNSS_REG_H
#define _CNSS_REG_H
#define QCA6390_PCIE_REMAP_BAR_CTRL_OFFSET 0x310C
#define QCA6390_CE_SRC_RING_REG_BASE 0xA00000
#define QCA6390_CE_DST_RING_REG_BASE 0xA01000
#define QCA6390_CE_COMMON_REG_BASE 0xA18000
#define QCA6390_CE_SRC_RING_BASE_LSB_OFFSET 0x0
#define QCA6390_CE_SRC_RING_BASE_MSB_OFFSET 0x4
#define QCA6390_CE_SRC_RING_ID_OFFSET 0x8
#define QCA6390_CE_SRC_RING_MISC_OFFSET 0x10
#define QCA6390_CE_SRC_CTRL_OFFSET 0x58
#define QCA6390_CE_SRC_R0_CE_CH_SRC_IS_OFFSET 0x5C
#define QCA6390_CE_SRC_RING_HP_OFFSET 0x400
#define QCA6390_CE_SRC_RING_TP_OFFSET 0x404
#define QCA6390_CE_DEST_RING_BASE_LSB_OFFSET 0x0
#define QCA6390_CE_DEST_RING_BASE_MSB_OFFSET 0x4
#define QCA6390_CE_DEST_RING_ID_OFFSET 0x8
#define QCA6390_CE_DEST_RING_MISC_OFFSET 0x10
#define QCA6390_CE_DEST_CTRL_OFFSET 0xB0
#define QCA6390_CE_CH_DST_IS_OFFSET 0xB4
#define QCA6390_CE_CH_DEST_CTRL2_OFFSET 0xB8
#define QCA6390_CE_DEST_RING_HP_OFFSET 0x400
#define QCA6390_CE_DEST_RING_TP_OFFSET 0x404
#define QCA6390_CE_STATUS_RING_BASE_LSB_OFFSET 0x58
#define QCA6390_CE_STATUS_RING_BASE_MSB_OFFSET 0x5C
#define QCA6390_CE_STATUS_RING_ID_OFFSET 0x60
#define QCA6390_CE_STATUS_RING_MISC_OFFSET 0x68
#define QCA6390_CE_STATUS_RING_HP_OFFSET 0x408
#define QCA6390_CE_STATUS_RING_TP_OFFSET 0x40C
#define QCA6390_CE_COMMON_GXI_ERR_INTS 0x14
#define QCA6390_CE_COMMON_GXI_ERR_STATS 0x18
#define QCA6390_CE_COMMON_GXI_WDOG_STATUS 0x2C
#define QCA6390_CE_COMMON_TARGET_IE_0 0x48
#define QCA6390_CE_COMMON_TARGET_IE_1 0x4C
#define QCA6390_CE_REG_INTERVAL 0x2000
#define SHADOW_REG_COUNT 36
#define QCA6390_PCIE_SHADOW_REG_VALUE_0 0x8FC
#define QCA6390_PCIE_SHADOW_REG_VALUE_34 0x984
#define QCA6390_PCIE_SHADOW_REG_VALUE_35 0x988
#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL3 0x1F80118
#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL4 0x1F8011C
#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL5 0x1F80120
#define SHADOW_REG_INTER_COUNT 43
#define QCA6390_PCIE_SHADOW_REG_INTER_0 0x1E05000
#define QCA6390_PCIE_SHADOW_REG_HUNG 0x1E050A8
#define QDSS_APB_DEC_CSR_BASE 0x1C01000
#define QDSS_APB_DEC_CSR_ETRIRQCTRL_OFFSET 0x6C
#define QDSS_APB_DEC_CSR_PRESERVEETF_OFFSET 0x70
#define QDSS_APB_DEC_CSR_PRESERVEETR0_OFFSET 0x74
#define QDSS_APB_DEC_CSR_PRESERVEETR1_OFFSET 0x78
#define MAX_UNWINDOWED_ADDRESS 0x80000
#define WINDOW_ENABLE_BIT 0x40000000
#define WINDOW_SHIFT 19
#define WINDOW_VALUE_MASK 0x3F
#define WINDOW_START MAX_UNWINDOWED_ADDRESS
#define WINDOW_RANGE_MASK 0x7FFFF
#define QCA6390_TIME_SYNC_ENABLE 0x80000000
#define QCA6390_TIME_SYNC_CLEAR 0x0
#define QCA6390_PCIE_SOC_WDOG_DISC_BAD_DATA_LOW_CFG_SOC_PCIE_REG 0x01E04234
#define QCA6390_PCIE_SOC_WDOG_DISC_BAD_DATA_LOW_CFG_SOC_PCIE_REG_VAL 0xDEAD1234
#define QCA6390_PCIE_PCIE_WCSS_STATUS_FOR_DEBUG_LOW_PCIE_LOCAL_REG 0x01E03140
#define QCA6390_PCIE_SOC_PCIE_WRAP_INTR_MASK_SOC_PCIE_REG 0x1E04054
#define QCA6390_PCIE_SOC_PCIE_WRAP_INTR_STATUS_SOC_PCIE_REG 0x1E04058
#define QCA6390_PCIE_SOC_COMMIT_REPLAY_SOC_PCIE_REG 0x1E05090
#define QCA6390_PCIE_PCIE_PARF_LTSSM 0x01E081B0
#define QCA6390_PCIE_PCIE_PARF_PM_STTS 0x01E08024
#define QCA6390_PCIE_PCIE_PARF_PM_STTS_1 0x01E08028
#define QCA6390_PCIE_PCIE_PARF_INT_STATUS 0x01E08220
#define QCA6390_PCIE_PCIE_INT_ALL_STATUS 0x01E08224
#define QCA6390_PCIE_PCIE_INT_ALL_MASK 0x01E0822C
#define QCA6390_PCIE_PCIE_PARF_BDF_TO_SID_CFG 0x01E0AC00
#define QCA6390_PCIE_PCIE_PARF_L1SS_SLEEP_NO_MHI_ACCESS_HANDLER_RD_4 0x01E08530
#define QCA6390_PCIE_PCIE_PARF_L1SS_SLEEP_NO_MHI_ACCESS_HANDLER_RD_3 0x01E0852c
#define QCA6390_PCIE_PCIE_PARF_MHI_CLOCK_RESET_CTRL 0x01E08174
#define QCA6390_PCIE_PCIE_PARF_MHI_BASE_ADDR_LOWER 0x01E08178
#define QCA6390_PCIE_PCIE_PARF_L1SS_SLEEP_MODE_HANDLER_STATUS 0x01E084D0
#define QCA6390_PCIE_PCIE_PARF_L1SS_SLEEP_MODE_HANDLER_CFG 0x01E084d4
#define QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0x01E0ec88
#define QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_PM_LINKST_IN_L1SUB 0x01E0ec08
#define QCA6390_PCIE_PCIE_CORE_CONFIG 0x01E08640
#define QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_PM_LINKST_IN_L2 0x01E0EC04
#define QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_PM_LINKST_IN_L1 0x01E0EC0C
#define QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0x01E0EC84
#define QCA6390_PCIE_PCIE_LOCAL_REG_WCSSAON_PCIE_SR_STATUS_HIGH 0x01E030C8
#define QCA6390_PCIE_PCIE_LOCAL_REG_WCSSAON_PCIE_SR_STATUS_LOW 0x01E030CC
#define QCA6390_PCIE_PCIE_LOCAL_REG_WCSS_STATUS_FOR_DEBUG_HIGH 0x01E0313C
#define QCA6390_PCIE_PCIE_LOCAL_REG_WCSS_STATUS_FOR_DEBUG_LOW 0x01E03140
#define QCA6390_GCC_DEBUG_CLK_CTL 0x001E4025C
#define QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_PLL_MODE 0x00D00200
#define QCA6390_WCSS_WFSS_PMM_WFSS_PMM_R0_PMM_CTRL 0x00B60164
#define QCA6390_WCSS_PMM_TOP_PMU_CX_CSR 0x00B70080
#define QCA6390_WCSS_PMM_TOP_AON_INT_RAW_STAT 0x00B700E0
#define QCA6390_WCSS_PMM_TOP_AON_INT_EN 0x00B700D0
#define QCA6390_WCSS_PMM_TOP_PMU_TESTBUS_STS 0x00B70020
#define QCA6390_WCSS_PMM_TOP_PMU_TESTBUS_CTL 0x00B7001C
#define QCA6390_WCSS_PMM_TOP_TESTBUS_STS 0x00B70028
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_CFG 0x00DB0008
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_CFG_MSK 0x20
#define QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_CTL 0x00D02000
#define QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE 0x00D02004
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_SPM_STS 0x00DB000C
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_SPM_CTL 0x00DB0030
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_SPM_SLP_SEQ_ENTRY_0 0x00DB0400
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_SPM_SLP_SEQ_ENTRY_9 0x00DB0424
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS0 0x00D90380
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS1 0x00D90384
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS2 0x00D90388
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS3 0x00D9038C
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS4 0x00D90390
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS5 0x00D90394
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS6 0x00D90398
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE0 0x00D90100
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE1 0x00D90104
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE2 0x00D90108
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE3 0x00D9010C
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE4 0x00D90110
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE5 0x00D90114
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE6 0x00D90118
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING0 0x00D90500
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING1 0x00D90504
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING2 0x00D90508
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING3 0x00D9050C
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING4 0x00D90510
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING5 0x00D90514
#define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING6 0x00D90518
#define QCA6390_WCSS_CC_WCSS_UMAC_NOC_CBCR 0x00C3029C
#define QCA6390_WCSS_CC_WCSS_UMAC_AHB_CBCR 0x00C302BC
#define QCA6390_WCSS_CC_WCSS_UMAC_GDSCR 0x00C30298
#define QCA6390_WCSS_CC_WCSS_WLAN1_GDSCR 0x00C300C4
#define QCA6390_WCSS_CC_WCSS_WLAN2_GDSCR 0x00C30138
#define QCA6390_WCSS_PMM_TOP_PMM_INT_CLR 0x00B70168
#define QCA6390_WCSS_PMM_TOP_AON_INT_STICKY_EN 0x00B700D8
#define QCA6390_TLMM_GPIO_IN_OUT57 0x01839004
#define QCA6390_TLMM_GPIO_INTR_CFG57 0x01839008
#define QCA6390_TLMM_GPIO_INTR_STATUS57 0x0183900C
#define QCA6390_TLMM_GPIO_IN_OUT59 0x0183b004
#define QCA6390_TLMM_GPIO_INTR_CFG59 0x0183b008
#define QCA6390_TLMM_GPIO_INTR_STATUS59 0x0183b00C
#define QCA6390_WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2 0x00B6017C
#define QCA6390_WFSS_PMM_WFSS_PMM_R0_WLAN2_STATUS_REG2 0x00B60190
#define QCA6390_WFSS_PMM_WFSS_PMM_R0_PMM_WLAN2_CFG_REG1 0x00B6018C
#define QCA6390_WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1 0x00B60178
#define QCA6390_WFSS_PMM_WFSS_PMM_R0_WLAN2_APS_STATUS_REG1 0x00B600B0
#define QCA6390_WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG1 0x00B60044
#define QCA6390_WLAON_WCSSAON_PCIE_SR_STATUS_HI_REG 0x01F806C4
#define QCA6390_WLAON_SOC_POWER_CTRL 0x01F80000
#define QCA6390_WLAON_PCIE_PWR_CTRL_REG 0x01F806BC
#define QCA6390_WLAON_WCSSAON_PCIE_SR_STATUS_LO_REG 0x1F806C8
#define QCA6390_WLAON_WCSS_TCSR_PMM_SR_STATUS_HI_REG 0x1F806CC
#define QCA6390_WLAON_WCSS_TCSR_PMM_SR_STATUS_LO_REG 0x1F806D0
#define QCA6390_WLAON_SOC_PWR_WDG_BARK_THRSHD 0x1F80004
#define QCA6390_WLAON_SOC_PWR_WDG_BITE_THRSHD 0x1F80008
#define QCA6390_WLAON_SW_COLD_RESET 0x1F8000C
#define QCA6390_WLAON_RFA_MEM_SLP_NRET_N_OVERRIDE 0x1F8001C
#define QCA6390_WLAON_GDSC_DELAY_SETTING 0x1F80024
#define QCA6390_WLAON_GDSC_DELAY_SETTING2 0x1F80028
#define QCA6390_WLAON_WL_PWR_STATUS_REG 0x1F8002C
#define QCA6390_WLAON_WL_AON_DBG_CFG_REG 0x1F80030
#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL1 0x1F80100
#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL6 0x1F80108
#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL7 0x1F8010C
#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL3 0x1F80118
#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL4 0x1F8011C
#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL5 0x1F80120
#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL8 0x1F801F0
#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL2 0x1F801F4
#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL9 0x1F801F8
#define QCA6390_WLAON_RTC_CLK_CAL_CTRL1 0x1F80200
#define QCA6390_WLAON_RTC_CLK_CAL_CTRL2 0x1F80204
#define QCA6390_WLAON_RTC_CLK_CAL_CTRL3 0x1F80208
#define QCA6390_WLAON_RTC_CLK_CAL_CTRL4 0x1F8020C
#define QCA6390_WLAON_RTC_CLK_CAL_CTRL5 0x1F80210
#define QCA6390_WLAON_RTC_CLK_CAL_CTRL6 0x1F80214
#define QCA6390_WLAON_RTC_CLK_CAL_CTRL7 0x1F80218
#define QCA6390_WLAON_RTC_CLK_CAL_CTRL8 0x1F8021C
#define QCA6390_WLAON_RTC_CLK_CAL_CTRL9 0x1F80220
#define QCA6390_WLAON_WCSSAON_CONFIG_REG 0x1F80300
#define QCA6390_WLAON_WLAN_OEM_DEBUG_REG 0x1F80304
#define QCA6390_WLAON_WLAN_RAM_DUMP_REG 0x1F80308
#define QCA6390_WLAON_QDSS_WCSS_REG 0x1F8030C
#define QCA6390_WLAON_QDSS_WCSS_ACK 0x1F80310
#define QCA6390_WLAON_WL_CLK_CNTL_KDF_REG 0x1F80314
#define QCA6390_WLAON_WL_CLK_CNTL_PMU_HFRC_REG 0x1F80318
#define QCA6390_WLAON_QFPROM_PWR_CTRL_REG 0x1F8031C
#define QCA6390_WLAON_DLY_CONFIG 0x1F80400
#define QCA6390_WLAON_WLAON_Q6_IRQ_REG 0x1F80404
#define QCA6390_WLAON_PCIE_INTF_SW_CFG_REG 0x1F80408
#define QCA6390_WLAON_PCIE_INTF_STICKY_SW_CFG_REG 0x1F8040C
#define QCA6390_WLAON_PCIE_INTF_PHY_SW_CFG_REG 0x1F80410
#define QCA6390_WLAON_PCIE_INTF_PHY_NOCSR_SW_CFG_REG 0x1F80414
#define QCA6390_WLAON_Q6_COOKIE_BIT 0x1F80500
#define QCA6390_WLAON_WARM_SW_ENTRY 0x1F80504
#define QCA6390_WLAON_RESET_DBG_SW_ENTRY 0x1F80508
#define QCA6390_WLAON_WL_PMUNOC_CFG_REG 0x1F8050C
#define QCA6390_WLAON_RESET_CAUSE_CFG_REG 0x1F80510
#define QCA6390_WLAON_SOC_WCSSAON_WAKEUP_IRQ_7_EN_REG 0x1F80514
#define QCA6390_WLAON_DEBUG 0x1F80600
#define QCA6390_WLAON_SOC_PARAMETERS 0x1F80604
#define QCA6390_WLAON_WLPM_SIGNAL 0x1F80608
#define QCA6390_WLAON_SOC_RESET_CAUSE_REG 0x1F8060C
#define QCA6390_WLAON_WAKEUP_PCIE_SOC_REG 0x1F80610
#define QCA6390_WLAON_PBL_STACK_CANARY 0x1F80614
#define QCA6390_WLAON_MEM_TOT_NUM_GRP_REG 0x1F80618
#define QCA6390_WLAON_MEM_TOT_BANKS_IN_GRP0_REG 0x1F8061C
#define QCA6390_WLAON_MEM_TOT_BANKS_IN_GRP1_REG 0x1F80620
#define QCA6390_WLAON_MEM_TOT_BANKS_IN_GRP2_REG 0x1F80624
#define QCA6390_WLAON_MEM_TOT_BANKS_IN_GRP3_REG 0x1F80628
#define QCA6390_WLAON_MEM_TOT_SIZE_IN_GRP0_REG 0x1F8062C
#define QCA6390_WLAON_MEM_TOT_SIZE_IN_GRP1_REG 0x1F80630
#define QCA6390_WLAON_MEM_TOT_SIZE_IN_GRP2_REG 0x1F80634
#define QCA6390_WLAON_MEM_TOT_SIZE_IN_GRP3_REG 0x1F80638
#define QCA6390_WLAON_MEM_SLP_NRET_OVERRIDE_GRP0_REG 0x1F8063C
#define QCA6390_WLAON_MEM_SLP_NRET_OVERRIDE_GRP1_REG 0x1F80640
#define QCA6390_WLAON_MEM_SLP_NRET_OVERRIDE_GRP2_REG 0x1F80644
#define QCA6390_WLAON_MEM_SLP_NRET_OVERRIDE_GRP3_REG 0x1F80648
#define QCA6390_WLAON_MEM_SLP_RET_OVERRIDE_GRP0_REG 0x1F8064C
#define QCA6390_WLAON_MEM_SLP_RET_OVERRIDE_GRP1_REG 0x1F80650
#define QCA6390_WLAON_MEM_SLP_RET_OVERRIDE_GRP2_REG 0x1F80654
#define QCA6390_WLAON_MEM_SLP_RET_OVERRIDE_GRP3_REG 0x1F80658
#define QCA6390_WLAON_MEM_CNT_SEL_REG 0x1F8065C
#define QCA6390_WLAON_MEM_NO_EXTBHS_REG 0x1F80660
#define QCA6390_WLAON_MEM_DEBUG_REG 0x1F80664
#define QCA6390_WLAON_MEM_DEBUG_BUS_REG 0x1F80668
#define QCA6390_WLAON_MEM_REDUN_CFG_REG 0x1F8066C
#define QCA6390_WLAON_WL_AON_SPARE2 0x1F80670
#define QCA6390_WLAON_VSEL_CFG_FOR_WL_RET_DISABLE_REG 0x1F80680
#define QCA6390_WLAON_BTFM_WLAN_IPC_STATUS_REG 0x1F80690
#define QCA6390_WLAON_MPM_COUNTER_CHICKEN_BITS 0x1F806A0
#define QCA6390_WLAON_WLPM_CHICKEN_BITS 0x1F806A4
#define QCA6390_WLAON_PCIE_PHY_PWR_REG 0x1F806A8
#define QCA6390_WLAON_WL_CLK_CNTL_PMU_LPO2M_REG 0x1F806AC
#define QCA6390_WLAON_WL_SS_ROOT_CLK_SWITCH_REG 0x1F806B0
#define QCA6390_WLAON_POWERCTRL_PMU_REG 0x1F806B4
#define QCA6390_WLAON_POWERCTRL_MEM_REG 0x1F806B8
#define QCA6390_WLAON_SOC_PWR_PROFILE_REG 0x1F806C0
#define QCA6390_WLAON_MEM_SVS_CFG_REG 0x1F806D4
#define QCA6390_WLAON_CMN_AON_MISC_REG 0x1F806D8
#define QCA6390_WLAON_INTR_STATUS 0x1F80700
#define QCA6390_SYSPM_SYSPM_PWR_STATUS 0x1F82000
#define QCA6390_SYSPM_DBG_BTFM_AON_REG 0x1F82004
#define QCA6390_SYSPM_DBG_BUS_SEL_REG 0x1F82008
#define QCA6390_SYSPM_WCSSAON_SR_STATUS 0x1F8200C
#endif

158
drivers/net/wireless/cnss2/wlan_firmware_service_v01.c
View file

@ -703,6 +703,24 @@ struct qmi_elem_info wlfw_ind_register_req_msg_v01_ei[] = {
.offset = offsetof(struct wlfw_ind_register_req_msg_v01,
qdss_trace_free_enable),
},
{
.data_type = QMI_OPT_FLAG,
.elem_len = 1,
.elem_size = sizeof(u8),
.array_type = NO_ARRAY,
.tlv_type = 0x1F,
.offset = offsetof(struct wlfw_ind_register_req_msg_v01,
respond_get_info_enable_valid),
},
{
.data_type = QMI_UNSIGNED_1_BYTE,
.elem_len = 1,
.elem_size = sizeof(u8),
.array_type = NO_ARRAY,
.tlv_type = 0x1F,
.offset = offsetof(struct wlfw_ind_register_req_msg_v01,
respond_get_info_enable),
},
{
.data_type = QMI_EOTI,
.array_type = NO_ARRAY,
@ -3608,3 +3626,143 @@ struct qmi_elem_info wlfw_wfc_call_status_resp_msg_v01_ei[] = {
},
};
struct qmi_elem_info wlfw_get_info_req_msg_v01_ei[] = {
{
.data_type = QMI_UNSIGNED_1_BYTE,
.elem_len = 1,
.elem_size = sizeof(u8),
.array_type = NO_ARRAY,
.tlv_type = 0x01,
.offset = offsetof(struct wlfw_get_info_req_msg_v01,
type),
},
{
.data_type = QMI_DATA_LEN,
.elem_len = 1,
.elem_size = sizeof(u16),
.array_type = NO_ARRAY,
.tlv_type = 0x02,
.offset = offsetof(struct wlfw_get_info_req_msg_v01,
data_len),
},
{
.data_type = QMI_UNSIGNED_1_BYTE,
.elem_len = QMI_WLFW_MAX_DATA_SIZE_V01,
.elem_size = sizeof(u8),
.array_type = VAR_LEN_ARRAY,
.tlv_type = 0x02,
.offset = offsetof(struct wlfw_get_info_req_msg_v01,
data),
},
{
.data_type = QMI_EOTI,
.array_type = NO_ARRAY,
.tlv_type = QMI_COMMON_TLV_TYPE,
},
};
struct qmi_elem_info wlfw_get_info_resp_msg_v01_ei[] = {
{
.data_type = QMI_STRUCT,
.elem_len = 1,
.elem_size = sizeof(struct qmi_response_type_v01),
.array_type = NO_ARRAY,
.tlv_type = 0x02,
.offset = offsetof(struct wlfw_get_info_resp_msg_v01,
resp),
.ei_array = qmi_response_type_v01_ei,
},
{
.data_type = QMI_EOTI,
.array_type = NO_ARRAY,
.tlv_type = QMI_COMMON_TLV_TYPE,
},
};
struct qmi_elem_info wlfw_respond_get_info_ind_msg_v01_ei[] = {
{
.data_type = QMI_DATA_LEN,
.elem_len = 1,
.elem_size = sizeof(u16),
.array_type = NO_ARRAY,
.tlv_type = 0x01,
.offset = offsetof(struct
wlfw_respond_get_info_ind_msg_v01,
data_len),
},
{
.data_type = QMI_UNSIGNED_1_BYTE,
.elem_len = QMI_WLFW_MAX_DATA_SIZE_V01,
.elem_size = sizeof(u8),
.array_type = VAR_LEN_ARRAY,
.tlv_type = 0x01,
.offset = offsetof(struct
wlfw_respond_get_info_ind_msg_v01,
data),
},
{
.data_type = QMI_OPT_FLAG,
.elem_len = 1,
.elem_size = sizeof(u8),
.array_type = NO_ARRAY,
.tlv_type = 0x10,
.offset = offsetof(struct
wlfw_respond_get_info_ind_msg_v01,
type_valid),
},
{
.data_type = QMI_UNSIGNED_1_BYTE,
.elem_len = 1,
.elem_size = sizeof(u8),
.array_type = NO_ARRAY,
.tlv_type = 0x10,
.offset = offsetof(struct
wlfw_respond_get_info_ind_msg_v01,
type),
},
{
.data_type = QMI_OPT_FLAG,
.elem_len = 1,
.elem_size = sizeof(u8),
.array_type = NO_ARRAY,
.tlv_type = 0x11,
.offset = offsetof(struct
wlfw_respond_get_info_ind_msg_v01,
is_last_valid),
},
{
.data_type = QMI_UNSIGNED_1_BYTE,
.elem_len = 1,
.elem_size = sizeof(u8),
.array_type = NO_ARRAY,
.tlv_type = 0x11,
.offset = offsetof(struct
wlfw_respond_get_info_ind_msg_v01,
is_last),
},
{
.data_type = QMI_OPT_FLAG,
.elem_len = 1,
.elem_size = sizeof(u8),
.array_type = NO_ARRAY,
.tlv_type = 0x12,
.offset = offsetof(struct
wlfw_respond_get_info_ind_msg_v01,
seq_no_valid),
},
{
.data_type = QMI_UNSIGNED_4_BYTE,
.elem_len = 1,
.elem_size = sizeof(u32),
.array_type = NO_ARRAY,
.tlv_type = 0x12,
.offset = offsetof(struct
wlfw_respond_get_info_ind_msg_v01,
seq_no),
},
{
.data_type = QMI_EOTI,
.array_type = NO_ARRAY,
.tlv_type = QMI_COMMON_TLV_TYPE,
},
};

37
drivers/net/wireless/cnss2/wlan_firmware_service_v01.h
View file

@ -13,6 +13,7 @@
#define QMI_WLFW_BDF_DOWNLOAD_REQ_V01 0x0025
#define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037
#define QMI_WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_V01 0x0044
#define QMI_WLFW_GET_INFO_REQ_V01 0x004A
#define QMI_WLFW_INITIATE_CAL_UPDATE_IND_V01 0x002A
#define QMI_WLFW_CAL_DONE_IND_V01 0x003E
#define QMI_WLFW_WFC_CALL_STATUS_RESP_V01 0x0049
@ -23,6 +24,7 @@
#define QMI_WLFW_FW_INIT_DONE_IND_V01 0x0038
#define QMI_WLFW_ANTENNA_GRANT_RESP_V01 0x0048
#define QMI_WLFW_CAL_REPORT_REQ_V01 0x0026
#define QMI_WLFW_RESPOND_GET_INFO_IND_V01 0x004B
#define QMI_WLFW_M3_INFO_RESP_V01 0x003C
#define QMI_WLFW_CAL_UPDATE_RESP_V01 0x0029
#define QMI_WLFW_CAL_DOWNLOAD_RESP_V01 0x0027
@ -49,6 +51,7 @@
#define QMI_WLFW_ATHDIAG_WRITE_REQ_V01 0x0031
#define QMI_WLFW_WLAN_MODE_RESP_V01 0x0022
#define QMI_WLFW_RESPOND_MEM_REQ_V01 0x0036
#define QMI_WLFW_GET_INFO_RESP_V01 0x004A
#define QMI_WLFW_QDSS_TRACE_MODE_RESP_V01 0x0045
#define QMI_WLFW_PIN_CONNECT_RESULT_IND_V01 0x002C
#define QMI_WLFW_FW_READY_IND_V01 0x0021
@ -272,9 +275,11 @@ struct wlfw_ind_register_req_msg_v01 {
u8 qdss_trace_save_enable;
u8 qdss_trace_free_enable_valid;
u8 qdss_trace_free_enable;
u8 respond_get_info_enable_valid;
u8 respond_get_info_enable;
};
#define WLFW_IND_REGISTER_REQ_MSG_V01_MAX_MSG_LEN 66
#define WLFW_IND_REGISTER_REQ_MSG_V01_MAX_MSG_LEN 70
extern struct qmi_elem_info wlfw_ind_register_req_msg_v01_ei[];
struct wlfw_ind_register_resp_msg_v01 {
@ -949,4 +954,34 @@ struct wlfw_wfc_call_status_resp_msg_v01 {
#define WLFW_WFC_CALL_STATUS_RESP_MSG_V01_MAX_MSG_LEN 7
extern struct qmi_elem_info wlfw_wfc_call_status_resp_msg_v01_ei[];
struct wlfw_get_info_req_msg_v01 {
u8 type;
u32 data_len;
u8 data[QMI_WLFW_MAX_DATA_SIZE_V01];
};
#define WLFW_GET_INFO_REQ_MSG_V01_MAX_MSG_LEN 6153
extern struct qmi_elem_info wlfw_get_info_req_msg_v01_ei[];
struct wlfw_get_info_resp_msg_v01 {
struct qmi_response_type_v01 resp;
};
#define WLFW_GET_INFO_RESP_MSG_V01_MAX_MSG_LEN 7
extern struct qmi_elem_info wlfw_get_info_resp_msg_v01_ei[];
struct wlfw_respond_get_info_ind_msg_v01 {
u32 data_len;
u8 data[QMI_WLFW_MAX_DATA_SIZE_V01];
u8 type_valid;
u8 type;
u8 is_last_valid;
u8 is_last;
u8 seq_no_valid;
u32 seq_no;
};
#define WLFW_RESPOND_GET_INFO_IND_MSG_V01_MAX_MSG_LEN 6164
extern struct qmi_elem_info wlfw_respond_get_info_ind_msg_v01_ei[];
#endif

8
include/net/cnss2.h
View file

@ -166,6 +166,11 @@ extern int cnss_self_recovery(struct device *dev,
enum cnss_recovery_reason reason);
extern int cnss_force_fw_assert(struct device *dev);
extern int cnss_force_collect_rddm(struct device *dev);
extern int cnss_qmi_send_get(struct device *dev);
extern int cnss_qmi_send_put(struct device *dev);
extern int cnss_qmi_send(struct device *dev, int type, void *cmd,
int cmd_len, void *cb_ctx,
int (*cb)(void *ctx, void *event, int event_len));
extern void *cnss_get_virt_ramdump_mem(struct device *dev, unsigned long *size);
extern int cnss_get_fw_files_for_target(struct device *dev,
struct cnss_fw_files *pfw_files,
@ -185,6 +190,9 @@ extern void cnss_request_pm_qos(struct device *dev, u32 qos_val);
extern void cnss_remove_pm_qos(struct device *dev);
extern void cnss_lock_pm_sem(struct device *dev);
extern void cnss_release_pm_sem(struct device *dev);
extern void cnss_pci_lock_reg_window(struct device *dev, unsigned long *flags);
extern void cnss_pci_unlock_reg_window(struct device *dev,
unsigned long *flags);
extern int cnss_wlan_pm_control(struct device *dev, bool vote);
extern int cnss_auto_suspend(struct device *dev);
extern int cnss_auto_resume(struct device *dev);