From 8f92f027b9e88bed4ea33c0bab217ea9c531e6ae Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Mon, 28 Dec 2020 21:19:08 +0530 Subject: [PATCH] ARM: dts: msm: Add BCL and PMIC die temperature mitigation for yupik Add BCL configuration to monitor battery current, level violation and state of charge depletion configuration for YUPIK. Add PMIC die temperature mitigation for YUPIK. The mitigation will trigger at the first PMIC alarm at 95C. Change-Id: Ife55eac7de58b0450e782b1106ec73db463a4707 --- qcom/pm7325b.dtsi | 108 +++++++++++ qcom/yupik-atp.dtsi | 1 + qcom/yupik-idp.dtsi | 1 + qcom/yupik-pmic-overlay.dtsi | 6 + qcom/yupik-qrd.dtsi | 1 + qcom/yupik-thermal-overlay-qrd.dtsi | 282 ++++++++++++++++++++++++++++ qcom/yupik-thermal-overlay.dtsi | 282 ++++++++++++++++++++++++++++ 7 files changed, 681 insertions(+) create mode 100644 qcom/yupik-thermal-overlay-qrd.dtsi create mode 100644 qcom/yupik-thermal-overlay.dtsi diff --git a/qcom/pm7325b.dtsi b/qcom/pm7325b.dtsi index 0ca5f7732a39..199c1fe23be9 100644 --- a/qcom/pm7325b.dtsi +++ b/qcom/pm7325b.dtsi @@ -29,6 +29,24 @@ #interrupt-cells = <2>; }; + pm7325b_bcl: bcl@4700 { + compatible = "qcom,bcl-v5"; + reg = <0x4700 0x100>; + interrupts = <0x3 0x47 0x0 IRQ_TYPE_NONE>, + <0x3 0x47 0x1 IRQ_TYPE_NONE>, + <0x3 0x47 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-lvl0", + "bcl-lvl1", + "bcl-lvl2"; + qcom,pmic7-threshold; + #thermal-sensor-cells = <1>; + }; + + bcl_soc:bcl-soc { + compatible = "qcom,msm-bcl-soc"; + #thermal-sensor-cells = <0>; + }; + pm7250b_vib: qcom,vibrator@df00 { compatible = "qcom,qpnp-vibrator-ldo"; reg = <0xdf00>; @@ -65,4 +83,94 @@ }; }; }; + + pm7325b-ibat-lvl0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7325b_bcl 0>; + + trips { + ibat_lvl0:ibat-lvl0 { + temperature = <6000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm7325b-ibat-lvl1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7325b_bcl 1>; + + trips { + ibat_lvl1:ibat-lvl1 { + temperature = <7500>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm7325b-bcl-lvl0 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7325b_bcl 5>; + + trips { + b_bcl_lvl0: b-bcl-lvl0 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pm7325b-bcl-lvl1 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7325b_bcl 6>; + + trips { + b_bcl_lvl1: b-bcl-lvl1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pm7325b-bcl-lvl2 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7325b_bcl 7>; + + trips { + b_bcl_lvl2: b-bcl-lvl2 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + socd { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&bcl_soc>; + + trips { + socd_trip:socd-trip { + temperature = <90>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; }; diff --git a/qcom/yupik-atp.dtsi b/qcom/yupik-atp.dtsi index ad548e49cc53..22b41f6b4b60 100644 --- a/qcom/yupik-atp.dtsi +++ b/qcom/yupik-atp.dtsi @@ -3,6 +3,7 @@ #include "yupik-pmic-overlay.dtsi" #include "pm8350b.dtsi" #include "yupik-audio-overlay.dtsi" +#include "yupik-thermal-overlay-qrd.dtsi" &soc { gpio_keys { diff --git a/qcom/yupik-idp.dtsi b/qcom/yupik-idp.dtsi index 92d4c51d29d2..b68e009e7a6e 100644 --- a/qcom/yupik-idp.dtsi +++ b/qcom/yupik-idp.dtsi @@ -4,6 +4,7 @@ #include "yupik-pmic-overlay.dtsi" #include "pm7325b.dtsi" #include "yupik-audio-overlay.dtsi" +#include "yupik-thermal-overlay.dtsi" &soc { gpio_keys { diff --git a/qcom/yupik-pmic-overlay.dtsi b/qcom/yupik-pmic-overlay.dtsi index 6737ee49d3a2..5cded5632a57 100644 --- a/qcom/yupik-pmic-overlay.dtsi +++ b/qcom/yupik-pmic-overlay.dtsi @@ -165,6 +165,12 @@ hysteresis = <1000>; type = "passive"; }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; }; }; diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index 2eaa1cad5480..ff6886b8f7a3 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -4,6 +4,7 @@ #include "yupik-pmic-overlay.dtsi" #include "pm8350b.dtsi" #include "yupik-audio-overlay.dtsi" +#include "yupik-thermal-overlay-qrd.dtsi" &soc { gpio_keys { diff --git a/qcom/yupik-thermal-overlay-qrd.dtsi b/qcom/yupik-thermal-overlay-qrd.dtsi new file mode 100644 index 000000000000..7c1faae42457 --- /dev/null +++ b/qcom/yupik-thermal-overlay-qrd.dtsi @@ -0,0 +1,282 @@ +#include + +&battery_charger { + #cooling-cells = <2>; +}; + +&thermal_zones { + socd { + cooling-maps { + socd_cpu4 { + trip = <&socd_trip>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + socd_cpu5 { + trip = <&socd_trip>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + socd_cpu6 { + trip = <&socd_trip>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + socd_cpu7 { + trip = <&socd_trip>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + pm8350b-bcl-lvl0 { + cooling-maps { + vbat_cpu4 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + vbat_cpu5 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + vbat_gpu0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + + vbat_cdsp0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cdsp_sw 2 2>; + }; + }; + }; + + pm8350b-bcl-lvl1 { + cooling-maps { + vbat_cpu6 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + vbat_cpu7 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu7_isolate 1 1>; + }; + + vbat_gpu1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + + vbat_cdsp1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cdsp_sw 4 4>; + }; + }; + }; + + pm8350b-bcl-lvl2 { + cooling-maps { + vbat_gpu2 { + trip = <&b_bcl_lvl2>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + vbat_cdsp2 { + trip = <&b_bcl_lvl2>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm8350c-bcl-lvl0 { + disable-thermal-zone; + cooling-maps { + vph_cpu4 { + trip = <&c_bcl_lvl0>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + vph_cpu5 { + trip = <&c_bcl_lvl0>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + vph_gpu0 { + trip = <&c_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + + vph_cdsp0 { + trip = <&c_bcl_lvl0>; + cooling-device = <&cdsp_sw 2 2>; + }; + }; + }; + + pm8350c-bcl-lvl1 { + disable-thermal-zone; + cooling-maps { + vph_cpu6 { + trip = <&c_bcl_lvl1>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + vph_cpu7 { + trip = <&c_bcl_lvl1>; + cooling-device = <&cpu7_isolate 1 1>; + }; + + vph_gpu1 { + trip = <&c_bcl_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + + vph_cdsp1 { + trip = <&c_bcl_lvl1>; + cooling-device = <&cdsp_sw 4 4>; + }; + }; + }; + + pm8350c-bcl-lvl2 { + disable-thermal-zone; + cooling-maps { + vph_gpu2 { + trip = <&c_bcl_lvl2>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + vph_cdsp2 { + trip = <&c_bcl_lvl2>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm8350b_tz { + cooling-maps { + battery_cdev { + trip = <&pm8350b_trip0>; + cooling-device = <&battery_charger + THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm7325_tz { + cooling-maps { + pm7325_gpu { + trip = <&pm7325_trip0>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pm7325_cpu1 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu1_isolate 1 1>; + }; + + pm7325_cpu2 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu2_isolate 1 1>; + }; + + pm7325_cpu3 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu3_isolate 1 1>; + }; + + pm7325_cpu4 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + pm7325_cpu5 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + pm7325_cpu6 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + pm7325_cpu7 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + pm8350c_tz { + cooling-maps { + pm8350c_gpu { + trip = <&pm8350c_trip0>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pm8350c_mdm { + trip = <&pm8350c_trip0>; + cooling-device = <&modem_tj THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pm8350c_nsp { + trip = <&pm8350c_trip0>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pmr735a_tz { + cooling-maps { + pmr735a_pa { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_pa_dsc + THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_pa_fr1 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_pa_fr1_dsc + THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_mmw0 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_mmw0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_mmw1 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_mmw1 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_mmw2 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_mmw2 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_mmw3 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_mmw3 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; +}; diff --git a/qcom/yupik-thermal-overlay.dtsi b/qcom/yupik-thermal-overlay.dtsi new file mode 100644 index 000000000000..1abb1a64ab03 --- /dev/null +++ b/qcom/yupik-thermal-overlay.dtsi @@ -0,0 +1,282 @@ +#include + +&battery_charger { + #cooling-cells = <2>; +}; + +&thermal_zones { + socd { + cooling-maps { + socd_cpu4 { + trip = <&socd_trip>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + socd_cpu5 { + trip = <&socd_trip>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + socd_cpu6 { + trip = <&socd_trip>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + socd_cpu7 { + trip = <&socd_trip>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + pm7325b-bcl-lvl0 { + cooling-maps { + vbat_cpu4 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + vbat_cpu5 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + vbat_gpu0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + + vbat_cdsp0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cdsp_sw 2 2>; + }; + }; + }; + + pm7325b-bcl-lvl1 { + cooling-maps { + vbat_cpu6 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + vbat_cpu7 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu7_isolate 1 1>; + }; + + vbat_gpu1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + + vbat_cdsp1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cdsp_sw 4 4>; + }; + }; + }; + + pm7325b-bcl-lvl2 { + cooling-maps { + vbat_gpu2 { + trip = <&b_bcl_lvl2>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + vbat_cdsp2 { + trip = <&b_bcl_lvl2>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm8350c-bcl-lvl0 { + disable-thermal-zone; + cooling-maps { + vph_cpu4 { + trip = <&c_bcl_lvl0>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + vph_cpu5 { + trip = <&c_bcl_lvl0>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + vph_gpu0 { + trip = <&c_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + + vph_cdsp0 { + trip = <&c_bcl_lvl0>; + cooling-device = <&cdsp_sw 2 2>; + }; + }; + }; + + pm8350c-bcl-lvl1 { + disable-thermal-zone; + cooling-maps { + vph_cpu6 { + trip = <&c_bcl_lvl1>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + vph_cpu7 { + trip = <&c_bcl_lvl1>; + cooling-device = <&cpu7_isolate 1 1>; + }; + + vph_gpu1 { + trip = <&c_bcl_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + + vph_cdsp1 { + trip = <&c_bcl_lvl1>; + cooling-device = <&cdsp_sw 4 4>; + }; + }; + }; + + pm8350c-bcl-lvl2 { + disable-thermal-zone; + cooling-maps { + vph_gpu2 { + trip = <&c_bcl_lvl2>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + vph_cdsp2 { + trip = <&c_bcl_lvl2>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm7325b_tz { + cooling-maps { + battery_cdev { + trip = <&pm7325b_trip0>; + cooling-device = <&battery_charger + THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm7325_tz { + cooling-maps { + pm7325_gpu { + trip = <&pm7325_trip0>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pm7325_cpu1 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu1_isolate 1 1>; + }; + + pm7325_cpu2 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu2_isolate 1 1>; + }; + + pm7325_cpu3 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu3_isolate 1 1>; + }; + + pm7325_cpu4 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + pm7325_cpu5 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + pm7325_cpu6 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + pm7325_cpu7 { + trip = <&pm7325_trip0>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + pm8350c_tz { + cooling-maps { + pm8350c_gpu { + trip = <&pm8350c_trip0>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pm8350c_mdm { + trip = <&pm8350c_trip0>; + cooling-device = <&modem_tj THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pm8350c_nsp { + trip = <&pm8350c_trip0>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pmr735a_tz { + cooling-maps { + pmr735a_pa { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_pa_dsc + THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_pa_fr1 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_pa_fr1_dsc + THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_mmw0 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_mmw0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_mmw1 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_mmw1 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_mmw2 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_mmw2 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + pmr735a_mmw3 { + trip = <&pmr735a_trip0>; + cooling-device = <&modem_mmw3 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; +};