From 2fdbcdbeec3224d236deb2057aa8110fc1bfca84 Mon Sep 17 00:00:00 2001 From: Chandra Sai Chidipudi Date: Mon, 16 Mar 2020 14:49:16 +0530 Subject: [PATCH 1/2] ARM: dts: msm: Add ipcc test nodes for Shima Add IPCC test nodes for adsp, cdsp for Shima. This allows testing IPCC ping from APPS to these subsystems. Change-Id: I49f6218f3a932df3ab422418f221a2591ceb7a18 --- qcom/ipcc-test-shima.dtsi | 5 +++++ qcom/shima.dtsi | 1 + 2 files changed, 6 insertions(+) create mode 100644 qcom/ipcc-test-shima.dtsi diff --git a/qcom/ipcc-test-shima.dtsi b/qcom/ipcc-test-shima.dtsi new file mode 100644 index 000000000000..9809b5abf881 --- /dev/null +++ b/qcom/ipcc-test-shima.dtsi @@ -0,0 +1,5 @@ +#include "ipcc-test.dtsi" + +&soc { + /delete-node/ ipcc-self-ping-slpi; +}; diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 5d859e1cd1a2..bdbae2d1dd32 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -967,6 +967,7 @@ #include "shima-gdsc.dtsi" #include "shima-ion.dtsi" #include "shima-usb.dtsi" +#include "ipcc-test-shima.dtsi" &gcc_pcie_0_gdsc { status = "ok"; From 5866be0732276b76f8235c3b457afe32736b3a0d Mon Sep 17 00:00:00 2001 From: Chandra Sai Chidipudi Date: Thu, 12 Mar 2020 11:49:54 +0530 Subject: [PATCH 2/2] ARM: dts: msm: Add LLCC entry for Shima Add Last Level Cache Controller (LLCC) device tree node for Shima. Change-Id: I0812f5590ed48c2b1a9617aa4ae7fa6a204452ef --- qcom/shima.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index bdbae2d1dd32..e682328c6736 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -895,6 +895,13 @@ reg-names = "pshold-base", "tcsr-boot-misc-detect"; }; + cache-controller@9200000 { + compatible = "qcom,shima-llcc", "qcom,llcc-v2"; + reg = <0x9200000 0xd0000> , <0x9600000 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + cap-based-alloc-and-pwr-collapse; + }; + clk_virt: interconnect { compatible = "qcom,shima-clk_virt"; #interconnect-cells = <1>;