From 8fe95998363c8ebc001de571f0595471014604cf Mon Sep 17 00:00:00 2001
From: Amir Vajid <avajid@quicinc.com>
Date: Mon, 24 Jun 2019 13:00:02 -0700
Subject: [PATCH] dt-bindings: devfreq: add support for memory latency QoS
 voting

Add documentation for the new memory latency QoS voting device
which is supported on some chipsets.

Change-Id: I89b4242b4fd91923031447338e379d2add162038
---
 bindings/devfreq/devfreq-qcom-qoslat.txt | 37 ++++++++++++++++++++++++
 1 file changed, 37 insertions(+)
 create mode 100644 bindings/devfreq/devfreq-qcom-qoslat.txt

diff --git a/bindings/devfreq/devfreq-qcom-qoslat.txt b/bindings/devfreq/devfreq-qcom-qoslat.txt
new file mode 100644
index 000000000000..7b25bf38e7be
--- /dev/null
+++ b/bindings/devfreq/devfreq-qcom-qoslat.txt
@@ -0,0 +1,37 @@
+QCOM Devfreq memory latency QoS voting device
+
+Some Qualcomm Technologies, Inc. (QTI) chipsets have an interface to vote for
+a memory latency QoS level. The qcom,devfreq-qoslat represents a device that
+votes on this interface to request a particular memory latency QoS level.
+
+Required properties:
+- compatible:		Must be "qcom,devfreq-qoslat"
+- operating-points-v2:	A phandle to the OPP v2 table that holds the supported
+			QoS levels for the particular chipset. Currently, only
+			OPP values of 0 and 1 are supported.
+- mboxes:		A phandle to the mailbox used by this device to send
+			requests to adjust the memory latency QoS level.
+Optional properties:
+- governor:		Initial governor to use for the device.
+			Default: "powersave"
+
+Example:
+
+	qoslat_opp_table: qoslat-opp-table {
+		compatible = "operating-points-v2";
+		opp-0  {
+			opp-hz = /bits/ 64 < 0 >;
+		};
+
+		opp-1 {
+			opp-hz = /bits/ 64 < 1 >;
+		};
+	};
+
+	qcom,devfreq-qoslat {
+		compatible = "qcom,devfreq-qoslat";
+		governor = "powersave";
+		operating-points-v2 = <&qoslat_opp_table>;
+		mboxes = <&qmp_aop 0>;
+	};
+