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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/cooloney/blackfin-2.6
* 'master' of master.kernel.org:/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: (30 commits) Blackfin SMC91X ethernet supporting driver: SMC91C111 LEDs are note drived in the kernel like in uboot Blackfin SPI driver: fix bug SPI DMA incomplete transmission Blackfin SPI driver: tweak spi cleanup function to match newer kernel changes Blackfin RTC drivers: update MAINTAINERS information Blackfin serial driver: decouple PARODD and CMSPAR checking from PARENB Blackfin serial driver: actually implement the break_ctl() function Blackfin serial driver: ignore framing and parity errors Blackfin serial driver: hook up our UARTs STP bit with userspaces CMSPAR Blackfin arch: move HI/LO macros into blackfin.h and punt the rest of macros.h as it includes VDSP macros we never use Blackfin arch: redo our linker script a bit Blackfin arch: make sure we initialize our L1 Data B section properly based on the linked kernel Blackfin arch: fix bug can not wakeup from sleep via push buttons Blackfin arch: add support for Alon Bar-Lev's dynamic kernel command-line Blackfin arch: add missing gpio.h header to fix compiling in some pm configurations Blackfin arch: As Mike pointed out range goes form m..MAX_BLACKFIN_GPIO -1 Blackfin arch: fix spelling typo in output Blackfin arch: try to split up functions like this into smaller units according to LKML review Blackfin arch: add proper ENDPROC() Blackfin arch: move more of our startup code to .init so it can be freed once we are up and running Blackfin arch: unify differences between our diff head.S files -- no functional changes ...
This commit is contained in:
Linus Torvalds
commit
902233ee49
60 changed files with 1070 additions and 2049 deletions
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@ -6,7 +6,11 @@
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#ifndef _BLACKFIN_H_
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#define _BLACKFIN_H_
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#include <asm/macros.h>
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#define LO(con32) ((con32) & 0xFFFF)
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#define lo(con32) ((con32) & 0xFFFF)
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#define HI(con32) (((con32) >> 16) & 0xFFFF)
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#define hi(con32) (((con32) >> 16) & 0xFFFF)
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#include <asm/mach/blackfin.h>
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#include <asm/bfin-global.h>
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@ -332,6 +332,7 @@ struct gpio_port_s {
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unsigned short inen;
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unsigned short fer;
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unsigned short reserved;
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};
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#endif /*CONFIG_PM*/
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@ -42,6 +42,12 @@
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#if defined(ANOMALY_05000198)
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#define bfin_read8(addr) ({ unsigned char __v; \
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__asm__ __volatile__ ("NOP;\n\t" \
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"%0 = b[%1] (z);\n\t" \
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: "=d"(__v) : "a"(addr)); \
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__v; })
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#define bfin_read16(addr) ({ unsigned __v; \
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__asm__ __volatile__ ("NOP;\n\t"\
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"%0 = w[%1] (z);\n\t"\
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@ -52,6 +58,11 @@
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"%0 = [%1];\n\t"\
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: "=d"(__v) : "a"(addr)); __v; })
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#define bfin_write8(addr, val) ({ \
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__asm__ __volatile__ ("NOP;\n\t" \
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"b[%0] = %1;\n\t" \
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: : "a"(addr), "d"(val) : "memory");})
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#define bfin_write16(addr,val) ({\
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__asm__ __volatile__ ("NOP;\n\t"\
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"w[%0] = %1;\n\t"\
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@ -64,6 +75,12 @@
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#else
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#define bfin_read8(addr) ({ unsigned char __v; \
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__asm__ __volatile__ ( \
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"%0 = b[%1] (z);\n\t" \
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:"=d"(__v) : "a"(addr)); \
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__v; })
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#define bfin_read16(addr) ({ unsigned __v; \
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__asm__ __volatile__ (\
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"%0 = w[%1] (z);\n\t"\
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@ -74,6 +91,11 @@
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"%0 = [%1];\n\t"\
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: "=d"(__v) : "a"(addr)); __v; })
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#define bfin_write8(addr, val) ({ \
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__asm__ __volatile__ ( \
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"b[%0] = %1; \n\t" \
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::"a"(addr), "d"(val) : "memory");})
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#define bfin_write16(addr,val) ({\
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__asm__ __volatile__ (\
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"w[%0] = %1;\n\t"\
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@ -1,95 +0,0 @@
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/************************************************************************
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*
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* macros.h
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*
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* (c) Copyright 2001-2003 Analog Devices, Inc. All rights reserved.
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*
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************************************************************************/
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/* Defines various assembly macros. */
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#ifndef _MACROS_H
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#define _MACROS_H
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#define LO(con32) ((con32) & 0xFFFF)
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#define lo(con32) ((con32) & 0xFFFF)
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#define HI(con32) (((con32) >> 16) & 0xFFFF)
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#define hi(con32) (((con32) >> 16) & 0xFFFF)
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/*
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* Set the corresponding bits in a System Register (SR);
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* All bits set in "mask" will be set in the system register
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* specified by "sys_reg" bitset_SR(sys_reg, mask), where
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* sys_reg is the system register and mask are the bits to be set.
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*/
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#define bitset_SR(sys_reg, mask)\
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[--SP] = (R7:6);\
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r7 = sys_reg;\
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r6.l = (mask) & 0xffff;\
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r6.h = (mask) >> 16;\
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r7 = r7 | r6;\
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sys_reg = r7;\
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csync;\
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(R7:6) = [SP++]
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/*
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* Clear the corresponding bits in a System Register (SR);
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* All bits set in "mask" will be cleared in the SR
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* specified by "sys_reg" bitclr_SR(sys_reg, mask), where
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* sys_reg is the SR and mask are the bits to be cleared.
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*/
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#define bitclr_SR(sys_reg, mask)\
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[--SP] = (R7:6);\
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r7 = sys_reg;\
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r7 =~ r7;\
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r6.l = (mask) & 0xffff;\
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r6.h = (mask) >> 16;\
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r7 = r7 | r6;\
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r7 =~ r7;\
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sys_reg = r7;\
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csync;\
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(R7:6) = [SP++]
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/*
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* Set the corresponding bits in a Memory Mapped Register (MMR);
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* All bits set in "mask" will be set in the MMR specified by "mmr_reg"
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* bitset_MMR(mmr_reg, mask), where mmr_reg is the MMR and mask are
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* the bits to be set.
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*/
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#define bitset_MMR(mmr_reg, mask)\
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[--SP] = (R7:6);\
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[--SP] = P5;\
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p5.l = mmr_reg & 0xffff;\
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p5.h = mmr_reg >> 16;\
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r7 = [p5];\
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r6.l = (mask) & 0xffff;\
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r6.h = (mask) >> 16;\
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r7 = r7 | r6;\
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[p5] = r7;\
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csync;\
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p5 = [SP++];\
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(R7:6) = [SP++]
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/*
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* Clear the corresponding bits in a Memory Mapped Register (MMR);
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* All bits set in "mask" will be cleared in the MMR specified by "mmr_reg"
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* bitclr_MMRreg(mmr_reg, mask), where sys_reg is the MMR and mask are
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* the bits to be cleared.
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*/
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#define bitclr_MMR(mmr_reg, mask)\
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[--SP] = (R7:6);\
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[--SP] = P5;\
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p5.l = mmr_reg & 0xffff;\
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p5.h = mmr_reg >> 16;\
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r7 = [p5];\
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r7 =~ r7;\
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r6.l = (mask) & 0xffff;\
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r6.h = (mask) >> 16;\
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r7 = r7 | r6;\
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r7 =~ r7;\
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[p5] = r7;\
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csync;\
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p5 = [SP++];\
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(R7:6) = [SP++]
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#endif /* _MACROS_H */
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