From 9038bddcc32d9a02e8bfaf1e2955f53bb39703fe Mon Sep 17 00:00:00 2001
From: Ram Chandrasekar <rkumbako@quicinc.com>
Date: Wed, 29 Apr 2020 15:20:51 -0700
Subject: [PATCH] ARM: dts: msm: Add PMIC die temperature mitigation for
 Lahaina

Add PMIC die temperature mitigation for Lahaina. The mitigation will
trigger at the first PMIC alarm at 95C.

Change-Id: I55f1c7b0eb637e417a3baabdd8d9b245439062cb
---
 qcom/lahaina-thermal-overlay.dtsi | 132 ++++++++++++++++++++++++++++++
 1 file changed, 132 insertions(+)

diff --git a/qcom/lahaina-thermal-overlay.dtsi b/qcom/lahaina-thermal-overlay.dtsi
index 69093cf1dfb5..d5ba35cc56cb 100644
--- a/qcom/lahaina-thermal-overlay.dtsi
+++ b/qcom/lahaina-thermal-overlay.dtsi
@@ -128,4 +128,136 @@
 			};
 		};
 	};
+
+	pm8350b_tz {
+		cooling-maps {
+			battery_cdev {
+				trip = <&pm8350b_trip0>;
+				cooling-device = <&battery_charger
+							THERMAL_MAX_LIMIT
+							THERMAL_MAX_LIMIT>;
+			};
+		};
+	};
+
+	pm8350_tz {
+		cooling-maps {
+			pm8350_gpu {
+				trip = <&pm8350_trip0>;
+				cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
+							THERMAL_MAX_LIMIT>;
+			};
+
+			pm8350_cpu0_freq {
+				trip = <&pm8350_trip0>;
+				cooling-device = <&CPU0 THERMAL_MAX_LIMIT
+							THERMAL_MAX_LIMIT>;
+			};
+
+			pm8350_cpu4_freq {
+				trip = <&pm8350_trip0>;
+				cooling-device = <&CPU4 THERMAL_MAX_LIMIT
+							THERMAL_MAX_LIMIT>;
+			};
+
+			pm8350_cpu7_freq {
+				trip = <&pm8350_trip0>;
+				cooling-device = <&CPU7 THERMAL_MAX_LIMIT
+							THERMAL_MAX_LIMIT>;
+			};
+
+			pm8350_cpu1 {
+				trip = <&pm8350_trip0>;
+				cooling-device = <&cpu1_isolate 1 1>;
+			};
+
+			pm8350_cpu2 {
+				trip = <&pm8350_trip0>;
+				cooling-device = <&cpu2_isolate 1 1>;
+			};
+
+			pm8350_cpu3 {
+				trip = <&pm8350_trip0>;
+				cooling-device = <&cpu3_isolate 1 1>;
+			};
+
+			pm8350_cpu4 {
+				trip = <&pm8350_trip0>;
+				cooling-device = <&cpu4_isolate 1 1>;
+			};
+
+			pm8350_cpu5 {
+				trip = <&pm8350_trip0>;
+				cooling-device = <&cpu5_isolate 1 1>;
+			};
+
+			pm8350_cpu6 {
+				trip = <&pm8350_trip0>;
+				cooling-device = <&cpu6_isolate 1 1>;
+			};
+
+			pm8350_cpu7 {
+				trip = <&pm8350_trip0>;
+				cooling-device = <&cpu7_isolate 1 1>;
+			};
+		};
+	};
+
+	pm8350c_tz {
+		cooling-maps {
+			pm8350c_mdm {
+				trip = <&pm8350c_trip0>;
+				cooling-device = <&modem_tj THERMAL_MAX_LIMIT
+							THERMAL_MAX_LIMIT>;
+			};
+
+			pm8350c_nsp {
+				trip = <&pm8350c_trip0>;
+				cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT
+							THERMAL_MAX_LIMIT>;
+			};
+		};
+	};
+
+	pmr735a_tz {
+		cooling-maps {
+			pmr735a_pa {
+				trip = <&pmr735a_trip0>;
+				cooling-device = <&modem_pa_dsc
+							THERMAL_MAX_LIMIT
+							THERMAL_MAX_LIMIT>;
+			};
+
+			pmr735a_pa_fr1 {
+				trip = <&pmr735a_trip0>;
+				cooling-device = <&modem_pa_fr1_dsc
+							THERMAL_MAX_LIMIT
+							THERMAL_MAX_LIMIT>;
+			};
+
+			pmr735a_mmw0 {
+				trip = <&pmr735a_trip0>;
+				cooling-device = <&modem_mmw0 THERMAL_MAX_LIMIT
+							THERMAL_MAX_LIMIT>;
+			};
+
+			pmr735a_mmw1 {
+				trip = <&pmr735a_trip0>;
+				cooling-device = <&modem_mmw1 THERMAL_MAX_LIMIT
+							THERMAL_MAX_LIMIT>;
+			};
+
+			pmr735a_mmw2 {
+				trip = <&pmr735a_trip0>;
+				cooling-device = <&modem_mmw2 THERMAL_MAX_LIMIT
+							THERMAL_MAX_LIMIT>;
+			};
+
+			pmr735a_mmw3 {
+				trip = <&pmr735a_trip0>;
+				cooling-device = <&modem_mmw3 THERMAL_MAX_LIMIT
+							THERMAL_MAX_LIMIT>;
+			};
+		};
+	};
 };