mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 10:41:38 -04:00
Merge branch '4.15-rc1-clkctrl-driver' of https://github.com/t-kristo/linux-pm into clk-next
* '4.15-rc1-clkctrl-driver' of https://github.com/t-kristo/linux-pm: (28 commits) clk: ti: omap4: clkctrl data fixes for opt-clocks clk: ti: dm816: add clkctrl clock data dt-bindings: clk: add dm816 clkctrl definitions clk: ti: dm814: add clkctrl clock data dt-bindings: clk: add dm814 clkctrl definitions clk: ti: am43xx: add clkctrl clock data dt-bindings: clk: add am43xx clkctrl definitions clk: ti: am33xx: add clkctrl clock data dt-bindings: clk: add am33xx clkctrl definitions clk: ti: dra7: add clkctrl clock data dt-bindings: clk: add dra7 clkctrl definitions clk: ti: omap5: add clkctrl clock data dt-bindings: clk: add omap5 clkctrl definitions clk: ti: omap3: cleanup unnecessary clock aliases clk: ti: am43xx: cleanup unnecessary clock aliases clk: ti: am33xx: cleanup unnecessary clock aliases clk: ti: dm816x: cleanup unnecessary clock aliases clk: ti: dm814x: cleanup unnecessary clock aliases clk: ti: omap5: cleanup unnecessary clock aliases clk: ti: dra7: drop unnecessary clock aliases ...
This commit is contained in:
Stephen Boyd
commit
90552a6f93
20 changed files with 2662 additions and 1052 deletions
108
include/dt-bindings/clock/am3.h
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108
include/dt-bindings/clock/am3.h
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@ -0,0 +1,108 @@
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/*
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* Copyright 2017 Texas Instruments, Inc.
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*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
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||||
#ifndef __DT_BINDINGS_CLK_AM3_H
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#define __DT_BINDINGS_CLK_AM3_H
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#define AM3_CLKCTRL_OFFSET 0x0
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#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET)
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/* l4_per clocks */
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#define AM3_L4_PER_CLKCTRL_OFFSET 0x14
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#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET)
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#define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14)
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#define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18)
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#define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c)
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#define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24)
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#define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28)
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#define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c)
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#define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30)
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#define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34)
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#define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38)
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#define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c)
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#define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40)
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#define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44)
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#define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48)
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#define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c)
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#define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50)
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#define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60)
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#define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68)
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#define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c)
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#define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70)
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#define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74)
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#define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78)
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#define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c)
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#define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80)
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#define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84)
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#define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88)
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#define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90)
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#define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94)
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#define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0)
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#define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac)
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#define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0)
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#define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4)
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#define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc)
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#define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0)
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#define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4)
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#define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc)
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#define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4)
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#define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8)
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#define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc)
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#define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0)
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#define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8)
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#define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec)
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#define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0)
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#define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4)
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#define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8)
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#define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc)
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#define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100)
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#define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c)
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#define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110)
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#define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120)
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#define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130)
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#define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c)
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/* l4_wkup clocks */
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#define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4
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#define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET)
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#define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4)
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#define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8)
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#define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc)
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#define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14)
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#define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0)
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#define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4)
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#define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8)
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#define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc)
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#define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0)
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#define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4)
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#define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8)
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#define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4)
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/* mpu clocks */
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#define AM3_MPU_CLKCTRL_OFFSET 0x4
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#define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET)
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#define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4)
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/* l4_rtc clocks */
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#define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0)
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/* gfx_l3 clocks */
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#define AM3_GFX_L3_CLKCTRL_OFFSET 0x4
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#define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET)
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#define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4)
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/* l4_cefuse clocks */
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#define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20
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#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET)
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#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20)
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#endif
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113
include/dt-bindings/clock/am4.h
Normal file
113
include/dt-bindings/clock/am4.h
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@ -0,0 +1,113 @@
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/*
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* Copyright 2017 Texas Instruments, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
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||||
*/
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#ifndef __DT_BINDINGS_CLK_AM4_H
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#define __DT_BINDINGS_CLK_AM4_H
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#define AM4_CLKCTRL_OFFSET 0x20
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#define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET)
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/* l4_wkup clocks */
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#define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120)
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#define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
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#define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228)
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#define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230)
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#define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328)
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#define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338)
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#define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340)
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#define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348)
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#define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350)
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#define AM4_SMARTREFLEX1_CLKCTRL AM4_CLKCTRL_INDEX(0x358)
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#define AM4_CONTROL_CLKCTRL AM4_CLKCTRL_INDEX(0x360)
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#define AM4_GPIO1_CLKCTRL AM4_CLKCTRL_INDEX(0x368)
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/* mpu clocks */
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#define AM4_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
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/* gfx_l3 clocks */
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#define AM4_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
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/* l4_rtc clocks */
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#define AM4_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
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/* l4_per clocks */
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#define AM4_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
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#define AM4_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28)
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#define AM4_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30)
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#define AM4_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40)
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#define AM4_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50)
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#define AM4_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58)
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#define AM4_VPFE0_CLKCTRL AM4_CLKCTRL_INDEX(0x68)
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#define AM4_VPFE1_CLKCTRL AM4_CLKCTRL_INDEX(0x70)
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#define AM4_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78)
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#define AM4_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80)
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#define AM4_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88)
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#define AM4_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90)
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#define AM4_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0)
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#define AM4_GPMC_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
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#define AM4_MCASP0_CLKCTRL AM4_CLKCTRL_INDEX(0x238)
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#define AM4_MCASP1_CLKCTRL AM4_CLKCTRL_INDEX(0x240)
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#define AM4_MMC3_CLKCTRL AM4_CLKCTRL_INDEX(0x248)
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#define AM4_QSPI_CLKCTRL AM4_CLKCTRL_INDEX(0x258)
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#define AM4_USB_OTG_SS0_CLKCTRL AM4_CLKCTRL_INDEX(0x260)
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#define AM4_USB_OTG_SS1_CLKCTRL AM4_CLKCTRL_INDEX(0x268)
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#define AM4_PRUSS_CLKCTRL AM4_CLKCTRL_INDEX(0x320)
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#define AM4_L4_LS_CLKCTRL AM4_CLKCTRL_INDEX(0x420)
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#define AM4_D_CAN0_CLKCTRL AM4_CLKCTRL_INDEX(0x428)
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#define AM4_D_CAN1_CLKCTRL AM4_CLKCTRL_INDEX(0x430)
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#define AM4_EPWMSS0_CLKCTRL AM4_CLKCTRL_INDEX(0x438)
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#define AM4_EPWMSS1_CLKCTRL AM4_CLKCTRL_INDEX(0x440)
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#define AM4_EPWMSS2_CLKCTRL AM4_CLKCTRL_INDEX(0x448)
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#define AM4_EPWMSS3_CLKCTRL AM4_CLKCTRL_INDEX(0x450)
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#define AM4_EPWMSS4_CLKCTRL AM4_CLKCTRL_INDEX(0x458)
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#define AM4_EPWMSS5_CLKCTRL AM4_CLKCTRL_INDEX(0x460)
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#define AM4_ELM_CLKCTRL AM4_CLKCTRL_INDEX(0x468)
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#define AM4_GPIO2_CLKCTRL AM4_CLKCTRL_INDEX(0x478)
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#define AM4_GPIO3_CLKCTRL AM4_CLKCTRL_INDEX(0x480)
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#define AM4_GPIO4_CLKCTRL AM4_CLKCTRL_INDEX(0x488)
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#define AM4_GPIO5_CLKCTRL AM4_CLKCTRL_INDEX(0x490)
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#define AM4_GPIO6_CLKCTRL AM4_CLKCTRL_INDEX(0x498)
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#define AM4_HDQ1W_CLKCTRL AM4_CLKCTRL_INDEX(0x4a0)
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#define AM4_I2C2_CLKCTRL AM4_CLKCTRL_INDEX(0x4a8)
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#define AM4_I2C3_CLKCTRL AM4_CLKCTRL_INDEX(0x4b0)
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#define AM4_MAILBOX_CLKCTRL AM4_CLKCTRL_INDEX(0x4b8)
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#define AM4_MMC1_CLKCTRL AM4_CLKCTRL_INDEX(0x4c0)
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#define AM4_MMC2_CLKCTRL AM4_CLKCTRL_INDEX(0x4c8)
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#define AM4_RNG_CLKCTRL AM4_CLKCTRL_INDEX(0x4e0)
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#define AM4_SPI0_CLKCTRL AM4_CLKCTRL_INDEX(0x500)
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#define AM4_SPI1_CLKCTRL AM4_CLKCTRL_INDEX(0x508)
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#define AM4_SPI2_CLKCTRL AM4_CLKCTRL_INDEX(0x510)
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#define AM4_SPI3_CLKCTRL AM4_CLKCTRL_INDEX(0x518)
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#define AM4_SPI4_CLKCTRL AM4_CLKCTRL_INDEX(0x520)
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#define AM4_SPINLOCK_CLKCTRL AM4_CLKCTRL_INDEX(0x528)
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#define AM4_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x530)
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#define AM4_TIMER3_CLKCTRL AM4_CLKCTRL_INDEX(0x538)
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#define AM4_TIMER4_CLKCTRL AM4_CLKCTRL_INDEX(0x540)
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#define AM4_TIMER5_CLKCTRL AM4_CLKCTRL_INDEX(0x548)
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#define AM4_TIMER6_CLKCTRL AM4_CLKCTRL_INDEX(0x550)
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#define AM4_TIMER7_CLKCTRL AM4_CLKCTRL_INDEX(0x558)
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#define AM4_TIMER8_CLKCTRL AM4_CLKCTRL_INDEX(0x560)
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#define AM4_TIMER9_CLKCTRL AM4_CLKCTRL_INDEX(0x568)
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#define AM4_TIMER10_CLKCTRL AM4_CLKCTRL_INDEX(0x570)
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#define AM4_TIMER11_CLKCTRL AM4_CLKCTRL_INDEX(0x578)
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#define AM4_UART2_CLKCTRL AM4_CLKCTRL_INDEX(0x580)
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#define AM4_UART3_CLKCTRL AM4_CLKCTRL_INDEX(0x588)
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#define AM4_UART4_CLKCTRL AM4_CLKCTRL_INDEX(0x590)
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#define AM4_UART5_CLKCTRL AM4_CLKCTRL_INDEX(0x598)
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#define AM4_UART6_CLKCTRL AM4_CLKCTRL_INDEX(0x5a0)
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#define AM4_OCP2SCP0_CLKCTRL AM4_CLKCTRL_INDEX(0x5b8)
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#define AM4_OCP2SCP1_CLKCTRL AM4_CLKCTRL_INDEX(0x5c0)
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#define AM4_EMIF_CLKCTRL AM4_CLKCTRL_INDEX(0x720)
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#define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20)
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#define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20)
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#endif
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45
include/dt-bindings/clock/dm814.h
Normal file
45
include/dt-bindings/clock/dm814.h
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Copyright 2017 Texas Instruments, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLK_DM814_H
|
||||
#define __DT_BINDINGS_CLK_DM814_H
|
||||
|
||||
#define DM814_CLKCTRL_OFFSET 0x0
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||||
#define DM814_CLKCTRL_INDEX(offset) ((offset) - DM814_CLKCTRL_OFFSET)
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||||
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||||
/* default clocks */
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#define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58)
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||||
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/* alwon clocks */
|
||||
#define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150)
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||||
#define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154)
|
||||
#define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158)
|
||||
#define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c)
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||||
#define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160)
|
||||
#define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164)
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||||
#define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168)
|
||||
#define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c)
|
||||
#define DM814_MCSPI1_CLKCTRL DM814_CLKCTRL_INDEX(0x190)
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||||
#define DM814_GPMC_CLKCTRL DM814_CLKCTRL_INDEX(0x1d0)
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||||
#define DM814_CPGMAC0_CLKCTRL DM814_CLKCTRL_INDEX(0x1d4)
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||||
#define DM814_MPU_CLKCTRL DM814_CLKCTRL_INDEX(0x1dc)
|
||||
#define DM814_RTC_CLKCTRL DM814_CLKCTRL_INDEX(0x1f0)
|
||||
#define DM814_TPCC_CLKCTRL DM814_CLKCTRL_INDEX(0x1f4)
|
||||
#define DM814_TPTC0_CLKCTRL DM814_CLKCTRL_INDEX(0x1f8)
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#define DM814_TPTC1_CLKCTRL DM814_CLKCTRL_INDEX(0x1fc)
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||||
#define DM814_TPTC2_CLKCTRL DM814_CLKCTRL_INDEX(0x200)
|
||||
#define DM814_TPTC3_CLKCTRL DM814_CLKCTRL_INDEX(0x204)
|
||||
#define DM814_MMC1_CLKCTRL DM814_CLKCTRL_INDEX(0x21c)
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||||
#define DM814_MMC2_CLKCTRL DM814_CLKCTRL_INDEX(0x220)
|
||||
#define DM814_MMC3_CLKCTRL DM814_CLKCTRL_INDEX(0x224)
|
||||
|
||||
#endif
|
||||
53
include/dt-bindings/clock/dm816.h
Normal file
53
include/dt-bindings/clock/dm816.h
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Copyright 2017 Texas Instruments, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLK_DM816_H
|
||||
#define __DT_BINDINGS_CLK_DM816_H
|
||||
|
||||
#define DM816_CLKCTRL_OFFSET 0x0
|
||||
#define DM816_CLKCTRL_INDEX(offset) ((offset) - DM816_CLKCTRL_OFFSET)
|
||||
|
||||
/* default clocks */
|
||||
#define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
|
||||
|
||||
/* alwon clocks */
|
||||
#define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
|
||||
#define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
|
||||
#define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
|
||||
#define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
|
||||
#define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
|
||||
#define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
|
||||
#define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
|
||||
#define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
|
||||
#define DM816_TIMER2_CLKCTRL DM816_CLKCTRL_INDEX(0x174)
|
||||
#define DM816_TIMER3_CLKCTRL DM816_CLKCTRL_INDEX(0x178)
|
||||
#define DM816_TIMER4_CLKCTRL DM816_CLKCTRL_INDEX(0x17c)
|
||||
#define DM816_TIMER5_CLKCTRL DM816_CLKCTRL_INDEX(0x180)
|
||||
#define DM816_TIMER6_CLKCTRL DM816_CLKCTRL_INDEX(0x184)
|
||||
#define DM816_TIMER7_CLKCTRL DM816_CLKCTRL_INDEX(0x188)
|
||||
#define DM816_WD_TIMER_CLKCTRL DM816_CLKCTRL_INDEX(0x18c)
|
||||
#define DM816_MCSPI1_CLKCTRL DM816_CLKCTRL_INDEX(0x190)
|
||||
#define DM816_MAILBOX_CLKCTRL DM816_CLKCTRL_INDEX(0x194)
|
||||
#define DM816_SPINBOX_CLKCTRL DM816_CLKCTRL_INDEX(0x198)
|
||||
#define DM816_MMC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1b0)
|
||||
#define DM816_GPMC_CLKCTRL DM816_CLKCTRL_INDEX(0x1d0)
|
||||
#define DM816_DAVINCI_MDIO_CLKCTRL DM816_CLKCTRL_INDEX(0x1d4)
|
||||
#define DM816_EMAC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1d8)
|
||||
#define DM816_MPU_CLKCTRL DM816_CLKCTRL_INDEX(0x1dc)
|
||||
#define DM816_RTC_CLKCTRL DM816_CLKCTRL_INDEX(0x1f0)
|
||||
#define DM816_TPCC_CLKCTRL DM816_CLKCTRL_INDEX(0x1f4)
|
||||
#define DM816_TPTC0_CLKCTRL DM816_CLKCTRL_INDEX(0x1f8)
|
||||
#define DM816_TPTC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1fc)
|
||||
#define DM816_TPTC2_CLKCTRL DM816_CLKCTRL_INDEX(0x200)
|
||||
#define DM816_TPTC3_CLKCTRL DM816_CLKCTRL_INDEX(0x204)
|
||||
|
||||
#endif
|
||||
172
include/dt-bindings/clock/dra7.h
Normal file
172
include/dt-bindings/clock/dra7.h
Normal file
|
|
@ -0,0 +1,172 @@
|
|||
/*
|
||||
* Copyright 2017 Texas Instruments, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLK_DRA7_H
|
||||
#define __DT_BINDINGS_CLK_DRA7_H
|
||||
|
||||
#define DRA7_CLKCTRL_OFFSET 0x20
|
||||
#define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET)
|
||||
|
||||
/* mpu clocks */
|
||||
#define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
|
||||
|
||||
/* ipu clocks */
|
||||
#define DRA7_IPU_CLKCTRL_OFFSET 0x40
|
||||
#define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET)
|
||||
#define DRA7_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50)
|
||||
#define DRA7_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58)
|
||||
#define DRA7_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60)
|
||||
#define DRA7_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68)
|
||||
#define DRA7_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70)
|
||||
#define DRA7_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78)
|
||||
#define DRA7_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80)
|
||||
|
||||
/* rtc clocks */
|
||||
#define DRA7_RTC_CLKCTRL_OFFSET 0x40
|
||||
#define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET)
|
||||
#define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44)
|
||||
|
||||
/* coreaon clocks */
|
||||
#define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
|
||||
#define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
|
||||
|
||||
/* l3main1 clocks */
|
||||
#define DRA7_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
|
||||
#define DRA7_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
|
||||
#define DRA7_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
|
||||
#define DRA7_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
|
||||
#define DRA7_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
|
||||
#define DRA7_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
|
||||
#define DRA7_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
|
||||
|
||||
/* dma clocks */
|
||||
#define DRA7_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
|
||||
|
||||
/* emif clocks */
|
||||
#define DRA7_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
|
||||
|
||||
/* atl clocks */
|
||||
#define DRA7_ATL_CLKCTRL_OFFSET 0x0
|
||||
#define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET)
|
||||
#define DRA7_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0)
|
||||
|
||||
/* l4cfg clocks */
|
||||
#define DRA7_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
|
||||
#define DRA7_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
|
||||
#define DRA7_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
|
||||
#define DRA7_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
|
||||
#define DRA7_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
|
||||
#define DRA7_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58)
|
||||
#define DRA7_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60)
|
||||
#define DRA7_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68)
|
||||
#define DRA7_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
|
||||
#define DRA7_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
|
||||
#define DRA7_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
|
||||
#define DRA7_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
|
||||
#define DRA7_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
|
||||
#define DRA7_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98)
|
||||
#define DRA7_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
|
||||
|
||||
/* l3instr clocks */
|
||||
#define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
|
||||
#define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
|
||||
|
||||
/* dss clocks */
|
||||
#define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
|
||||
#define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
|
||||
|
||||
/* l3init clocks */
|
||||
#define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
|
||||
#define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
|
||||
#define DRA7_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
|
||||
#define DRA7_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
|
||||
#define DRA7_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
|
||||
#define DRA7_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
|
||||
#define DRA7_PCIE1_CLKCTRL DRA7_CLKCTRL_INDEX(0xb0)
|
||||
#define DRA7_PCIE2_CLKCTRL DRA7_CLKCTRL_INDEX(0xb8)
|
||||
#define DRA7_GMAC_CLKCTRL DRA7_CLKCTRL_INDEX(0xd0)
|
||||
#define DRA7_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0)
|
||||
#define DRA7_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8)
|
||||
#define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)
|
||||
|
||||
/* l4per clocks */
|
||||
#define DRA7_L4PER_CLKCTRL_OFFSET 0x0
|
||||
#define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET)
|
||||
#define DRA7_L4_PER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc)
|
||||
#define DRA7_L4_PER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x14)
|
||||
#define DRA7_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28)
|
||||
#define DRA7_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30)
|
||||
#define DRA7_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38)
|
||||
#define DRA7_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40)
|
||||
#define DRA7_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48)
|
||||
#define DRA7_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50)
|
||||
#define DRA7_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58)
|
||||
#define DRA7_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60)
|
||||
#define DRA7_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68)
|
||||
#define DRA7_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70)
|
||||
#define DRA7_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78)
|
||||
#define DRA7_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80)
|
||||
#define DRA7_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88)
|
||||
#define DRA7_EPWMSS1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x90)
|
||||
#define DRA7_EPWMSS2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x98)
|
||||
#define DRA7_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0)
|
||||
#define DRA7_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8)
|
||||
#define DRA7_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0)
|
||||
#define DRA7_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8)
|
||||
#define DRA7_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0)
|
||||
#define DRA7_EPWMSS0_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc4)
|
||||
#define DRA7_TIMER13_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc8)
|
||||
#define DRA7_TIMER14_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd0)
|
||||
#define DRA7_TIMER15_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd8)
|
||||
#define DRA7_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0)
|
||||
#define DRA7_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8)
|
||||
#define DRA7_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100)
|
||||
#define DRA7_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108)
|
||||
#define DRA7_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110)
|
||||
#define DRA7_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118)
|
||||
#define DRA7_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120)
|
||||
#define DRA7_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128)
|
||||
#define DRA7_TIMER16_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x130)
|
||||
#define DRA7_QSPI_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x138)
|
||||
#define DRA7_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140)
|
||||
#define DRA7_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148)
|
||||
#define DRA7_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150)
|
||||
#define DRA7_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158)
|
||||
#define DRA7_MCASP2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x160)
|
||||
#define DRA7_MCASP3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x168)
|
||||
#define DRA7_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170)
|
||||
#define DRA7_MCASP5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x178)
|
||||
#define DRA7_MCASP8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x190)
|
||||
#define DRA7_MCASP4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x198)
|
||||
#define DRA7_AES1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a0)
|
||||
#define DRA7_AES2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a8)
|
||||
#define DRA7_DES_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1b0)
|
||||
#define DRA7_RNG_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c0)
|
||||
#define DRA7_SHAM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c8)
|
||||
#define DRA7_UART7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1d0)
|
||||
#define DRA7_UART8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e0)
|
||||
#define DRA7_UART9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e8)
|
||||
#define DRA7_DCAN2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1f0)
|
||||
#define DRA7_MCASP6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x204)
|
||||
#define DRA7_MCASP7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x208)
|
||||
|
||||
/* wkupaon clocks */
|
||||
#define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
|
||||
#define DRA7_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
|
||||
#define DRA7_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
|
||||
#define DRA7_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
|
||||
#define DRA7_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
|
||||
#define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
|
||||
#define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
|
||||
#define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
|
||||
|
||||
#endif
|
||||
118
include/dt-bindings/clock/omap5.h
Normal file
118
include/dt-bindings/clock/omap5.h
Normal file
|
|
@ -0,0 +1,118 @@
|
|||
/*
|
||||
* Copyright 2017 Texas Instruments, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLK_OMAP5_H
|
||||
#define __DT_BINDINGS_CLK_OMAP5_H
|
||||
|
||||
#define OMAP5_CLKCTRL_OFFSET 0x20
|
||||
#define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET)
|
||||
|
||||
/* mpu clocks */
|
||||
#define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
|
||||
/* dsp clocks */
|
||||
#define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
|
||||
/* abe clocks */
|
||||
#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
|
||||
#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
|
||||
#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
|
||||
#define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
|
||||
#define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
|
||||
#define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
|
||||
#define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70)
|
||||
#define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
|
||||
#define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80)
|
||||
|
||||
/* l3main1 clocks */
|
||||
#define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
|
||||
/* l3main2 clocks */
|
||||
#define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
|
||||
/* ipu clocks */
|
||||
#define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
|
||||
/* dma clocks */
|
||||
#define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
|
||||
/* emif clocks */
|
||||
#define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
#define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
|
||||
#define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
|
||||
|
||||
/* l4cfg clocks */
|
||||
#define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
#define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
|
||||
#define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
|
||||
|
||||
/* l3instr clocks */
|
||||
#define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
#define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
|
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/* l4per clocks */
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#define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
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#define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
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#define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
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#define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40)
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#define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
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#define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
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#define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60)
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#define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
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#define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70)
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#define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
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#define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80)
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#define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0)
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#define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8)
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#define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0)
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#define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8)
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#define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0)
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#define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0)
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#define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8)
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#define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100)
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#define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108)
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#define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110)
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#define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118)
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#define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120)
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#define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128)
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#define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140)
|
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#define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148)
|
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#define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150)
|
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#define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158)
|
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#define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160)
|
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#define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168)
|
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#define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170)
|
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#define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178)
|
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|
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/* dss clocks */
|
||||
#define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
|
||||
/* l3init clocks */
|
||||
#define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
|
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#define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
|
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#define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
|
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#define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
|
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#define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88)
|
||||
#define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0)
|
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#define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8)
|
||||
#define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0)
|
||||
|
||||
/* wkupaon clocks */
|
||||
#define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
#define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
|
||||
#define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
|
||||
#define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40)
|
||||
#define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
|
||||
#define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue