mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-11 15:11:48 -04:00
Merge "ARM: dts: msm: Add tlmm pinctrl support for SA8195"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
90a1d855f3
20 changed files with 6122 additions and 41 deletions
|
|
@ -192,6 +192,9 @@ compatible = "qcom,sa8155p-adp-star"
|
|||
compatible = "qcom,sa8155-adp-air"
|
||||
compatible = "qcom,sa8155-v2-adp-air"
|
||||
compatible = "qcom,sa8155p-v2-adp-air"
|
||||
compatible = "qcom,sa8195p-adp-star"
|
||||
compatible = "qcom,sa8195p-v2-adp-air"
|
||||
compatible = "qcom,sa8195p"
|
||||
compatible = "qcom,adp-air"
|
||||
compatible = "qcom,kona-rumi"
|
||||
compatible = "qcom,kona-mtp"
|
||||
|
|
|
|||
185
bindings/pinctrl/qcom,sdmshrike-pinctrl.txt
Normal file
185
bindings/pinctrl/qcom,sdmshrike-pinctrl.txt
Normal file
|
|
@ -0,0 +1,185 @@
|
|||
Qualcomm Technologies, Inc. SDMSHRIKE TLMM block
|
||||
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
sdmshrike platform.
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be "qcom,sdmshrike-pinctrl"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: the base address and size of the north, south, west
|
||||
and east TLMM tiles.
|
||||
|
||||
- reg-names:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Defintiion: names for the cells of reg, must contain "north", "south"
|
||||
"west" and "east".
|
||||
|
||||
- interrupts:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: should specify the TLMM summary IRQ.
|
||||
|
||||
- interrupt-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as an interrupt controller
|
||||
|
||||
- #interrupt-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
- gpio-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as a gpio controller
|
||||
|
||||
- #gpio-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/gpio/gpio.h>
|
||||
|
||||
- gpio-ranges:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: see ../gpio/gpio.txt
|
||||
|
||||
- gpio-reserved-ranges:
|
||||
Usage: optional
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: see ../gpio/gpio.txt
|
||||
|
||||
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
|
||||
a general description of GPIO and interrupt bindings.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
The pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
parameters, such as pull-up, drive strength, etc.
|
||||
|
||||
|
||||
PIN CONFIGURATION NODES:
|
||||
|
||||
The name of each subnode is not important; all subnodes should be enumerated
|
||||
and processed purely based on their content.
|
||||
|
||||
Each subnode only affects those parameters that are explicitly listed. In
|
||||
other words, a subnode that lists a mux function but no pin configuration
|
||||
parameters implies no information about any pin configuration parameters.
|
||||
Similarly, a pin subnode that describes a pullup parameter implies no
|
||||
information about e.g. the mux function.
|
||||
|
||||
|
||||
The following generic properties as defined in pinctrl-bindings.txt are valid
|
||||
to specify in a pin configuration subnode:
|
||||
|
||||
- pins:
|
||||
Usage: required
|
||||
Value type: <string-array>
|
||||
Definition: List of gpio pins affected by the properties specified in
|
||||
this subnode.
|
||||
|
||||
Valid pins are:
|
||||
gpio0-gpio149
|
||||
Supports mux, bias and drive-strength
|
||||
|
||||
sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
|
||||
sdc2_data sdc1_rclk
|
||||
Supports bias and drive-strength
|
||||
|
||||
ufs_reset
|
||||
Supports bias and drive-strength
|
||||
|
||||
- function:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Specify the alternative function to be configured for the
|
||||
specified pins. Functions are only valid for gpio pins.
|
||||
Valid values are:
|
||||
|
||||
adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char,
|
||||
atest_char0, atest_char1, atest_char2, atest_char3,
|
||||
audio_ref, atest_usb1, atest_usb2, atest_usb10,
|
||||
atest_usb11, atest_usb12, atest_usb13, atest_usb20,
|
||||
atest_usb21, atest_usb22, atest_usb2, atest_usb23,
|
||||
btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
|
||||
cci_timer1, cci_timer2, cci_timer3, cci_timer4,
|
||||
cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
|
||||
ddr_pxi0, ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd,
|
||||
emac_phy, emac_pps, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
|
||||
hs1_mi2s, hs2_mi2s, hs3_mi2s, jitter_bist,
|
||||
lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1,
|
||||
mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps,
|
||||
pa_indicator, pci_e0, phase_flag, pll_bypassnl,
|
||||
pll_bist, pci_e1, pll_reset, pri_mi2s, pri_mi2s_ws,
|
||||
prng_rosc, qdss, qdss_cti, qlink_request, qlink_enable,
|
||||
qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qua_mi2s,
|
||||
qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
|
||||
qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16,
|
||||
qup17, qup18, qup19, qup_l4, qup_l5, qup_l6, rgmii,
|
||||
sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu, ter_mi2s,
|
||||
tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
|
||||
tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt,
|
||||
usb2phy_ac, usb_phy, vfr_1, vsense_trigger, wlan1_adc0,
|
||||
wlan1_adc1, wlan2_adc0, wlan2_adc1, wmss_reset
|
||||
|
||||
- bias-disable:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as no pull.
|
||||
|
||||
- bias-pull-down:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as pull down.
|
||||
|
||||
- bias-pull-up:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as pull up.
|
||||
|
||||
- output-high:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven
|
||||
high.
|
||||
Not valid for sdc pins.
|
||||
|
||||
- output-low:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven
|
||||
low.
|
||||
Not valid for sdc pins.
|
||||
|
||||
- drive-strength:
|
||||
Usage: optional
|
||||
Value type: <u32>
|
||||
Definition: Selects the drive strength for the specified pins, in mA.
|
||||
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
|
||||
|
||||
Example:
|
||||
|
||||
tlmm: pinctrl@3000000 {
|
||||
compatible = "qcom,sdmshrike-pinctrl";
|
||||
reg = <0x03000000 0xddc000>, <0x17c000f0 0x60>;
|
||||
reg-names = "pinctrl", "spi_cfg";
|
||||
interrupts = <0 208 0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
|
@ -144,26 +144,35 @@ dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb
|
|||
endif
|
||||
|
||||
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
|
||||
dtbo-$(CONFIG_ARCH_SM8150) += \
|
||||
sm8150-cdp-overlay.dtbo \
|
||||
sa8155-adp-star-overlay.dtbo \
|
||||
sa8155p-adp-star-overlay.dtbo \
|
||||
sa8155-v2-adp-air-overlay.dtbo \
|
||||
sa8155p-v2-adp-air-overlay.dtbo
|
||||
dtbo-$(CONFIG_ARCH_SA8155) += \
|
||||
sa8155-adp-star-overlay.dtbo \
|
||||
sa8155p-adp-star-overlay.dtbo \
|
||||
sa8155-v2-adp-air-overlay.dtbo \
|
||||
sa8155p-v2-adp-air-overlay.dtbo
|
||||
|
||||
sm8150-cdp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb
|
||||
sa8155-adp-star-overlay.dtbo-base := sa8155.dtb sa8155-v2.dtb
|
||||
sa8155p-adp-star-overlay.dtbo-base := sa8155p.dtb sa8155p-v2.dtb
|
||||
sa8155-v2-adp-air-overlay.dtbo-base := sa8155.dtb sa8155-v2.dtb
|
||||
sa8155p-v2-adp-air-overlay.dtbo-base := sa8155p.dtb sa8155p-v2.dtb
|
||||
else
|
||||
dtb-$(CONFIG_ARCH_SM8150) += sm8150-cdp.dtb \
|
||||
sa8155-adp-star.dtb \
|
||||
sa8155p-adp-star.dtb \
|
||||
sa8155-v2-adp-star.dtb \
|
||||
sa8155p-v2-adp-star.dtb \
|
||||
sa8155-v2-adp-air.dtb \
|
||||
sa8155p-v2-adp-air.dtb
|
||||
dtb-$(CONFIG_ARCH_SA8155) += sa8155-adp-star.dtb \
|
||||
sa8155p-adp-star.dtb \
|
||||
sa8155-v2-adp-star.dtb \
|
||||
sa8155p-v2-adp-star.dtb \
|
||||
sa8155-v2-adp-air.dtb \
|
||||
sa8155p-v2-adp-air.dtb
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
|
||||
dtbo-$(CONFIG_ARCH_SA8195) += \
|
||||
sa8195p-adp-star-overlay.dtbo \
|
||||
sa8195p-v2-adp-air-overlay.dtbo
|
||||
|
||||
sa8195p-adp-star-overlay.dtbo-base := sa8195p.dtb
|
||||
sa8195p-v2-adp-air-overlay.dtbo-base := sa8195p.dtb
|
||||
else
|
||||
dtb-$(CONFIG_ARCH_SA8195) += sa8195p-adp-star.dtb \
|
||||
sa8195p-v2-adp-air.dtb
|
||||
endif
|
||||
endif
|
||||
|
||||
|
|
|
|||
5
qcom/sa8195p-adp-common.dtsi
Normal file
5
qcom/sa8195p-adp-common.dtsi
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
&qupv3_id_1 {
|
||||
status = "ok"
|
||||
};
|
||||
12
qcom/sa8195p-adp-star-overlay.dts
Normal file
12
qcom/sa8195p-adp-star-overlay.dts
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sa8195p-adp-star.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ADP-STAR";
|
||||
compatible = "qcom,sa8195p-adp-star", "qcom,sa8195p",
|
||||
"qcom,adp-star";
|
||||
qcom,msm-id = <405 0x20000>;
|
||||
qcom,board-id = <0x010019 0>;
|
||||
};
|
||||
11
qcom/sa8195p-adp-star.dts
Normal file
11
qcom/sa8195p-adp-star.dts
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "sa8195p.dtsi"
|
||||
#include "sa8195p-adp-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SA8195P ADP-STAR";
|
||||
compatible = "qcom,sa8195p-adp-star", "qcom,sa8195p",
|
||||
"qcom,adp-star";
|
||||
qcom,board-id = <25 0>;
|
||||
};
|
||||
1
qcom/sa8195p-adp-star.dtsi
Normal file
1
qcom/sa8195p-adp-star.dtsi
Normal file
|
|
@ -0,0 +1 @@
|
|||
#include "sa8195p-adp-common.dtsi"
|
||||
13
qcom/sa8195p-v2-adp-air-overlay.dts
Normal file
13
qcom/sa8195p-v2-adp-air-overlay.dts
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sa8195p-v2-adp-air.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ADP-AIR";
|
||||
compatible = "qcom,sa8195p-v2-adp-air", "qcom,sa8195p",
|
||||
"qcom,adp-air";
|
||||
qcom,msm-id = <405 0x20000>;
|
||||
qcom,board-id = <0x02010019 0>;
|
||||
};
|
||||
|
||||
10
qcom/sa8195p-v2-adp-air.dts
Normal file
10
qcom/sa8195p-v2-adp-air.dts
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "sa8195p.dtsi"
|
||||
#include "sa8195p-adp-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SA8195P V2 ADP AIR";
|
||||
compatible = "qcom,sa8195p-v2-adp-air", "qcom,sa8195p", "qcom,adp-air";
|
||||
qcom,board-id = <0x02010019 0>;
|
||||
};
|
||||
1
qcom/sa8195p-v2-adp-air.dtsi
Normal file
1
qcom/sa8195p-v2-adp-air.dtsi
Normal file
|
|
@ -0,0 +1 @@
|
|||
#include "sa8195p-adp-common.dtsi"
|
||||
10
qcom/sa8195p.dts
Normal file
10
qcom/sa8195p.dts
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "sa8195p.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SA8195P AU SoC";
|
||||
compatible = "qcom,sa8195";
|
||||
qcom,pmic-name = "PM8150";
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
8
qcom/sa8195p.dtsi
Normal file
8
qcom/sa8195p.dtsi
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
#include "sdmshrike-v2.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SA8195P";
|
||||
qcom,msm-name = "SA8195P";
|
||||
qcom,msm-id = <405 0x20000>;
|
||||
};
|
||||
|
||||
5155
qcom/sdmshrike-pinctrl.dtsi
Normal file
5155
qcom/sdmshrike-pinctrl.dtsi
Normal file
File diff suppressed because it is too large
Load diff
10
qcom/sdmshrike-v2.dts
Normal file
10
qcom/sdmshrike-v2.dts
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "sdmshrike-v2.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SA8195 v2 SoC";
|
||||
compatible = "qcom,sa8195";
|
||||
qcom,pmic-name = "PM8150";
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
8
qcom/sdmshrike-v2.dtsi
Normal file
8
qcom/sdmshrike-v2.dtsi
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
|
||||
#include "sdmshrike.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SA8195 V2";
|
||||
qcom,msm-name = "SA8195 V2";
|
||||
qcom,msm-id = <340 0x20000>;
|
||||
};
|
||||
|
||||
10
qcom/sdmshrike.dts
Normal file
10
qcom/sdmshrike.dts
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "sdmshrike.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SDMSHRIKE SoC";
|
||||
compatible = "qcom,sdmshrike";
|
||||
qcom,pmic-name = "PM8150";
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
656
qcom/sdmshrike.dtsi
Normal file
656
qcom/sdmshrike.dtsi
Normal file
|
|
@ -0,0 +1,656 @@
|
|||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SDMSHRIKE";
|
||||
compatible = "qcom,sdmshrike";
|
||||
qcom,msm-name = "SDMSHRIKE";
|
||||
qcom,msm-id = <340 0x10000>;
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
memory { device_type = "memory"; reg = <0 0 0 0>; };
|
||||
|
||||
aliases {
|
||||
serial0 = &uart2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1024>;
|
||||
cache-size = <0x8000>;
|
||||
next-level-cache = <&L2_0>;
|
||||
#cooling-cells = <2>;
|
||||
L2_0: l2-cache {
|
||||
compatible = "arm,arch-cache";
|
||||
cache-size = <0x20000>;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_0>;
|
||||
|
||||
L3_0: l3-cache {
|
||||
compatible = "arm,arch-cache";
|
||||
cache-size = <0x400000>;
|
||||
cache-level = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
L1_I_0: l1-icache {
|
||||
compatible = "arm,arch-cache";
|
||||
qcom,dump-size = <0xa000>;
|
||||
};
|
||||
|
||||
L1_D_0: l1-dcache {
|
||||
compatible = "arm,arch-cache";
|
||||
qcom,dump-size = <0xa000>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU1: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1024>;
|
||||
cache-size = <0x8000>;
|
||||
next-level-cache = <&L2_1>;
|
||||
#cooling-cells = <2>;
|
||||
L2_1: l2-cache {
|
||||
compatible = "arm,arch-cache";
|
||||
cache-size = <0x20000>;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
|
||||
L1_I_100: l1-icache {
|
||||
compatible = "arm,arch-cache";
|
||||
qcom,dump-size = <0xa000>;
|
||||
};
|
||||
|
||||
L1_D_100: l1-dcache {
|
||||
compatible = "arm,arch-cache";
|
||||
qcom,dump-size = <0xa000>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU2: cpu@200 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x200>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1024>;
|
||||
cache-size = <0x8000>;
|
||||
next-level-cache = <&L2_2>;
|
||||
#cooling-cells = <2>;
|
||||
L2_2: l2-cache {
|
||||
compatible = "arm,arch-cache";
|
||||
cache-size = <0x20000>;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
|
||||
L1_I_200: l1-icache {
|
||||
compatible = "arm,arch-cache";
|
||||
qcom,dump-size = <0xa000>;
|
||||
};
|
||||
|
||||
L1_D_200: l1-dcache {
|
||||
compatible = "arm,arch-cache";
|
||||
qcom,dump-size = <0xa000>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU3: cpu@300 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x300>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1024>;
|
||||
cache-size = <0x8000>;
|
||||
next-level-cache = <&L2_3>;
|
||||
#cooling-cells = <2>;
|
||||
L2_3: l2-cache {
|
||||
compatible = "arm,arch-cache";
|
||||
cache-size = <0x20000>;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
|
||||
L1_I_300: l1-icache {
|
||||
compatible = "arm,arch-cache";
|
||||
qcom,dump-size = <0xa000>;
|
||||
};
|
||||
|
||||
L1_D_300: l1-dcache {
|
||||
compatible = "arm,arch-cache";
|
||||
qcom,dump-size = <0xa000>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU4: cpu@400 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x400>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1740>;
|
||||
cache-size = <0x20000>;
|
||||
next-level-cache = <&L2_4>;
|
||||
#cooling-cells = <2>;
|
||||
L2_4: l2-cache {
|
||||
compatible = "arm,arch-cache";
|
||||
cache-size = <0x80000>;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
|
||||
L1_I_400: l1-icache {
|
||||
compatible = "arm,arch-cache";
|
||||
qcom,dump-size = <0x14000>;
|
||||
};
|
||||
|
||||
L1_D_400: l1-dcache {
|
||||
compatible = "arm,arch-cache";
|
||||
qcom,dump-size = <0x14000>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU5: cpu@500 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x500>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1740>;
|
||||
cache-size = <0x20000>;
|
||||
next-level-cache = <&L2_5>;
|
||||
#cooling-cells = <2>;
|
||||
L2_5: l2-cache {
|
||||
compatible = "arm,arch-cache";
|
||||
cache-size = <0x80000>;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
|
||||
L1_I_500: l1-icache {
|
||||
compatible = "arm,arch-cache";
|
||||
qcom,dump-size = <0x14000>;
|
||||
};
|
||||
|
||||
L1_D_500: l1-dcache {
|
||||
compatible = "arm,arch-cache";
|
||||
qcom,dump-size = <0x14000>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU6: cpu@600 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x600>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1740>;
|
||||
cache-size = <0x20000>;
|
||||
next-level-cache = <&L2_6>;
|
||||
#cooling-cells = <2>;
|
||||
L2_6: l2-cache {
|
||||
compatible = "arm,arch-cache";
|
||||
cache-size = <0x80000>;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
|
||||
L1_I_600: l1-icache {
|
||||
compatible = "arm,arch-cache";
|
||||
qcom,dump-size = <0x14000>;
|
||||
};
|
||||
|
||||
L1_D_600: l1-dcache {
|
||||
compatible = "arm,arch-cache";
|
||||
qcom,dump-size = <0x14000>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU7: cpu@700 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x700>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1740>;
|
||||
cache-size = <0x20000>;
|
||||
next-level-cache = <&L2_7>;
|
||||
#cooling-cells = <2>;
|
||||
L2_7: l2-cache {
|
||||
compatible = "arm,arch-cache";
|
||||
cache-size = <0x80000>;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
|
||||
L1_I_700: l1-icache {
|
||||
compatible = "arm,arch-cache";
|
||||
qcom,dump-size = <0x14000>;
|
||||
};
|
||||
|
||||
L1_D_700: l1-dcache {
|
||||
compatible = "arm,arch-cache";
|
||||
qcom,dump-size = <0x14000>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU1>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&CPU2>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&CPU3>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&CPU4>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU5>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&CPU6>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&CPU7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
firmware: firmware {
|
||||
};
|
||||
|
||||
reserved_memory: reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
hyp_mem: hyp_mem@85700000 {
|
||||
no-map;
|
||||
reg = <0x0 0x85700000 0x0 0x600000>;
|
||||
};
|
||||
|
||||
xbl_aop_mem: xbl_aop_mem@85e00000 {
|
||||
no-map;
|
||||
reg = <0x0 0x85e00000 0x0 0x140000>;
|
||||
};
|
||||
|
||||
flex_sec_apps_mem: flex_sec_apps_regions@85ffd000 {
|
||||
no-map;
|
||||
reg = <0x0 0x85ffd000 0x0 0x3000>;
|
||||
};
|
||||
|
||||
smem_region: smem@86000000 {
|
||||
no-map;
|
||||
reg = <0x0 0x86000000 0x0 0x200000>;
|
||||
};
|
||||
|
||||
removed_regions: removed_regions@86200000 {
|
||||
no-map;
|
||||
reg = <0x0 0x86200000 0x0 0x5500000>;
|
||||
};
|
||||
|
||||
pil_camera_mem: camera_region@8b700000 {
|
||||
no-map;
|
||||
reg = <0x0 0x8b700000 0x0 0x500000>;
|
||||
};
|
||||
|
||||
pil_wlan_fw_mem: pil_wlan_fw_region@8bc00000 {
|
||||
no-map;
|
||||
reg = <0x0 0x8bc00000 0x0 0x180000>;
|
||||
};
|
||||
|
||||
pil_npu_mem: pil_npu_region@0x8bd80000 {
|
||||
no-map;
|
||||
reg = <0x0 0x8bd80000 0x0 0x80000>;
|
||||
};
|
||||
|
||||
pil_adsp_mem: pil_adsp_region@0x8be00000 {
|
||||
no-map;
|
||||
reg = <0x0 0x8be00000 0x0 0x1a00000>;
|
||||
};
|
||||
|
||||
pil_modem_mem: modem_region@0x8d800000 {
|
||||
no-map;
|
||||
reg = <0x0 0x8d800000 0x0 0x9600000>;
|
||||
};
|
||||
|
||||
pil_video_mem: pil_video_region@0x96e00000 {
|
||||
no-map;
|
||||
reg = <0x0 0x96e00000 0x0 0x500000>;
|
||||
};
|
||||
|
||||
pil_slpi_mem: pil_slpi_region@0x97300000 {
|
||||
no-map;
|
||||
reg = <0x0 0x97300000 0x0 0x1400000>;
|
||||
};
|
||||
|
||||
pil_ipa_fw_mem: pil_ipa_fw_region@0x98700000 {
|
||||
no-map;
|
||||
reg = <0x0 0x98700000 0x0 0x10000>;
|
||||
};
|
||||
|
||||
pil_ipa_gsi_mem: pil_ipa_gsi_region@0x98710000 {
|
||||
no-map;
|
||||
reg = <0x0 0x98710000 0x0 0x5000>;
|
||||
};
|
||||
|
||||
pil_gpu_mem: pil_gpu_region@0x98715000 {
|
||||
no-map;
|
||||
reg = <0x0 0x98715000 0x0 0x2000>;
|
||||
};
|
||||
|
||||
pil_spss_mem: pil_spss_region@0x98800000 {
|
||||
no-map;
|
||||
reg = <0x0 0x98800000 0x0 0x100000>;
|
||||
};
|
||||
|
||||
pil_cdsp_mem: cdsp_regions@0x98900000 {
|
||||
no-map;
|
||||
reg = <0x0 0x98900000 0x0 0x1400000>;
|
||||
};
|
||||
|
||||
qseecom_mem: qseecom_region@0x9e400000 {
|
||||
compatible = "shared-dma-pool";
|
||||
no-map;
|
||||
reg = <0x0 0x9e400000 0x0 0x1400000>;
|
||||
};
|
||||
|
||||
|
||||
cont_splash_memory: cont_splash_region@0x9c000000 {
|
||||
reg = <0x0 0x9c000000 0x0 0x02400000>;
|
||||
label = "cont_splash_region";
|
||||
};
|
||||
|
||||
disp_rdump_memory: disp_rdump_region@0x9c000000 {
|
||||
reg = <0x0 0x9c000000 0x0 0x02400000>;
|
||||
label = "disp_rdump_region";
|
||||
};
|
||||
|
||||
adsp_mem: adsp_region {
|
||||
compatible = "shared-dma-pool";
|
||||
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
||||
reusable;
|
||||
alignment = <0x0 0x400000>;
|
||||
size = <0x0 0x1000000>;
|
||||
};
|
||||
|
||||
cdsp_mem: cdsp_region {
|
||||
compatible = "shared-dma-pool";
|
||||
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
||||
reusable;
|
||||
alignment = <0x0 0x400000>;
|
||||
size = <0x0 0x400000>;
|
||||
};
|
||||
|
||||
user_contig_mem: user_contig_region {
|
||||
compatible = "shared-dma-pool";
|
||||
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
||||
reusable;
|
||||
alignment = <0x0 0x400000>;
|
||||
size = <0x0 0x1000000>;
|
||||
};
|
||||
|
||||
qseecom_ta_mem: qseecom_ta_region {
|
||||
compatible = "shared-dma-pool";
|
||||
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
||||
reusable;
|
||||
alignment = <0x0 0x400000>;
|
||||
size = <0x0 0x1000000>;
|
||||
};
|
||||
|
||||
sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
|
||||
compatible = "shared-dma-pool";
|
||||
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
||||
reusable;
|
||||
alignment = <0x0 0x400000>;
|
||||
size = <0x0 0x800000>;
|
||||
};
|
||||
|
||||
secure_display_memory: secure_display_region { /* Secure UI */
|
||||
compatible = "shared-dma-pool";
|
||||
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
||||
reusable;
|
||||
alignment = <0x0 0x400000>;
|
||||
size = <0x0 0xA000000>;
|
||||
};
|
||||
|
||||
dump_mem: mem_dump_region {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
size = <0 0x2400000>;
|
||||
};
|
||||
|
||||
/* global autoconfigured region for contiguous allocations */
|
||||
linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
||||
reusable;
|
||||
alignment = <0x0 0x400000>;
|
||||
size = <0x0 0x2800000>;
|
||||
linux,cma-default;
|
||||
};
|
||||
};
|
||||
|
||||
vendor: vendor {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0xffffffff>;
|
||||
compatible = "simple-bus";
|
||||
};
|
||||
|
||||
soc: soc { };
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0xffffffff>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
intc: interrupt-controller@17a00000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
#redistributor-regions = <1>;
|
||||
redistributor-stride = <0x0 0x20000>;
|
||||
reg = <0x17a00000 0x10000>, /* GICD */
|
||||
<0x17a60000 0x100000>; /* GICR * 8 */
|
||||
interrupts = <1 9 4>;
|
||||
interrupt-parent = <&intc>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <1 1 0xf08>,
|
||||
<1 2 0xf08>,
|
||||
<1 3 0xf08>,
|
||||
<1 0 0xf08>;
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
timer@0x17c20000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
compatible = "arm,armv7-timer-mem";
|
||||
reg = <0x17c20000 0x1000>;
|
||||
clock-frequency = <19200000>;
|
||||
|
||||
frame@0x17c21000 {
|
||||
frame-number = <0>;
|
||||
interrupts = <0 7 0x4>,
|
||||
<0 6 0x4>;
|
||||
reg = <0x17c21000 0x1000>,
|
||||
<0x17c22000 0x1000>;
|
||||
};
|
||||
|
||||
frame@17c23000 {
|
||||
frame-number = <1>;
|
||||
interrupts = <0 8 0x4>;
|
||||
reg = <0x17c23000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17c25000 {
|
||||
frame-number = <2>;
|
||||
interrupts = <0 9 0x4>;
|
||||
reg = <0x17c25000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17c27000 {
|
||||
frame-number = <3>;
|
||||
interrupts = <0 10 0x4>;
|
||||
reg = <0x17c26000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17c29000 {
|
||||
frame-number = <4>;
|
||||
interrupts = <0 11 0x4>;
|
||||
reg = <0x17c29000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17c2b000 {
|
||||
frame-number = <5>;
|
||||
interrupts = <0 12 0x4>;
|
||||
reg = <0x17c2b000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17c2d000 {
|
||||
frame-number = <6>;
|
||||
interrupts = <0 13 0x4>;
|
||||
reg = <0x17c2d000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
qcom,msm-imem@146bf000 {
|
||||
compatible = "qcom,msm-imem";
|
||||
reg = <0x146bf000 0x1000>;
|
||||
ranges = <0x0 0x146bf000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
mem_dump_table@10 {
|
||||
compatible = "qcom,msm-imem-mem_dump_table";
|
||||
reg = <0x10 0x8>;
|
||||
};
|
||||
|
||||
restart_reason@65c {
|
||||
compatible = "qcom,msm-imem-restart_reason";
|
||||
reg = <0x65c 0x4>;
|
||||
};
|
||||
|
||||
dload_type@1c {
|
||||
compatible = "qcom,msm-imem-dload-type";
|
||||
reg = <0x1c 0x4>;
|
||||
};
|
||||
|
||||
boot_stats@6b0 {
|
||||
compatible = "qcom,msm-imem-boot_stats";
|
||||
reg = <0x6b0 0x20>;
|
||||
};
|
||||
|
||||
kaslr_offset@6d0 {
|
||||
compatible = "qcom,msm-imem-kaslr_offset";
|
||||
reg = <0x6d0 0xc>;
|
||||
};
|
||||
|
||||
pil@94c {
|
||||
compatible = "qcom,msm-imem-pil";
|
||||
reg = <0x94c 0xc8>;
|
||||
};
|
||||
|
||||
diag_dload@c8 {
|
||||
compatible = "qcom,msm-imem-diag-dload";
|
||||
reg = <0xc8 0xc8>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,msm-rtb {
|
||||
compatible = "qcom,msm-rtb";
|
||||
qcom,rtb-size = <0x100000>;
|
||||
};
|
||||
|
||||
qcom,mpm2-sleep-counter@c221000 {
|
||||
compatible = "qcom,mpm2-sleep-counter";
|
||||
reg = <0xc221000 0x1000>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
apps_rsc: rsc@18200000 {
|
||||
label = "apps_rsc";
|
||||
compatible = "qcom,rpmh-rsc";
|
||||
reg = <0x18200000 0x10000>,
|
||||
<0x18210000 0x10000>,
|
||||
<0x18220000 0x10000>;
|
||||
reg-names = "drv-0", "drv-1", "drv-2";
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,tcs-offset = <0xd00>;
|
||||
qcom,drv-id = <2>;
|
||||
qcom,tcs-config = <ACTIVE_TCS 2>,
|
||||
<SLEEP_TCS 1>,
|
||||
<WAKE_TCS 1>,
|
||||
<CONTROL_TCS 0>;
|
||||
|
||||
};
|
||||
|
||||
qupv3_id_1: geniqup@ac0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
reg = <0x00ac0000 0x6000>;
|
||||
ranges;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
status = "disabled";
|
||||
|
||||
uart2: serial@a90000 {
|
||||
compatible = "qcom,geni-debug-uart";
|
||||
reg = <0x0 0x00a90000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "ok"
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
#include "sdmshrike-pinctrl.dtsi"
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "sm8150-cdp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "CDP";
|
||||
compatible = "qcom,sm8150-cdp", "qcom,sm8150", "qcom,cdp";
|
||||
qcom,board-id = <1 0>;
|
||||
};
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "sm8150.dtsi"
|
||||
#include "sm8150-cdp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SM8150 CDP";
|
||||
compatible = "qcom,sm8150-cdp", "qcom,sm8150", "qcom,cdp";
|
||||
qcom,board-id = <1 0>;
|
||||
};
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
Loading…
Reference in a new issue