From 90ded952e1d3a81814773adc03193b960caaff56 Mon Sep 17 00:00:00 2001 From: Shefali Jain Date: Tue, 11 Sep 2018 10:26:35 +0530 Subject: [PATCH] clk: qcom: rcg2: Add DIV_ROUND_CLOSEST_ULL to roundoff RCG frequency The Alpha BW for Fabia PLL is 16 bit and the calculated hw rate has additional KHz of frequency. Due to this additional frequency, the source is wrongly selected. Truncate the additional KHz using the DIV_ROUND_CLOSEST_ULL. Change-Id: Ic9c523c87277c4813b676cf8a52a1207e8f1ecc2 Signed-off-by: Shefali Jain --- drivers/clk/qcom/clk-rcg2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index f6b97489e80a..d96dd1884b9c 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -440,7 +440,8 @@ static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate, } if (rcg->flags & FORCE_ENABLE_RCG) { - rcg->current_freq = clk_get_rate(hw->clk); + rcg->current_freq = DIV_ROUND_CLOSEST_ULL( + clk_get_rate(hw->clk), 1000) * 1000; if (rcg->current_freq == cxo_f.freq) curr_src_index = 0; else {