mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-12 07:37:31 -04:00
Merge "ARM: dts: msm: Add a new power level for supported devices"
This commit is contained in:
commit
90dfd0bbe3
3 changed files with 330 additions and 122 deletions
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@ -52,6 +52,9 @@
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qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */
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nvmem-cells = <&gpu_speed_bin>;
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nvmem-cell-names = "speed_bin";
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qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr";
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interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
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@ -1,173 +1,364 @@
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&msm_gpu {
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qcom,chipid = <0x06060001>;
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qcom,initial-pwrlevel = <9>;
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/delete-property/qcom,initial-pwrlevel;
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/delete-node/qcom,gpu-pwrlevels;
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/* Power levels */
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qcom,gpu-pwrlevels {
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/* Power levels bins */
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qcom,gpu-pwrlevel-bins {
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compatible="qcom,gpu-pwrlevel-bins";
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-pwrlevels";
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qcom,gpu-pwrlevels-0 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <0>;
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qcom,initial-pwrlevel = <9>;
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <840000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <840000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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qcom,bus-freq-ddr7 = <11>;
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qcom,bus-min-ddr7 = <11>;
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qcom,bus-max-ddr7 = <11>;
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qcom,bus-freq-ddr7 = <11>;
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qcom,bus-min-ddr7 = <11>;
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qcom,bus-max-ddr7 = <11>;
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qcom,bus-freq-ddr8 = <11>;
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qcom,bus-min-ddr8 = <11>;
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qcom,bus-max-ddr8 = <11>;
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qcom,bus-freq-ddr8 = <11>;
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qcom,bus-min-ddr8 = <11>;
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qcom,bus-max-ddr8 = <11>;
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qcom,acd-level = <0x882a5ffd>;
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};
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <778000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,bus-freq-ddr7 = <11>;
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qcom,bus-min-ddr7 = <11>;
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qcom,bus-max-ddr7 = <11>;
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qcom,bus-freq-ddr8 = <11>;
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qcom,bus-min-ddr8 = <11>;
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qcom,bus-max-ddr8 = <11>;
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qcom,acd-level = <0xa82a5ffd>;
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};
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <738000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq-ddr7 = <11>;
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qcom,bus-min-ddr7 = <11>;
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qcom,bus-max-ddr7 = <11>;
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qcom,bus-freq-ddr8 = <11>;
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qcom,bus-min-ddr8 = <11>;
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qcom,bus-max-ddr8 = <11>;
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qcom,acd-level = <0xa82a5ffd>;
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};
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <676000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq-ddr7 = <11>;
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qcom,bus-min-ddr7 = <11>;
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qcom,bus-max-ddr7 = <11>;
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qcom,bus-freq-ddr8 = <10>;
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qcom,bus-min-ddr8 = <10>;
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qcom,bus-max-ddr8 = <11>;
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qcom,acd-level = <0x882b5ffd>;
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};
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <608000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
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qcom,bus-freq-ddr7 = <8>;
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qcom,bus-min-ddr7 = <7>;
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qcom,bus-max-ddr7 = <11>;
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qcom,bus-freq-ddr8 = <7>;
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||||
qcom,bus-min-ddr8 = <7>;
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qcom,bus-max-ddr8 = <11>;
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||||
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qcom,acd-level = <0xa82b5ffd>;
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};
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <540000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq-ddr7 = <8>;
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||||
qcom,bus-min-ddr7 = <7>;
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||||
qcom,bus-max-ddr7 = <10>;
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||||
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qcom,bus-freq-ddr8 = <7>;
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||||
qcom,bus-min-ddr8 = <7>;
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qcom,bus-max-ddr8 = <9>;
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||||
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qcom,acd-level = <0xa82c5ffd>;
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};
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <491000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
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qcom,bus-freq-ddr7 = <8>;
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qcom,bus-min-ddr7 = <6>;
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qcom,bus-max-ddr7 = <10>;
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qcom,bus-freq-ddr8 = <7>;
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qcom,bus-min-ddr8 = <5>;
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qcom,bus-max-ddr8 = <7>;
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||||
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qcom,acd-level = <0xa82c5ffd>;
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};
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <443000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq-ddr7 = <8>;
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qcom,bus-min-ddr7 = <6>;
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qcom,bus-max-ddr7 = <10>;
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qcom,bus-freq-ddr8 = <7>;
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qcom,bus-min-ddr8 = <5>;
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qcom,bus-max-ddr8 = <7>;
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qcom,acd-level = <0xa82d5ffd>;
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};
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qcom,gpu-pwrlevel@8 {
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reg = <8>;
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qcom,gpu-freq = <379000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
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qcom,bus-freq-ddr7 = <8>;
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qcom,bus-min-ddr7 = <6>;
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qcom,bus-max-ddr7 = <10>;
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||||
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qcom,bus-freq-ddr8 = <6>;
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qcom,bus-min-ddr8 = <5>;
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qcom,bus-max-ddr8 = <7>;
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qcom,acd-level = <0x882e5ffd>;
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};
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qcom,gpu-pwrlevel@9 {
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reg = <9>;
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qcom,gpu-freq = <315000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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||||
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qcom,bus-freq-ddr7 = <2>;
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||||
qcom,bus-min-ddr7 = <2>;
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qcom,bus-max-ddr7 = <9>;
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||||
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qcom,bus-freq-ddr8 = <2>;
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qcom,bus-min-ddr8 = <2>;
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qcom,bus-max-ddr8 = <7>;
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qcom,acd-level = <0x882f5ffd>;
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};
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qcom,acd-level = <0x882a5ffd>;
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};
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <778000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,gpu-pwrlevels-1 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <1>;
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qcom,initial-pwrlevel = <10>;
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qcom,bus-freq-ddr7 = <11>;
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qcom,bus-min-ddr7 = <11>;
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qcom,bus-max-ddr7 = <11>;
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <900000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
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||||
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||||
qcom,bus-freq-ddr8 = <11>;
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||||
qcom,bus-min-ddr8 = <11>;
|
||||
qcom,bus-max-ddr8 = <11>;
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||||
qcom,bus-freq-ddr7 = <11>;
|
||||
qcom,bus-min-ddr7 = <11>;
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||||
qcom,bus-max-ddr7 = <11>;
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||||
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||||
qcom,acd-level = <0xa82a5ffd>;
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||||
};
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||||
qcom,bus-freq-ddr8 = <11>;
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||||
qcom,bus-min-ddr8 = <11>;
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qcom,bus-max-ddr8 = <11>;
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||||
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||||
qcom,gpu-pwrlevel@2 {
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reg = <2>;
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||||
qcom,gpu-freq = <738000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,acd-level = <0x882a5ffd>;
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};
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||||
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qcom,bus-freq-ddr7 = <11>;
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||||
qcom,bus-min-ddr7 = <11>;
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qcom,bus-max-ddr7 = <11>;
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||||
qcom,gpu-pwrlevel@1 {
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||||
reg = <1>;
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||||
qcom,gpu-freq = <840000000>;
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||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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||||
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||||
qcom,bus-freq-ddr8 = <11>;
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||||
qcom,bus-min-ddr8 = <11>;
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||||
qcom,bus-max-ddr8 = <11>;
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||||
qcom,bus-freq-ddr7 = <11>;
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||||
qcom,bus-min-ddr7 = <11>;
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||||
qcom,bus-max-ddr7 = <11>;
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||||
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||||
qcom,acd-level = <0xa82a5ffd>;
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||||
};
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||||
qcom,bus-freq-ddr8 = <11>;
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||||
qcom,bus-min-ddr8 = <11>;
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qcom,bus-max-ddr8 = <11>;
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <676000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,acd-level = <0x882a5ffd>;
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||||
};
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||||
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qcom,bus-freq-ddr7 = <11>;
|
||||
qcom,bus-min-ddr7 = <11>;
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||||
qcom,bus-max-ddr7 = <11>;
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||||
qcom,gpu-pwrlevel@2 {
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reg = <2>;
|
||||
qcom,gpu-freq = <778000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <10>;
|
||||
qcom,bus-min-ddr8 = <10>;
|
||||
qcom,bus-max-ddr8 = <11>;
|
||||
qcom,bus-freq-ddr7 = <11>;
|
||||
qcom,bus-min-ddr7 = <11>;
|
||||
qcom,bus-max-ddr7 = <11>;
|
||||
|
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qcom,acd-level = <0x882b5ffd>;
|
||||
};
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qcom,bus-freq-ddr8 = <11>;
|
||||
qcom,bus-min-ddr8 = <11>;
|
||||
qcom,bus-max-ddr8 = <11>;
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||||
|
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <608000000>;
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||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
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||||
qcom,acd-level = <0xa82a5ffd>;
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||||
};
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||||
|
||||
qcom,bus-freq-ddr7 = <8>;
|
||||
qcom,bus-min-ddr7 = <7>;
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||||
qcom,bus-max-ddr7 = <11>;
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||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
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||||
qcom,gpu-freq = <738000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <7>;
|
||||
qcom,bus-min-ddr8 = <7>;
|
||||
qcom,bus-max-ddr8 = <11>;
|
||||
qcom,bus-freq-ddr7 = <11>;
|
||||
qcom,bus-min-ddr7 = <11>;
|
||||
qcom,bus-max-ddr7 = <11>;
|
||||
|
||||
qcom,acd-level = <0xa82b5ffd>;
|
||||
};
|
||||
qcom,bus-freq-ddr8 = <11>;
|
||||
qcom,bus-min-ddr8 = <11>;
|
||||
qcom,bus-max-ddr8 = <11>;
|
||||
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <540000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,acd-level = <0xa82a5ffd>;
|
||||
};
|
||||
|
||||
qcom,bus-freq-ddr7 = <8>;
|
||||
qcom,bus-min-ddr7 = <7>;
|
||||
qcom,bus-max-ddr7 = <10>;
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <676000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <7>;
|
||||
qcom,bus-min-ddr8 = <7>;
|
||||
qcom,bus-max-ddr8 = <9>;
|
||||
qcom,bus-freq-ddr7 = <11>;
|
||||
qcom,bus-min-ddr7 = <11>;
|
||||
qcom,bus-max-ddr7 = <11>;
|
||||
|
||||
qcom,acd-level = <0xa82c5ffd>;
|
||||
};
|
||||
qcom,bus-freq-ddr8 = <10>;
|
||||
qcom,bus-min-ddr8 = <10>;
|
||||
qcom,bus-max-ddr8 = <11>;
|
||||
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <491000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
||||
qcom,acd-level = <0x882b5ffd>;
|
||||
};
|
||||
|
||||
qcom,bus-freq-ddr7 = <8>;
|
||||
qcom,bus-min-ddr7 = <6>;
|
||||
qcom,bus-max-ddr7 = <10>;
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <608000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <7>;
|
||||
qcom,bus-min-ddr8 = <5>;
|
||||
qcom,bus-max-ddr8 = <7>;
|
||||
qcom,bus-freq-ddr7 = <8>;
|
||||
qcom,bus-min-ddr7 = <7>;
|
||||
qcom,bus-max-ddr7 = <11>;
|
||||
|
||||
qcom,acd-level = <0xa82c5ffd>;
|
||||
};
|
||||
qcom,bus-freq-ddr8 = <7>;
|
||||
qcom,bus-min-ddr8 = <7>;
|
||||
qcom,bus-max-ddr8 = <11>;
|
||||
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <443000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,acd-level = <0xa82b5ffd>;
|
||||
};
|
||||
|
||||
qcom,bus-freq-ddr7 = <8>;
|
||||
qcom,bus-min-ddr7 = <6>;
|
||||
qcom,bus-max-ddr7 = <10>;
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <540000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <7>;
|
||||
qcom,bus-min-ddr8 = <5>;
|
||||
qcom,bus-max-ddr8 = <7>;
|
||||
qcom,bus-freq-ddr7 = <8>;
|
||||
qcom,bus-min-ddr7 = <7>;
|
||||
qcom,bus-max-ddr7 = <10>;
|
||||
|
||||
qcom,acd-level = <0xa82d5ffd>;
|
||||
};
|
||||
qcom,bus-freq-ddr8 = <7>;
|
||||
qcom,bus-min-ddr8 = <7>;
|
||||
qcom,bus-max-ddr8 = <9>;
|
||||
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <379000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
|
||||
qcom,acd-level = <0xa82c5ffd>;
|
||||
};
|
||||
|
||||
qcom,bus-freq-ddr7 = <8>;
|
||||
qcom,bus-min-ddr7 = <6>;
|
||||
qcom,bus-max-ddr7 = <10>;
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <491000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <6>;
|
||||
qcom,bus-min-ddr8 = <5>;
|
||||
qcom,bus-max-ddr8 = <7>;
|
||||
qcom,bus-freq-ddr7 = <8>;
|
||||
qcom,bus-min-ddr7 = <6>;
|
||||
qcom,bus-max-ddr7 = <10>;
|
||||
|
||||
qcom,acd-level = <0x882e5ffd>;
|
||||
};
|
||||
qcom,bus-freq-ddr8 = <7>;
|
||||
qcom,bus-min-ddr8 = <5>;
|
||||
qcom,bus-max-ddr8 = <7>;
|
||||
|
||||
qcom,gpu-pwrlevel@9 {
|
||||
reg = <9>;
|
||||
qcom,gpu-freq = <315000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
qcom,acd-level = <0xa82c5ffd>;
|
||||
};
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <9>;
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <443000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <2>;
|
||||
qcom,bus-min-ddr8 = <2>;
|
||||
qcom,bus-max-ddr8 = <7>;
|
||||
qcom,bus-freq-ddr7 = <8>;
|
||||
qcom,bus-min-ddr7 = <6>;
|
||||
qcom,bus-max-ddr7 = <10>;
|
||||
|
||||
qcom,acd-level = <0x882f5ffd>;
|
||||
qcom,bus-freq-ddr8 = <7>;
|
||||
qcom,bus-min-ddr8 = <5>;
|
||||
qcom,bus-max-ddr8 = <7>;
|
||||
|
||||
qcom,acd-level = <0xa82d5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@9 {
|
||||
reg = <9>;
|
||||
qcom,gpu-freq = <379000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <8>;
|
||||
qcom,bus-min-ddr7 = <6>;
|
||||
qcom,bus-max-ddr7 = <10>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <6>;
|
||||
qcom,bus-min-ddr8 = <5>;
|
||||
qcom,bus-max-ddr8 = <7>;
|
||||
|
||||
qcom,acd-level = <0x882e5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@10 {
|
||||
reg = <10>;
|
||||
qcom,gpu-freq = <315000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <9>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <2>;
|
||||
qcom,bus-min-ddr8 = <2>;
|
||||
qcom,bus-max-ddr8 = <7>;
|
||||
|
||||
qcom,acd-level = <0x882f5ffd>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -5659,6 +5659,20 @@
|
|||
qcom,use-ap-power-save;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qfprom: qfprom@784000 {
|
||||
compatible = "qcom,qfprom";
|
||||
reg = <0x784000 0x3000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
read-only;
|
||||
ranges;
|
||||
|
||||
gpu_speed_bin: gpu_speed_bin@17b {
|
||||
reg = <0x17b 0x1>;
|
||||
bits = <5 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "ipcc-test.dtsi"
|
||||
|
|
|
|||
Loading…
Reference in a new issue