mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-30 11:41:38 -04:00
The common clk framework changes for 3.6 include a small number of core
framework improvments, platform ports and new DT bindings. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJQDyNXAAoJEDqPOy9afJhJYT8QAMXV2AcB/nF3iOesjj7dZlCB qjEDd+fbISQMsvBrj9r4+rSktNWS451I46Yob4lfgfd7aVGD7iA8EK7kd11aSIx7 fjEfYuCoIBqdl0RJqXrKnXuoO/lKoX7kHdwdYj0BOZRDHoJs4CTpQaEhsTG2Ahp8 Sn7LmqMFe+hfIIL8gCn9/R0dUa8kGjFlNMN9y4hW01oPYRBNW0m6C9Af3SJlrJ0d Besk6c5Q6GHpuwJvir4kw9cghOXIzdJRFO4t9XkVBCWqQTSDhbIObOL9svLljJn/ OS4HKbvEpT1pY0P63qqzTv6o6VA3zGK+nt/oqa1T7EuZXktBS+G/eRNjAPEQx1BL bkLoM2zeSZ4zc/rWGrTk/rLGRSlzcHn1O+fy2P9RwtzhkIzN1FhxWd96FAWpFXsD VglwsB/WHQnZpi5VoQTtfqhBne6wo7BdNYpqrvYthG1OjsLgvqdK34HPESzvI+C1 k9BpLBLkUmfejJeu9Ox28hOlq92WVAqrZPOBSdcM3nyTenYG9JWM+OUytKs+Ph7a j8eSopG/Obe63BCTq5lpBJ6gOgjNK7DrmDZPwEDjSe+w/pE08/41uyNgEmzExxs8 1RQusSJAh6pJblixFYosrXtDsrU2HneJhR5aOFHKrHfqrXZ2bPoG/ut7wBr1opZF YJFNnvJ5zTbmku4HiEz8 =V8ad -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.linaro.org/people/mturquette/linux Pull common clk framework changes from Michael Turquette: "This includes a small number of core framework improvments, platform ports and new DT bindings." Fix up trivial conflicts in drivers/clk/Makefile * tag 'clk-for-linus' of git://git.linaro.org/people/mturquette/linux: (21 commits) clk: fix compile for OF && !COMMON_CLK clk: fix clk_get on of_clk_get_by_name return check clk: mxs: clk_register_clkdev mx28 usb clocks clk: add highbank clock support dt: add clock binding doc to primecell bindings clk: add DT fixed-clock binding support clk: add DT clock binding support ARM: integrator: convert to common clock clk: add versatile ICST307 driver ARM: integrator: put symbolic bus names on devices ARM: u300: convert to common clock clk: cache parent clocks only for muxes clk: wm831x: Add initial WM831x clock driver clk: Constify struct clk_init_data clk: Add CLK_IS_BASIC flag to identify basic clocks clk: Add support for rate table based dividers clk: Add support for power of two type dividers clk: mxs: imx28: decrease the frequency of ref_io1 for SSP2 and SSP3 clk: mxs: add clkdev lookup for pwm clk: mxs: Fix the GPMI clock name ...
This commit is contained in:
Linus Torvalds
commit
9161c3b796
42 changed files with 2536 additions and 1824 deletions
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@ -34,4 +34,11 @@ config COMMON_CLK_DEBUG
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clk_flags, clk_prepare_count, clk_enable_count &
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clk_notifier_count.
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config COMMON_CLK_WM831X
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tristate "Clock driver for WM831x/2x PMICs"
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depends on MFD_WM831X
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---help---
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Supports the clocking subsystem of the WM831x/2x series of
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PMICs from Wolfson Microlectronics.
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endmenu
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@ -1,9 +1,15 @@
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# common clock types
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obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
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obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \
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clk-mux.o clk-divider.o clk-fixed-factor.o
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# SoCs specific
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obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
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obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
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obj-$(CONFIG_ARCH_MXS) += mxs/
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obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
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obj-$(CONFIG_PLAT_SPEAR) += spear/
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obj-$(CONFIG_ARCH_U300) += clk-u300.o
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obj-$(CONFIG_ARCH_INTEGRATOR) += versatile/
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# Chip specific
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obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
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@ -30,18 +30,89 @@
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#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
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#define div_mask(d) ((1 << (d->width)) - 1)
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#define is_power_of_two(i) !(i & ~i)
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static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
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{
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unsigned int maxdiv = 0;
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->div > maxdiv)
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maxdiv = clkt->div;
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return maxdiv;
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}
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static unsigned int _get_maxdiv(struct clk_divider *divider)
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{
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if (divider->flags & CLK_DIVIDER_ONE_BASED)
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return div_mask(divider);
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if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
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return 1 << div_mask(divider);
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if (divider->table)
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return _get_table_maxdiv(divider->table);
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return div_mask(divider) + 1;
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}
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static unsigned int _get_table_div(const struct clk_div_table *table,
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unsigned int val)
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{
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->val == val)
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return clkt->div;
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return 0;
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}
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static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
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{
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if (divider->flags & CLK_DIVIDER_ONE_BASED)
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return val;
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if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
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return 1 << val;
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if (divider->table)
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return _get_table_div(divider->table, val);
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return val + 1;
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}
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static unsigned int _get_table_val(const struct clk_div_table *table,
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unsigned int div)
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{
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->div == div)
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return clkt->val;
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return 0;
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}
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static unsigned int _get_val(struct clk_divider *divider, u8 div)
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{
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if (divider->flags & CLK_DIVIDER_ONE_BASED)
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return div;
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if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
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return __ffs(div);
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if (divider->table)
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return _get_table_val(divider->table, div);
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return div - 1;
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}
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static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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unsigned int div;
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unsigned int div, val;
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div = readl(divider->reg) >> divider->shift;
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div &= div_mask(divider);
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val = readl(divider->reg) >> divider->shift;
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val &= div_mask(divider);
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if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
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div++;
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div = _get_div(divider, val);
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if (!div) {
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WARN(1, "%s: Invalid divisor for clock %s\n", __func__,
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__clk_get_name(hw->clk));
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return parent_rate;
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}
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return parent_rate / div;
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}
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@ -52,6 +123,26 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
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*/
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#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
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static bool _is_valid_table_div(const struct clk_div_table *table,
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unsigned int div)
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{
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->div == div)
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return true;
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return false;
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}
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static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
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{
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if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
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return is_power_of_two(div);
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if (divider->table)
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return _is_valid_table_div(divider->table, div);
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return true;
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}
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static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
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unsigned long *best_parent_rate)
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{
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@ -62,10 +153,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
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if (!rate)
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rate = 1;
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maxdiv = (1 << divider->width);
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if (divider->flags & CLK_DIVIDER_ONE_BASED)
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maxdiv--;
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maxdiv = _get_maxdiv(divider);
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if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
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parent_rate = *best_parent_rate;
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@ -82,6 +170,8 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
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maxdiv = min(ULONG_MAX / rate, maxdiv);
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for (i = 1; i <= maxdiv; i++) {
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if (!_is_valid_div(divider, i))
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continue;
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parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
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MULT_ROUND_UP(rate, i));
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now = parent_rate / i;
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@ -93,9 +183,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
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}
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if (!bestdiv) {
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bestdiv = (1 << divider->width);
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if (divider->flags & CLK_DIVIDER_ONE_BASED)
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bestdiv--;
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bestdiv = _get_maxdiv(divider);
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*best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
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}
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@ -115,24 +203,22 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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unsigned int div;
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unsigned int div, value;
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unsigned long flags = 0;
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u32 val;
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div = parent_rate / rate;
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value = _get_val(divider, div);
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if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
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div--;
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if (div > div_mask(divider))
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div = div_mask(divider);
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if (value > div_mask(divider))
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value = div_mask(divider);
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if (divider->lock)
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spin_lock_irqsave(divider->lock, flags);
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val = readl(divider->reg);
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val &= ~(div_mask(divider) << divider->shift);
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val |= div << divider->shift;
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val |= value << divider->shift;
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writel(val, divider->reg);
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if (divider->lock)
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@ -148,6 +234,47 @@ const struct clk_ops clk_divider_ops = {
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};
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EXPORT_SYMBOL_GPL(clk_divider_ops);
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static struct clk *_register_divider(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags, const struct clk_div_table *table,
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spinlock_t *lock)
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{
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struct clk_divider *div;
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struct clk *clk;
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struct clk_init_data init;
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/* allocate the divider */
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div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
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if (!div) {
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pr_err("%s: could not allocate divider clk\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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init.name = name;
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init.ops = &clk_divider_ops;
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init.flags = flags | CLK_IS_BASIC;
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init.parent_names = (parent_name ? &parent_name: NULL);
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init.num_parents = (parent_name ? 1 : 0);
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/* struct clk_divider assignments */
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div->reg = reg;
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div->shift = shift;
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div->width = width;
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div->flags = clk_divider_flags;
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div->lock = lock;
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div->hw.init = &init;
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div->table = table;
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/* register the clock */
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clk = clk_register(dev, &div->hw);
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if (IS_ERR(clk))
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kfree(div);
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return clk;
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}
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/**
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* clk_register_divider - register a divider clock with the clock framework
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* @dev: device registering this clock
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@ -165,36 +292,30 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags, spinlock_t *lock)
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{
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struct clk_divider *div;
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struct clk *clk;
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struct clk_init_data init;
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/* allocate the divider */
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div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
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if (!div) {
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pr_err("%s: could not allocate divider clk\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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init.name = name;
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init.ops = &clk_divider_ops;
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init.flags = flags;
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init.parent_names = (parent_name ? &parent_name: NULL);
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init.num_parents = (parent_name ? 1 : 0);
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/* struct clk_divider assignments */
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div->reg = reg;
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div->shift = shift;
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div->width = width;
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div->flags = clk_divider_flags;
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div->lock = lock;
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div->hw.init = &init;
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/* register the clock */
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clk = clk_register(dev, &div->hw);
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if (IS_ERR(clk))
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kfree(div);
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return clk;
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return _register_divider(dev, name, parent_name, flags, reg, shift,
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width, clk_divider_flags, NULL, lock);
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}
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/**
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* clk_register_divider_table - register a table based divider clock with
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* the clock framework
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* @dev: device registering this clock
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* @name: name of this clock
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* @parent_name: name of clock's parent
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* @flags: framework-specific flags
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* @reg: register address to adjust divider
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* @shift: number of bits to shift the bitfield
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* @width: width of the bitfield
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* @clk_divider_flags: divider-specific flags for this clock
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* @table: array of divider/value pairs ending with a div set to 0
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* @lock: shared register lock for this clock
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*/
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struct clk *clk_register_divider_table(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags, const struct clk_div_table *table,
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spinlock_t *lock)
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{
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return _register_divider(dev, name, parent_name, flags, reg, shift,
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width, clk_divider_flags, table, lock);
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}
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|
|
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|
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@ -82,7 +82,7 @@ struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
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init.name = name;
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init.ops = &clk_fixed_factor_ops;
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init.flags = flags;
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init.flags = flags | CLK_IS_BASIC;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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|
|
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@ -14,6 +14,7 @@
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/of.h>
|
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/*
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* DOC: basic fixed-rate clock that cannot gate
|
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@ -63,7 +64,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
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|
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init.name = name;
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init.ops = &clk_fixed_rate_ops;
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init.flags = flags;
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init.flags = flags | CLK_IS_BASIC;
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init.parent_names = (parent_name ? &parent_name: NULL);
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init.num_parents = (parent_name ? 1 : 0);
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|
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@ -79,3 +80,25 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
|
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|
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return clk;
|
||||
}
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||||
|
||||
#ifdef CONFIG_OF
|
||||
/**
|
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* of_fixed_clk_setup() - Setup function for simple fixed rate clock
|
||||
*/
|
||||
void __init of_fixed_clk_setup(struct device_node *node)
|
||||
{
|
||||
struct clk *clk;
|
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const char *clk_name = node->name;
|
||||
u32 rate;
|
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|
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if (of_property_read_u32(node, "clock-frequency", &rate))
|
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return;
|
||||
|
||||
of_property_read_string(node, "clock-output-names", &clk_name);
|
||||
|
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clk = clk_register_fixed_rate(NULL, clk_name, NULL, CLK_IS_ROOT, rate);
|
||||
if (clk)
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_fixed_clk_setup);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -130,7 +130,7 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
|
|||
|
||||
init.name = name;
|
||||
init.ops = &clk_gate_ops;
|
||||
init.flags = flags;
|
||||
init.flags = flags | CLK_IS_BASIC;
|
||||
init.parent_names = (parent_name ? &parent_name: NULL);
|
||||
init.num_parents = (parent_name ? 1 : 0);
|
||||
|
||||
|
|
|
|||
346
drivers/clk/clk-highbank.c
Normal file
346
drivers/clk/clk-highbank.c
Normal file
|
|
@ -0,0 +1,346 @@
|
|||
/*
|
||||
* Copyright 2011-2012 Calxeda, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
extern void __iomem *sregs_base;
|
||||
|
||||
#define HB_PLL_LOCK_500 0x20000000
|
||||
#define HB_PLL_LOCK 0x10000000
|
||||
#define HB_PLL_DIVF_SHIFT 20
|
||||
#define HB_PLL_DIVF_MASK 0x0ff00000
|
||||
#define HB_PLL_DIVQ_SHIFT 16
|
||||
#define HB_PLL_DIVQ_MASK 0x00070000
|
||||
#define HB_PLL_DIVR_SHIFT 8
|
||||
#define HB_PLL_DIVR_MASK 0x00001f00
|
||||
#define HB_PLL_RANGE_SHIFT 4
|
||||
#define HB_PLL_RANGE_MASK 0x00000070
|
||||
#define HB_PLL_BYPASS 0x00000008
|
||||
#define HB_PLL_RESET 0x00000004
|
||||
#define HB_PLL_EXT_BYPASS 0x00000002
|
||||
#define HB_PLL_EXT_ENA 0x00000001
|
||||
|
||||
#define HB_PLL_VCO_MIN_FREQ 2133000000
|
||||
#define HB_PLL_MAX_FREQ HB_PLL_VCO_MIN_FREQ
|
||||
#define HB_PLL_MIN_FREQ (HB_PLL_VCO_MIN_FREQ / 64)
|
||||
|
||||
#define HB_A9_BCLK_DIV_MASK 0x00000006
|
||||
#define HB_A9_BCLK_DIV_SHIFT 1
|
||||
#define HB_A9_PCLK_DIV 0x00000001
|
||||
|
||||
struct hb_clk {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg;
|
||||
char *parent_name;
|
||||
};
|
||||
#define to_hb_clk(p) container_of(p, struct hb_clk, hw)
|
||||
|
||||
static int clk_pll_prepare(struct clk_hw *hwclk)
|
||||
{
|
||||
struct hb_clk *hbclk = to_hb_clk(hwclk);
|
||||
u32 reg;
|
||||
|
||||
reg = readl(hbclk->reg);
|
||||
reg &= ~HB_PLL_RESET;
|
||||
writel(reg, hbclk->reg);
|
||||
|
||||
while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
|
||||
;
|
||||
while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
|
||||
;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void clk_pll_unprepare(struct clk_hw *hwclk)
|
||||
{
|
||||
struct hb_clk *hbclk = to_hb_clk(hwclk);
|
||||
u32 reg;
|
||||
|
||||
reg = readl(hbclk->reg);
|
||||
reg |= HB_PLL_RESET;
|
||||
writel(reg, hbclk->reg);
|
||||
}
|
||||
|
||||
static int clk_pll_enable(struct clk_hw *hwclk)
|
||||
{
|
||||
struct hb_clk *hbclk = to_hb_clk(hwclk);
|
||||
u32 reg;
|
||||
|
||||
reg = readl(hbclk->reg);
|
||||
reg |= HB_PLL_EXT_ENA;
|
||||
writel(reg, hbclk->reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void clk_pll_disable(struct clk_hw *hwclk)
|
||||
{
|
||||
struct hb_clk *hbclk = to_hb_clk(hwclk);
|
||||
u32 reg;
|
||||
|
||||
reg = readl(hbclk->reg);
|
||||
reg &= ~HB_PLL_EXT_ENA;
|
||||
writel(reg, hbclk->reg);
|
||||
}
|
||||
|
||||
static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct hb_clk *hbclk = to_hb_clk(hwclk);
|
||||
unsigned long divf, divq, vco_freq, reg;
|
||||
|
||||
reg = readl(hbclk->reg);
|
||||
if (reg & HB_PLL_EXT_BYPASS)
|
||||
return parent_rate;
|
||||
|
||||
divf = (reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT;
|
||||
divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT;
|
||||
vco_freq = parent_rate * (divf + 1);
|
||||
|
||||
return vco_freq / (1 << divq);
|
||||
}
|
||||
|
||||
static void clk_pll_calc(unsigned long rate, unsigned long ref_freq,
|
||||
u32 *pdivq, u32 *pdivf)
|
||||
{
|
||||
u32 divq, divf;
|
||||
unsigned long vco_freq;
|
||||
|
||||
if (rate < HB_PLL_MIN_FREQ)
|
||||
rate = HB_PLL_MIN_FREQ;
|
||||
if (rate > HB_PLL_MAX_FREQ)
|
||||
rate = HB_PLL_MAX_FREQ;
|
||||
|
||||
for (divq = 1; divq <= 6; divq++) {
|
||||
if ((rate * (1 << divq)) >= HB_PLL_VCO_MIN_FREQ)
|
||||
break;
|
||||
}
|
||||
|
||||
vco_freq = rate * (1 << divq);
|
||||
divf = (vco_freq + (ref_freq / 2)) / ref_freq;
|
||||
divf--;
|
||||
|
||||
*pdivq = divq;
|
||||
*pdivf = divf;
|
||||
}
|
||||
|
||||
static long clk_pll_round_rate(struct clk_hw *hwclk, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
u32 divq, divf;
|
||||
unsigned long ref_freq = *parent_rate;
|
||||
|
||||
clk_pll_calc(rate, ref_freq, &divq, &divf);
|
||||
|
||||
return (ref_freq * (divf + 1)) / (1 << divq);
|
||||
}
|
||||
|
||||
static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct hb_clk *hbclk = to_hb_clk(hwclk);
|
||||
u32 divq, divf;
|
||||
u32 reg;
|
||||
|
||||
clk_pll_calc(rate, parent_rate, &divq, &divf);
|
||||
|
||||
reg = readl(hbclk->reg);
|
||||
if (divf != ((reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT)) {
|
||||
/* Need to re-lock PLL, so put it into bypass mode */
|
||||
reg |= HB_PLL_EXT_BYPASS;
|
||||
writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
|
||||
|
||||
writel(reg | HB_PLL_RESET, hbclk->reg);
|
||||
reg &= ~(HB_PLL_DIVF_MASK | HB_PLL_DIVQ_MASK);
|
||||
reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT);
|
||||
writel(reg | HB_PLL_RESET, hbclk->reg);
|
||||
writel(reg, hbclk->reg);
|
||||
|
||||
while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
|
||||
;
|
||||
while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
|
||||
;
|
||||
reg |= HB_PLL_EXT_ENA;
|
||||
reg &= ~HB_PLL_EXT_BYPASS;
|
||||
} else {
|
||||
reg &= ~HB_PLL_DIVQ_MASK;
|
||||
reg |= divq << HB_PLL_DIVQ_SHIFT;
|
||||
}
|
||||
writel(reg, hbclk->reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops clk_pll_ops = {
|
||||
.prepare = clk_pll_prepare,
|
||||
.unprepare = clk_pll_unprepare,
|
||||
.enable = clk_pll_enable,
|
||||
.disable = clk_pll_disable,
|
||||
.recalc_rate = clk_pll_recalc_rate,
|
||||
.round_rate = clk_pll_round_rate,
|
||||
.set_rate = clk_pll_set_rate,
|
||||
};
|
||||
|
||||
static unsigned long clk_cpu_periphclk_recalc_rate(struct clk_hw *hwclk,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct hb_clk *hbclk = to_hb_clk(hwclk);
|
||||
u32 div = (readl(hbclk->reg) & HB_A9_PCLK_DIV) ? 8 : 4;
|
||||
return parent_rate / div;
|
||||
}
|
||||
|
||||
static const struct clk_ops a9periphclk_ops = {
|
||||
.recalc_rate = clk_cpu_periphclk_recalc_rate,
|
||||
};
|
||||
|
||||
static unsigned long clk_cpu_a9bclk_recalc_rate(struct clk_hw *hwclk,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct hb_clk *hbclk = to_hb_clk(hwclk);
|
||||
u32 div = (readl(hbclk->reg) & HB_A9_BCLK_DIV_MASK) >> HB_A9_BCLK_DIV_SHIFT;
|
||||
|
||||
return parent_rate / (div + 2);
|
||||
}
|
||||
|
||||
static const struct clk_ops a9bclk_ops = {
|
||||
.recalc_rate = clk_cpu_a9bclk_recalc_rate,
|
||||
};
|
||||
|
||||
static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct hb_clk *hbclk = to_hb_clk(hwclk);
|
||||
u32 div;
|
||||
|
||||
div = readl(hbclk->reg) & 0x1f;
|
||||
div++;
|
||||
div *= 2;
|
||||
|
||||
return parent_rate / div;
|
||||
}
|
||||
|
||||
static long clk_periclk_round_rate(struct clk_hw *hwclk, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
u32 div;
|
||||
|
||||
div = *parent_rate / rate;
|
||||
div++;
|
||||
div &= ~0x1;
|
||||
|
||||
return *parent_rate / div;
|
||||
}
|
||||
|
||||
static int clk_periclk_set_rate(struct clk_hw *hwclk, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct hb_clk *hbclk = to_hb_clk(hwclk);
|
||||
u32 div;
|
||||
|
||||
div = parent_rate / rate;
|
||||
if (div & 0x1)
|
||||
return -EINVAL;
|
||||
|
||||
writel(div >> 1, hbclk->reg);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops periclk_ops = {
|
||||
.recalc_rate = clk_periclk_recalc_rate,
|
||||
.round_rate = clk_periclk_round_rate,
|
||||
.set_rate = clk_periclk_set_rate,
|
||||
};
|
||||
|
||||
static __init struct clk *hb_clk_init(struct device_node *node, const struct clk_ops *ops)
|
||||
{
|
||||
u32 reg;
|
||||
struct clk *clk;
|
||||
struct hb_clk *hb_clk;
|
||||
const char *clk_name = node->name;
|
||||
const char *parent_name;
|
||||
struct clk_init_data init;
|
||||
int rc;
|
||||
|
||||
rc = of_property_read_u32(node, "reg", ®);
|
||||
if (WARN_ON(rc))
|
||||
return NULL;
|
||||
|
||||
hb_clk = kzalloc(sizeof(*hb_clk), GFP_KERNEL);
|
||||
if (WARN_ON(!hb_clk))
|
||||
return NULL;
|
||||
|
||||
hb_clk->reg = sregs_base + reg;
|
||||
|
||||
of_property_read_string(node, "clock-output-names", &clk_name);
|
||||
|
||||
init.name = clk_name;
|
||||
init.ops = ops;
|
||||
init.flags = 0;
|
||||
parent_name = of_clk_get_parent_name(node, 0);
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
hb_clk->hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &hb_clk->hw);
|
||||
if (WARN_ON(IS_ERR(clk))) {
|
||||
kfree(hb_clk);
|
||||
return NULL;
|
||||
}
|
||||
rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
return clk;
|
||||
}
|
||||
|
||||
static void __init hb_pll_init(struct device_node *node)
|
||||
{
|
||||
hb_clk_init(node, &clk_pll_ops);
|
||||
}
|
||||
|
||||
static void __init hb_a9periph_init(struct device_node *node)
|
||||
{
|
||||
hb_clk_init(node, &a9periphclk_ops);
|
||||
}
|
||||
|
||||
static void __init hb_a9bus_init(struct device_node *node)
|
||||
{
|
||||
struct clk *clk = hb_clk_init(node, &a9bclk_ops);
|
||||
clk_prepare_enable(clk);
|
||||
}
|
||||
|
||||
static void __init hb_emmc_init(struct device_node *node)
|
||||
{
|
||||
hb_clk_init(node, &periclk_ops);
|
||||
}
|
||||
|
||||
static const __initconst struct of_device_id clk_match[] = {
|
||||
{ .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
|
||||
{ .compatible = "calxeda,hb-pll-clock", .data = hb_pll_init, },
|
||||
{ .compatible = "calxeda,hb-a9periph-clock", .data = hb_a9periph_init, },
|
||||
{ .compatible = "calxeda,hb-a9bus-clock", .data = hb_a9bus_init, },
|
||||
{ .compatible = "calxeda,hb-emmc-clock", .data = hb_emmc_init, },
|
||||
{}
|
||||
};
|
||||
|
||||
void __init highbank_clocks_init(void)
|
||||
{
|
||||
of_clk_init(clk_match);
|
||||
}
|
||||
|
|
@ -106,7 +106,7 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
|
|||
|
||||
init.name = name;
|
||||
init.ops = &clk_mux_ops;
|
||||
init.flags = flags;
|
||||
init.flags = flags | CLK_IS_BASIC;
|
||||
init.parent_names = parent_names;
|
||||
init.num_parents = num_parents;
|
||||
|
||||
|
|
|
|||
746
drivers/clk/clk-u300.c
Normal file
746
drivers/clk/clk-u300.c
Normal file
|
|
@ -0,0 +1,746 @@
|
|||
/*
|
||||
* U300 clock implementation
|
||||
* Copyright (C) 2007-2012 ST-Ericsson AB
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
* Author: Linus Walleij <linus.walleij@stericsson.com>
|
||||
* Author: Jonas Aaberg <jonas.aberg@stericsson.com>
|
||||
*/
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <mach/syscon.h>
|
||||
|
||||
/*
|
||||
* The clocking hierarchy currently looks like this.
|
||||
* NOTE: the idea is NOT to show how the clocks are routed on the chip!
|
||||
* The ideas is to show dependencies, so a clock higher up in the
|
||||
* hierarchy has to be on in order for another clock to be on. Now,
|
||||
* both CPU and DMA can actually be on top of the hierarchy, and that
|
||||
* is not modeled currently. Instead we have the backbone AMBA bus on
|
||||
* top. This bus cannot be programmed in any way but conceptually it
|
||||
* needs to be active for the bridges and devices to transport data.
|
||||
*
|
||||
* Please be aware that a few clocks are hw controlled, which mean that
|
||||
* the hw itself can turn on/off or change the rate of the clock when
|
||||
* needed!
|
||||
*
|
||||
* AMBA bus
|
||||
* |
|
||||
* +- CPU
|
||||
* +- FSMC NANDIF NAND Flash interface
|
||||
* +- SEMI Shared Memory interface
|
||||
* +- ISP Image Signal Processor (U335 only)
|
||||
* +- CDS (U335 only)
|
||||
* +- DMA Direct Memory Access Controller
|
||||
* +- AAIF APP/ACC Inteface (Mobile Scalable Link, MSL)
|
||||
* +- APEX
|
||||
* +- VIDEO_ENC AVE2/3 Video Encoder
|
||||
* +- XGAM Graphics Accelerator Controller
|
||||
* +- AHB
|
||||
* |
|
||||
* +- ahb:0 AHB Bridge
|
||||
* | |
|
||||
* | +- ahb:1 INTCON Interrupt controller
|
||||
* | +- ahb:3 MSPRO Memory Stick Pro controller
|
||||
* | +- ahb:4 EMIF External Memory interface
|
||||
* |
|
||||
* +- fast:0 FAST bridge
|
||||
* | |
|
||||
* | +- fast:1 MMCSD MMC/SD card reader controller
|
||||
* | +- fast:2 I2S0 PCM I2S channel 0 controller
|
||||
* | +- fast:3 I2S1 PCM I2S channel 1 controller
|
||||
* | +- fast:4 I2C0 I2C channel 0 controller
|
||||
* | +- fast:5 I2C1 I2C channel 1 controller
|
||||
* | +- fast:6 SPI SPI controller
|
||||
* | +- fast:7 UART1 Secondary UART (U335 only)
|
||||
* |
|
||||
* +- slow:0 SLOW bridge
|
||||
* |
|
||||
* +- slow:1 SYSCON (not possible to control)
|
||||
* +- slow:2 WDOG Watchdog
|
||||
* +- slow:3 UART0 primary UART
|
||||
* +- slow:4 TIMER_APP Application timer - used in Linux
|
||||
* +- slow:5 KEYPAD controller
|
||||
* +- slow:6 GPIO controller
|
||||
* +- slow:7 RTC controller
|
||||
* +- slow:8 BT Bus Tracer (not used currently)
|
||||
* +- slow:9 EH Event Handler (not used currently)
|
||||
* +- slow:a TIMER_ACC Access style timer (not used currently)
|
||||
* +- slow:b PPM (U335 only, what is that?)
|
||||
*/
|
||||
|
||||
/* Global syscon virtual base */
|
||||
static void __iomem *syscon_vbase;
|
||||
|
||||
/**
|
||||
* struct clk_syscon - U300 syscon clock
|
||||
* @hw: corresponding clock hardware entry
|
||||
* @hw_ctrld: whether this clock is hardware controlled (for refcount etc)
|
||||
* and does not need any magic pokes to be enabled/disabled
|
||||
* @reset: state holder, whether this block's reset line is asserted or not
|
||||
* @res_reg: reset line enable/disable flag register
|
||||
* @res_bit: bit for resetting or taking this consumer out of reset
|
||||
* @en_reg: clock line enable/disable flag register
|
||||
* @en_bit: bit for enabling/disabling this consumer clock line
|
||||
* @clk_val: magic value to poke in the register to enable/disable
|
||||
* this one clock
|
||||
*/
|
||||
struct clk_syscon {
|
||||
struct clk_hw hw;
|
||||
bool hw_ctrld;
|
||||
bool reset;
|
||||
void __iomem *res_reg;
|
||||
u8 res_bit;
|
||||
void __iomem *en_reg;
|
||||
u8 en_bit;
|
||||
u16 clk_val;
|
||||
};
|
||||
|
||||
#define to_syscon(_hw) container_of(_hw, struct clk_syscon, hw)
|
||||
|
||||
static DEFINE_SPINLOCK(syscon_resetreg_lock);
|
||||
|
||||
/*
|
||||
* Reset control functions. We remember if a block has been
|
||||
* taken out of reset and don't remove the reset assertion again
|
||||
* and vice versa. Currently we only remove resets so the
|
||||
* enablement function is defined out.
|
||||
*/
|
||||
static void syscon_block_reset_enable(struct clk_syscon *sclk)
|
||||
{
|
||||
unsigned long iflags;
|
||||
u16 val;
|
||||
|
||||
/* Not all blocks support resetting */
|
||||
if (!sclk->res_reg)
|
||||
return;
|
||||
spin_lock_irqsave(&syscon_resetreg_lock, iflags);
|
||||
val = readw(sclk->res_reg);
|
||||
val |= BIT(sclk->res_bit);
|
||||
writew(val, sclk->res_reg);
|
||||
spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
|
||||
sclk->reset = true;
|
||||
}
|
||||
|
||||
static void syscon_block_reset_disable(struct clk_syscon *sclk)
|
||||
{
|
||||
unsigned long iflags;
|
||||
u16 val;
|
||||
|
||||
/* Not all blocks support resetting */
|
||||
if (!sclk->res_reg)
|
||||
return;
|
||||
spin_lock_irqsave(&syscon_resetreg_lock, iflags);
|
||||
val = readw(sclk->res_reg);
|
||||
val &= ~BIT(sclk->res_bit);
|
||||
writew(val, sclk->res_reg);
|
||||
spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
|
||||
sclk->reset = false;
|
||||
}
|
||||
|
||||
static int syscon_clk_prepare(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_syscon *sclk = to_syscon(hw);
|
||||
|
||||
/* If the block is in reset, bring it out */
|
||||
if (sclk->reset)
|
||||
syscon_block_reset_disable(sclk);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void syscon_clk_unprepare(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_syscon *sclk = to_syscon(hw);
|
||||
|
||||
/* Please don't force the console into reset */
|
||||
if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)
|
||||
return;
|
||||
/* When unpreparing, force block into reset */
|
||||
if (!sclk->reset)
|
||||
syscon_block_reset_enable(sclk);
|
||||
}
|
||||
|
||||
static int syscon_clk_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_syscon *sclk = to_syscon(hw);
|
||||
|
||||
/* Don't touch the hardware controlled clocks */
|
||||
if (sclk->hw_ctrld)
|
||||
return 0;
|
||||
/* These cannot be controlled */
|
||||
if (sclk->clk_val == 0xFFFFU)
|
||||
return 0;
|
||||
|
||||
writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCER);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void syscon_clk_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_syscon *sclk = to_syscon(hw);
|
||||
|
||||
/* Don't touch the hardware controlled clocks */
|
||||
if (sclk->hw_ctrld)
|
||||
return;
|
||||
if (sclk->clk_val == 0xFFFFU)
|
||||
return;
|
||||
/* Please don't disable the console port */
|
||||
if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)
|
||||
return;
|
||||
|
||||
writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCDR);
|
||||
}
|
||||
|
||||
static int syscon_clk_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_syscon *sclk = to_syscon(hw);
|
||||
u16 val;
|
||||
|
||||
/* If no enable register defined, it's always-on */
|
||||
if (!sclk->en_reg)
|
||||
return 1;
|
||||
|
||||
val = readw(sclk->en_reg);
|
||||
val &= BIT(sclk->en_bit);
|
||||
|
||||
return val ? 1 : 0;
|
||||
}
|
||||
|
||||
static u16 syscon_get_perf(void)
|
||||
{
|
||||
u16 val;
|
||||
|
||||
val = readw(syscon_vbase + U300_SYSCON_CCR);
|
||||
val &= U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
|
||||
return val;
|
||||
}
|
||||
|
||||
static unsigned long
|
||||
syscon_clk_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_syscon *sclk = to_syscon(hw);
|
||||
u16 perf = syscon_get_perf();
|
||||
|
||||
switch(sclk->clk_val) {
|
||||
case U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN:
|
||||
case U300_SYSCON_SBCER_I2C0_CLK_EN:
|
||||
case U300_SYSCON_SBCER_I2C1_CLK_EN:
|
||||
case U300_SYSCON_SBCER_MMC_CLK_EN:
|
||||
case U300_SYSCON_SBCER_SPI_CLK_EN:
|
||||
/* The FAST clocks have one progression */
|
||||
switch(perf) {
|
||||
case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
|
||||
case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
|
||||
return 13000000;
|
||||
default:
|
||||
return parent_rate; /* 26 MHz */
|
||||
}
|
||||
case U300_SYSCON_SBCER_DMAC_CLK_EN:
|
||||
case U300_SYSCON_SBCER_NANDIF_CLK_EN:
|
||||
case U300_SYSCON_SBCER_XGAM_CLK_EN:
|
||||
/* AMBA interconnect peripherals */
|
||||
switch(perf) {
|
||||
case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
|
||||
case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
|
||||
return 6500000;
|
||||
case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
|
||||
return 26000000;
|
||||
default:
|
||||
return parent_rate; /* 52 MHz */
|
||||
}
|
||||
case U300_SYSCON_SBCER_SEMI_CLK_EN:
|
||||
case U300_SYSCON_SBCER_EMIF_CLK_EN:
|
||||
/* EMIF speeds */
|
||||
switch(perf) {
|
||||
case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
|
||||
case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
|
||||
return 13000000;
|
||||
case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
|
||||
return 52000000;
|
||||
default:
|
||||
return 104000000;
|
||||
}
|
||||
case U300_SYSCON_SBCER_CPU_CLK_EN:
|
||||
/* And the fast CPU clock */
|
||||
switch(perf) {
|
||||
case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
|
||||
case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
|
||||
return 13000000;
|
||||
case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
|
||||
return 52000000;
|
||||
case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
|
||||
return 104000000;
|
||||
default:
|
||||
return parent_rate; /* 208 MHz */
|
||||
}
|
||||
default:
|
||||
/*
|
||||
* The SLOW clocks and default just inherit the rate of
|
||||
* their parent (typically PLL13 13 MHz).
|
||||
*/
|
||||
return parent_rate;
|
||||
}
|
||||
}
|
||||
|
||||
static long
|
||||
syscon_clk_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
struct clk_syscon *sclk = to_syscon(hw);
|
||||
|
||||
if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)
|
||||
return *prate;
|
||||
/* We really only support setting the rate of the CPU clock */
|
||||
if (rate <= 13000000)
|
||||
return 13000000;
|
||||
if (rate <= 52000000)
|
||||
return 52000000;
|
||||
if (rate <= 104000000)
|
||||
return 104000000;
|
||||
return 208000000;
|
||||
}
|
||||
|
||||
static int syscon_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_syscon *sclk = to_syscon(hw);
|
||||
u16 val;
|
||||
|
||||
/* We only support setting the rate of the CPU clock */
|
||||
if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)
|
||||
return -EINVAL;
|
||||
switch (rate) {
|
||||
case 13000000:
|
||||
val = U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER;
|
||||
break;
|
||||
case 52000000:
|
||||
val = U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE;
|
||||
break;
|
||||
case 104000000:
|
||||
val = U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH;
|
||||
break;
|
||||
case 208000000:
|
||||
val = U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
val |= readw(syscon_vbase + U300_SYSCON_CCR) &
|
||||
~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK ;
|
||||
writew(val, syscon_vbase + U300_SYSCON_CCR);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops syscon_clk_ops = {
|
||||
.prepare = syscon_clk_prepare,
|
||||
.unprepare = syscon_clk_unprepare,
|
||||
.enable = syscon_clk_enable,
|
||||
.disable = syscon_clk_disable,
|
||||
.is_enabled = syscon_clk_is_enabled,
|
||||
.recalc_rate = syscon_clk_recalc_rate,
|
||||
.round_rate = syscon_clk_round_rate,
|
||||
.set_rate = syscon_clk_set_rate,
|
||||
};
|
||||
|
||||
static struct clk * __init
|
||||
syscon_clk_register(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
bool hw_ctrld,
|
||||
void __iomem *res_reg, u8 res_bit,
|
||||
void __iomem *en_reg, u8 en_bit,
|
||||
u16 clk_val)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_syscon *sclk;
|
||||
struct clk_init_data init;
|
||||
|
||||
sclk = kzalloc(sizeof(struct clk_syscon), GFP_KERNEL);
|
||||
if (!sclk) {
|
||||
pr_err("could not allocate syscon clock %s\n",
|
||||
name);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
init.name = name;
|
||||
init.ops = &syscon_clk_ops;
|
||||
init.flags = flags;
|
||||
init.parent_names = (parent_name ? &parent_name : NULL);
|
||||
init.num_parents = (parent_name ? 1 : 0);
|
||||
sclk->hw.init = &init;
|
||||
sclk->hw_ctrld = hw_ctrld;
|
||||
/* Assume the block is in reset at registration */
|
||||
sclk->reset = true;
|
||||
sclk->res_reg = res_reg;
|
||||
sclk->res_bit = res_bit;
|
||||
sclk->en_reg = en_reg;
|
||||
sclk->en_bit = en_bit;
|
||||
sclk->clk_val = clk_val;
|
||||
|
||||
clk = clk_register(dev, &sclk->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(sclk);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
/**
|
||||
* struct clk_mclk - U300 MCLK clock (MMC/SD clock)
|
||||
* @hw: corresponding clock hardware entry
|
||||
* @is_mspro: if this is the memory stick clock rather than MMC/SD
|
||||
*/
|
||||
struct clk_mclk {
|
||||
struct clk_hw hw;
|
||||
bool is_mspro;
|
||||
};
|
||||
|
||||
#define to_mclk(_hw) container_of(_hw, struct clk_mclk, hw)
|
||||
|
||||
static int mclk_clk_prepare(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_mclk *mclk = to_mclk(hw);
|
||||
u16 val;
|
||||
|
||||
/* The MMC and MSPRO clocks need some special set-up */
|
||||
if (!mclk->is_mspro) {
|
||||
/* Set default MMC clock divisor to 18.9 MHz */
|
||||
writew(0x0054U, syscon_vbase + U300_SYSCON_MMF0R);
|
||||
val = readw(syscon_vbase + U300_SYSCON_MMCR);
|
||||
/* Disable the MMC feedback clock */
|
||||
val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
|
||||
/* Disable MSPRO frequency */
|
||||
val &= ~U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
|
||||
writew(val, syscon_vbase + U300_SYSCON_MMCR);
|
||||
} else {
|
||||
val = readw(syscon_vbase + U300_SYSCON_MMCR);
|
||||
/* Disable the MMC feedback clock */
|
||||
val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
|
||||
/* Enable MSPRO frequency */
|
||||
val |= U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
|
||||
writew(val, syscon_vbase + U300_SYSCON_MMCR);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned long
|
||||
mclk_clk_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
u16 perf = syscon_get_perf();
|
||||
|
||||
switch (perf) {
|
||||
case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
|
||||
/*
|
||||
* Here, the 208 MHz PLL gets shut down and the always
|
||||
* on 13 MHz PLL used for RTC etc kicks into use
|
||||
* instead.
|
||||
*/
|
||||
return 13000000;
|
||||
case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
|
||||
case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
|
||||
case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
|
||||
case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
|
||||
{
|
||||
/*
|
||||
* This clock is under program control. The register is
|
||||
* divided in two nybbles, bit 7-4 gives cycles-1 to count
|
||||
* high, bit 3-0 gives cycles-1 to count low. Distribute
|
||||
* these with no more than 1 cycle difference between
|
||||
* low and high and add low and high to get the actual
|
||||
* divisor. The base PLL is 208 MHz. Writing 0x00 will
|
||||
* divide by 1 and 1 so the highest frequency possible
|
||||
* is 104 MHz.
|
||||
*
|
||||
* e.g. 0x54 =>
|
||||
* f = 208 / ((5+1) + (4+1)) = 208 / 11 = 18.9 MHz
|
||||
*/
|
||||
u16 val = readw(syscon_vbase + U300_SYSCON_MMF0R) &
|
||||
U300_SYSCON_MMF0R_MASK;
|
||||
switch (val) {
|
||||
case 0x0054:
|
||||
return 18900000;
|
||||
case 0x0044:
|
||||
return 20800000;
|
||||
case 0x0043:
|
||||
return 23100000;
|
||||
case 0x0033:
|
||||
return 26000000;
|
||||
case 0x0032:
|
||||
return 29700000;
|
||||
case 0x0022:
|
||||
return 34700000;
|
||||
case 0x0021:
|
||||
return 41600000;
|
||||
case 0x0011:
|
||||
return 52000000;
|
||||
case 0x0000:
|
||||
return 104000000;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return parent_rate;
|
||||
}
|
||||
|
||||
static long
|
||||
mclk_clk_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
if (rate <= 18900000)
|
||||
return 18900000;
|
||||
if (rate <= 20800000)
|
||||
return 20800000;
|
||||
if (rate <= 23100000)
|
||||
return 23100000;
|
||||
if (rate <= 26000000)
|
||||
return 26000000;
|
||||
if (rate <= 29700000)
|
||||
return 29700000;
|
||||
if (rate <= 34700000)
|
||||
return 34700000;
|
||||
if (rate <= 41600000)
|
||||
return 41600000;
|
||||
/* Highest rate */
|
||||
return 52000000;
|
||||
}
|
||||
|
||||
static int mclk_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
u16 val;
|
||||
u16 reg;
|
||||
|
||||
switch (rate) {
|
||||
case 18900000:
|
||||
val = 0x0054;
|
||||
break;
|
||||
case 20800000:
|
||||
val = 0x0044;
|
||||
break;
|
||||
case 23100000:
|
||||
val = 0x0043;
|
||||
break;
|
||||
case 26000000:
|
||||
val = 0x0033;
|
||||
break;
|
||||
case 29700000:
|
||||
val = 0x0032;
|
||||
break;
|
||||
case 34700000:
|
||||
val = 0x0022;
|
||||
break;
|
||||
case 41600000:
|
||||
val = 0x0021;
|
||||
break;
|
||||
case 52000000:
|
||||
val = 0x0011;
|
||||
break;
|
||||
case 104000000:
|
||||
val = 0x0000;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
reg = readw(syscon_vbase + U300_SYSCON_MMF0R) &
|
||||
~U300_SYSCON_MMF0R_MASK;
|
||||
writew(reg | val, syscon_vbase + U300_SYSCON_MMF0R);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops mclk_ops = {
|
||||
.prepare = mclk_clk_prepare,
|
||||
.recalc_rate = mclk_clk_recalc_rate,
|
||||
.round_rate = mclk_clk_round_rate,
|
||||
.set_rate = mclk_clk_set_rate,
|
||||
};
|
||||
|
||||
static struct clk * __init
|
||||
mclk_clk_register(struct device *dev, const char *name,
|
||||
const char *parent_name, bool is_mspro)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_mclk *mclk;
|
||||
struct clk_init_data init;
|
||||
|
||||
mclk = kzalloc(sizeof(struct clk_mclk), GFP_KERNEL);
|
||||
if (!mclk) {
|
||||
pr_err("could not allocate MMC/SD clock %s\n",
|
||||
name);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
init.name = "mclk";
|
||||
init.ops = &mclk_ops;
|
||||
init.flags = 0;
|
||||
init.parent_names = (parent_name ? &parent_name : NULL);
|
||||
init.num_parents = (parent_name ? 1 : 0);
|
||||
mclk->hw.init = &init;
|
||||
mclk->is_mspro = is_mspro;
|
||||
|
||||
clk = clk_register(dev, &mclk->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(mclk);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
void __init u300_clk_init(void __iomem *base)
|
||||
{
|
||||
u16 val;
|
||||
struct clk *clk;
|
||||
|
||||
syscon_vbase = base;
|
||||
|
||||
/* Set system to run at PLL208, max performance, a known state. */
|
||||
val = readw(syscon_vbase + U300_SYSCON_CCR);
|
||||
val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
|
||||
writew(val, syscon_vbase + U300_SYSCON_CCR);
|
||||
/* Wait for the PLL208 to lock if not locked in yet */
|
||||
while (!(readw(syscon_vbase + U300_SYSCON_CSR) &
|
||||
U300_SYSCON_CSR_PLL208_LOCK_IND));
|
||||
|
||||
/* Power management enable */
|
||||
val = readw(syscon_vbase + U300_SYSCON_PMCR);
|
||||
val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
|
||||
writew(val, syscon_vbase + U300_SYSCON_PMCR);
|
||||
|
||||
/* These are always available (RTC and PLL13) */
|
||||
clk = clk_register_fixed_rate(NULL, "app_32_clk", NULL,
|
||||
CLK_IS_ROOT, 32768);
|
||||
/* The watchdog sits directly on the 32 kHz clock */
|
||||
clk_register_clkdev(clk, NULL, "coh901327_wdog");
|
||||
clk = clk_register_fixed_rate(NULL, "pll13", NULL,
|
||||
CLK_IS_ROOT, 13000000);
|
||||
|
||||
/* These derive from PLL208 */
|
||||
clk = clk_register_fixed_rate(NULL, "pll208", NULL,
|
||||
CLK_IS_ROOT, 208000000);
|
||||
clk = clk_register_fixed_factor(NULL, "app_208_clk", "pll208",
|
||||
0, 1, 1);
|
||||
clk = clk_register_fixed_factor(NULL, "app_104_clk", "pll208",
|
||||
0, 1, 2);
|
||||
clk = clk_register_fixed_factor(NULL, "app_52_clk", "pll208",
|
||||
0, 1, 4);
|
||||
/* The 52 MHz is divided down to 26 MHz */
|
||||
clk = clk_register_fixed_factor(NULL, "app_26_clk", "app_52_clk",
|
||||
0, 1, 2);
|
||||
|
||||
/* Directly on the AMBA interconnect */
|
||||
clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true,
|
||||
syscon_vbase + U300_SYSCON_RRR, 3,
|
||||
syscon_vbase + U300_SYSCON_CERR, 3,
|
||||
U300_SYSCON_SBCER_CPU_CLK_EN);
|
||||
clk = syscon_clk_register(NULL, "dmac_clk", "app_52_clk", 0, true,
|
||||
syscon_vbase + U300_SYSCON_RRR, 4,
|
||||
syscon_vbase + U300_SYSCON_CERR, 4,
|
||||
U300_SYSCON_SBCER_DMAC_CLK_EN);
|
||||
clk_register_clkdev(clk, NULL, "dma");
|
||||
clk = syscon_clk_register(NULL, "fsmc_clk", "app_52_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RRR, 6,
|
||||
syscon_vbase + U300_SYSCON_CERR, 6,
|
||||
U300_SYSCON_SBCER_NANDIF_CLK_EN);
|
||||
clk_register_clkdev(clk, NULL, "fsmc-nand");
|
||||
clk = syscon_clk_register(NULL, "xgam_clk", "app_52_clk", 0, true,
|
||||
syscon_vbase + U300_SYSCON_RRR, 8,
|
||||
syscon_vbase + U300_SYSCON_CERR, 8,
|
||||
U300_SYSCON_SBCER_XGAM_CLK_EN);
|
||||
clk_register_clkdev(clk, NULL, "xgam");
|
||||
clk = syscon_clk_register(NULL, "semi_clk", "app_104_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RRR, 9,
|
||||
syscon_vbase + U300_SYSCON_CERR, 9,
|
||||
U300_SYSCON_SBCER_SEMI_CLK_EN);
|
||||
clk_register_clkdev(clk, NULL, "semi");
|
||||
|
||||
/* AHB bridge clocks */
|
||||
clk = syscon_clk_register(NULL, "ahb_subsys_clk", "app_52_clk", 0, true,
|
||||
syscon_vbase + U300_SYSCON_RRR, 10,
|
||||
syscon_vbase + U300_SYSCON_CERR, 10,
|
||||
U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN);
|
||||
clk = syscon_clk_register(NULL, "intcon_clk", "ahb_subsys_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RRR, 12,
|
||||
syscon_vbase + U300_SYSCON_CERR, 12,
|
||||
/* Cannot be enabled, just taken out of reset */
|
||||
0xFFFFU);
|
||||
clk_register_clkdev(clk, NULL, "intcon");
|
||||
clk = syscon_clk_register(NULL, "emif_clk", "ahb_subsys_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RRR, 5,
|
||||
syscon_vbase + U300_SYSCON_CERR, 5,
|
||||
U300_SYSCON_SBCER_EMIF_CLK_EN);
|
||||
clk_register_clkdev(clk, NULL, "pl172");
|
||||
|
||||
/* FAST bridge clocks */
|
||||
clk = syscon_clk_register(NULL, "fast_clk", "app_26_clk", 0, true,
|
||||
syscon_vbase + U300_SYSCON_RFR, 0,
|
||||
syscon_vbase + U300_SYSCON_CEFR, 0,
|
||||
U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN);
|
||||
clk = syscon_clk_register(NULL, "i2c0_p_clk", "fast_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RFR, 1,
|
||||
syscon_vbase + U300_SYSCON_CEFR, 1,
|
||||
U300_SYSCON_SBCER_I2C0_CLK_EN);
|
||||
clk_register_clkdev(clk, NULL, "stu300.0");
|
||||
clk = syscon_clk_register(NULL, "i2c1_p_clk", "fast_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RFR, 2,
|
||||
syscon_vbase + U300_SYSCON_CEFR, 2,
|
||||
U300_SYSCON_SBCER_I2C1_CLK_EN);
|
||||
clk_register_clkdev(clk, NULL, "stu300.1");
|
||||
clk = syscon_clk_register(NULL, "mmc_p_clk", "fast_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RFR, 5,
|
||||
syscon_vbase + U300_SYSCON_CEFR, 5,
|
||||
U300_SYSCON_SBCER_MMC_CLK_EN);
|
||||
clk_register_clkdev(clk, "apb_pclk", "mmci");
|
||||
clk = syscon_clk_register(NULL, "spi_p_clk", "fast_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RFR, 6,
|
||||
syscon_vbase + U300_SYSCON_CEFR, 6,
|
||||
U300_SYSCON_SBCER_SPI_CLK_EN);
|
||||
/* The SPI has no external clock for the outward bus, uses the pclk */
|
||||
clk_register_clkdev(clk, NULL, "pl022");
|
||||
clk_register_clkdev(clk, "apb_pclk", "pl022");
|
||||
|
||||
/* SLOW bridge clocks */
|
||||
clk = syscon_clk_register(NULL, "slow_clk", "pll13", 0, true,
|
||||
syscon_vbase + U300_SYSCON_RSR, 0,
|
||||
syscon_vbase + U300_SYSCON_CESR, 0,
|
||||
U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN);
|
||||
clk = syscon_clk_register(NULL, "uart0_clk", "slow_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RSR, 1,
|
||||
syscon_vbase + U300_SYSCON_CESR, 1,
|
||||
U300_SYSCON_SBCER_UART_CLK_EN);
|
||||
/* Same clock is used for APB and outward bus */
|
||||
clk_register_clkdev(clk, NULL, "uart0");
|
||||
clk_register_clkdev(clk, "apb_pclk", "uart0");
|
||||
clk = syscon_clk_register(NULL, "gpio_clk", "slow_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RSR, 4,
|
||||
syscon_vbase + U300_SYSCON_CESR, 4,
|
||||
U300_SYSCON_SBCER_GPIO_CLK_EN);
|
||||
clk_register_clkdev(clk, NULL, "u300-gpio");
|
||||
clk = syscon_clk_register(NULL, "keypad_clk", "slow_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RSR, 5,
|
||||
syscon_vbase + U300_SYSCON_CESR, 6,
|
||||
U300_SYSCON_SBCER_KEYPAD_CLK_EN);
|
||||
clk_register_clkdev(clk, NULL, "coh901461-keypad");
|
||||
clk = syscon_clk_register(NULL, "rtc_clk", "slow_clk", 0, true,
|
||||
syscon_vbase + U300_SYSCON_RSR, 6,
|
||||
/* No clock enable register bit */
|
||||
NULL, 0, 0xFFFFU);
|
||||
clk_register_clkdev(clk, NULL, "rtc-coh901331");
|
||||
clk = syscon_clk_register(NULL, "app_tmr_clk", "slow_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RSR, 7,
|
||||
syscon_vbase + U300_SYSCON_CESR, 7,
|
||||
U300_SYSCON_SBCER_APP_TMR_CLK_EN);
|
||||
clk_register_clkdev(clk, NULL, "apptimer");
|
||||
clk = syscon_clk_register(NULL, "acc_tmr_clk", "slow_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RSR, 8,
|
||||
syscon_vbase + U300_SYSCON_CESR, 8,
|
||||
U300_SYSCON_SBCER_ACC_TMR_CLK_EN);
|
||||
clk_register_clkdev(clk, NULL, "timer");
|
||||
|
||||
/* Then this special MMC/SD clock */
|
||||
clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false);
|
||||
clk_register_clkdev(clk, NULL, "mmci");
|
||||
}
|
||||
428
drivers/clk/clk-wm831x.c
Normal file
428
drivers/clk/clk-wm831x.c
Normal file
|
|
@ -0,0 +1,428 @@
|
|||
/*
|
||||
* WM831x clock control
|
||||
*
|
||||
* Copyright 2011-2 Wolfson Microelectronics PLC.
|
||||
*
|
||||
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/mfd/wm831x/core.h>
|
||||
|
||||
struct wm831x_clk {
|
||||
struct wm831x *wm831x;
|
||||
struct clk_hw xtal_hw;
|
||||
struct clk_hw fll_hw;
|
||||
struct clk_hw clkout_hw;
|
||||
struct clk *xtal;
|
||||
struct clk *fll;
|
||||
struct clk *clkout;
|
||||
bool xtal_ena;
|
||||
};
|
||||
|
||||
static int wm831x_xtal_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
|
||||
xtal_hw);
|
||||
|
||||
return clkdata->xtal_ena;
|
||||
}
|
||||
|
||||
static unsigned long wm831x_xtal_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
|
||||
xtal_hw);
|
||||
|
||||
if (clkdata->xtal_ena)
|
||||
return 32768;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops wm831x_xtal_ops = {
|
||||
.is_enabled = wm831x_xtal_is_enabled,
|
||||
.recalc_rate = wm831x_xtal_recalc_rate,
|
||||
};
|
||||
|
||||
static struct clk_init_data wm831x_xtal_init = {
|
||||
.name = "xtal",
|
||||
.ops = &wm831x_xtal_ops,
|
||||
.flags = CLK_IS_ROOT,
|
||||
};
|
||||
|
||||
static const unsigned long wm831x_fll_auto_rates[] = {
|
||||
2048000,
|
||||
11289600,
|
||||
12000000,
|
||||
12288000,
|
||||
19200000,
|
||||
22579600,
|
||||
24000000,
|
||||
24576000,
|
||||
};
|
||||
|
||||
static int wm831x_fll_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
|
||||
fll_hw);
|
||||
struct wm831x *wm831x = clkdata->wm831x;
|
||||
int ret;
|
||||
|
||||
ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_1);
|
||||
if (ret < 0) {
|
||||
dev_err(wm831x->dev, "Unable to read FLL_CONTROL_1: %d\n",
|
||||
ret);
|
||||
return true;
|
||||
}
|
||||
|
||||
return (ret & WM831X_FLL_ENA) != 0;
|
||||
}
|
||||
|
||||
static int wm831x_fll_prepare(struct clk_hw *hw)
|
||||
{
|
||||
struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
|
||||
fll_hw);
|
||||
struct wm831x *wm831x = clkdata->wm831x;
|
||||
int ret;
|
||||
|
||||
ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_2,
|
||||
WM831X_FLL_ENA, WM831X_FLL_ENA);
|
||||
if (ret != 0)
|
||||
dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret);
|
||||
|
||||
usleep_range(2000, 2000);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void wm831x_fll_unprepare(struct clk_hw *hw)
|
||||
{
|
||||
struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
|
||||
fll_hw);
|
||||
struct wm831x *wm831x = clkdata->wm831x;
|
||||
int ret;
|
||||
|
||||
ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_2, WM831X_FLL_ENA, 0);
|
||||
if (ret != 0)
|
||||
dev_crit(wm831x->dev, "Failed to disaable FLL: %d\n", ret);
|
||||
}
|
||||
|
||||
static unsigned long wm831x_fll_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
|
||||
fll_hw);
|
||||
struct wm831x *wm831x = clkdata->wm831x;
|
||||
int ret;
|
||||
|
||||
ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
|
||||
if (ret < 0) {
|
||||
dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
|
||||
ret);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (ret & WM831X_FLL_AUTO)
|
||||
return wm831x_fll_auto_rates[ret & WM831X_FLL_AUTO_FREQ_MASK];
|
||||
|
||||
dev_err(wm831x->dev, "FLL only supported in AUTO mode\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static long wm831x_fll_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *unused)
|
||||
{
|
||||
int best = 0;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++)
|
||||
if (abs(wm831x_fll_auto_rates[i] - rate) <
|
||||
abs(wm831x_fll_auto_rates[best] - rate))
|
||||
best = i;
|
||||
|
||||
return wm831x_fll_auto_rates[best];
|
||||
}
|
||||
|
||||
static int wm831x_fll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
|
||||
fll_hw);
|
||||
struct wm831x *wm831x = clkdata->wm831x;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++)
|
||||
if (wm831x_fll_auto_rates[i] == rate)
|
||||
break;
|
||||
if (i == ARRAY_SIZE(wm831x_fll_auto_rates))
|
||||
return -EINVAL;
|
||||
|
||||
if (wm831x_fll_is_enabled(hw))
|
||||
return -EPERM;
|
||||
|
||||
return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_2,
|
||||
WM831X_FLL_AUTO_FREQ_MASK, i);
|
||||
}
|
||||
|
||||
static const char *wm831x_fll_parents[] = {
|
||||
"xtal",
|
||||
"clkin",
|
||||
};
|
||||
|
||||
static u8 wm831x_fll_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
|
||||
fll_hw);
|
||||
struct wm831x *wm831x = clkdata->wm831x;
|
||||
int ret;
|
||||
|
||||
/* AUTO mode is always clocked from the crystal */
|
||||
ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
|
||||
if (ret < 0) {
|
||||
dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
|
||||
ret);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (ret & WM831X_FLL_AUTO)
|
||||
return 0;
|
||||
|
||||
ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_5);
|
||||
if (ret < 0) {
|
||||
dev_err(wm831x->dev, "Unable to read FLL_CONTROL_5: %d\n",
|
||||
ret);
|
||||
return 0;
|
||||
}
|
||||
|
||||
switch (ret & WM831X_FLL_CLK_SRC_MASK) {
|
||||
case 0:
|
||||
return 0;
|
||||
case 1:
|
||||
return 1;
|
||||
default:
|
||||
dev_err(wm831x->dev, "Unsupported FLL clock source %d\n",
|
||||
ret & WM831X_FLL_CLK_SRC_MASK);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct clk_ops wm831x_fll_ops = {
|
||||
.is_enabled = wm831x_fll_is_enabled,
|
||||
.prepare = wm831x_fll_prepare,
|
||||
.unprepare = wm831x_fll_unprepare,
|
||||
.round_rate = wm831x_fll_round_rate,
|
||||
.recalc_rate = wm831x_fll_recalc_rate,
|
||||
.set_rate = wm831x_fll_set_rate,
|
||||
.get_parent = wm831x_fll_get_parent,
|
||||
};
|
||||
|
||||
static struct clk_init_data wm831x_fll_init = {
|
||||
.name = "fll",
|
||||
.ops = &wm831x_fll_ops,
|
||||
.parent_names = wm831x_fll_parents,
|
||||
.num_parents = ARRAY_SIZE(wm831x_fll_parents),
|
||||
.flags = CLK_SET_RATE_GATE,
|
||||
};
|
||||
|
||||
static int wm831x_clkout_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
|
||||
clkout_hw);
|
||||
struct wm831x *wm831x = clkdata->wm831x;
|
||||
int ret;
|
||||
|
||||
ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
|
||||
if (ret < 0) {
|
||||
dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",
|
||||
ret);
|
||||
return true;
|
||||
}
|
||||
|
||||
return (ret & WM831X_CLKOUT_ENA) != 0;
|
||||
}
|
||||
|
||||
static int wm831x_clkout_prepare(struct clk_hw *hw)
|
||||
{
|
||||
struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
|
||||
clkout_hw);
|
||||
struct wm831x *wm831x = clkdata->wm831x;
|
||||
int ret;
|
||||
|
||||
ret = wm831x_reg_unlock(wm831x);
|
||||
if (ret != 0) {
|
||||
dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
|
||||
WM831X_CLKOUT_ENA, WM831X_CLKOUT_ENA);
|
||||
if (ret != 0)
|
||||
dev_crit(wm831x->dev, "Failed to enable CLKOUT: %d\n", ret);
|
||||
|
||||
wm831x_reg_lock(wm831x);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void wm831x_clkout_unprepare(struct clk_hw *hw)
|
||||
{
|
||||
struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
|
||||
clkout_hw);
|
||||
struct wm831x *wm831x = clkdata->wm831x;
|
||||
int ret;
|
||||
|
||||
ret = wm831x_reg_unlock(wm831x);
|
||||
if (ret != 0) {
|
||||
dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
|
||||
WM831X_CLKOUT_ENA, 0);
|
||||
if (ret != 0)
|
||||
dev_crit(wm831x->dev, "Failed to disable CLKOUT: %d\n", ret);
|
||||
|
||||
wm831x_reg_lock(wm831x);
|
||||
}
|
||||
|
||||
static const char *wm831x_clkout_parents[] = {
|
||||
"xtal",
|
||||
"fll",
|
||||
};
|
||||
|
||||
static u8 wm831x_clkout_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
|
||||
clkout_hw);
|
||||
struct wm831x *wm831x = clkdata->wm831x;
|
||||
int ret;
|
||||
|
||||
ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
|
||||
if (ret < 0) {
|
||||
dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",
|
||||
ret);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (ret & WM831X_CLKOUT_SRC)
|
||||
return 0;
|
||||
else
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int wm831x_clkout_set_parent(struct clk_hw *hw, u8 parent)
|
||||
{
|
||||
struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
|
||||
clkout_hw);
|
||||
struct wm831x *wm831x = clkdata->wm831x;
|
||||
|
||||
return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
|
||||
WM831X_CLKOUT_SRC,
|
||||
parent << WM831X_CLKOUT_SRC_SHIFT);
|
||||
}
|
||||
|
||||
static const struct clk_ops wm831x_clkout_ops = {
|
||||
.is_enabled = wm831x_clkout_is_enabled,
|
||||
.prepare = wm831x_clkout_prepare,
|
||||
.unprepare = wm831x_clkout_unprepare,
|
||||
.get_parent = wm831x_clkout_get_parent,
|
||||
.set_parent = wm831x_clkout_set_parent,
|
||||
};
|
||||
|
||||
static struct clk_init_data wm831x_clkout_init = {
|
||||
.name = "clkout",
|
||||
.ops = &wm831x_clkout_ops,
|
||||
.parent_names = wm831x_clkout_parents,
|
||||
.num_parents = ARRAY_SIZE(wm831x_clkout_parents),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
};
|
||||
|
||||
static __devinit int wm831x_clk_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
|
||||
struct wm831x_clk *clkdata;
|
||||
int ret;
|
||||
|
||||
clkdata = devm_kzalloc(&pdev->dev, sizeof(*clkdata), GFP_KERNEL);
|
||||
if (!clkdata)
|
||||
return -ENOMEM;
|
||||
|
||||
/* XTAL_ENA can only be set via OTP/InstantConfig so just read once */
|
||||
ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
|
||||
if (ret < 0) {
|
||||
dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
clkdata->xtal_ena = ret & WM831X_XTAL_ENA;
|
||||
|
||||
clkdata->xtal_hw.init = &wm831x_xtal_init;
|
||||
clkdata->xtal = clk_register(&pdev->dev, &clkdata->xtal_hw);
|
||||
if (!clkdata->xtal)
|
||||
return -EINVAL;
|
||||
|
||||
clkdata->fll_hw.init = &wm831x_fll_init;
|
||||
clkdata->fll = clk_register(&pdev->dev, &clkdata->fll_hw);
|
||||
if (!clkdata->fll) {
|
||||
ret = -EINVAL;
|
||||
goto err_xtal;
|
||||
}
|
||||
|
||||
clkdata->clkout_hw.init = &wm831x_clkout_init;
|
||||
clkdata->clkout = clk_register(&pdev->dev, &clkdata->clkout_hw);
|
||||
if (!clkdata->clkout) {
|
||||
ret = -EINVAL;
|
||||
goto err_fll;
|
||||
}
|
||||
|
||||
dev_set_drvdata(&pdev->dev, clkdata);
|
||||
|
||||
return 0;
|
||||
|
||||
err_fll:
|
||||
clk_unregister(clkdata->fll);
|
||||
err_xtal:
|
||||
clk_unregister(clkdata->xtal);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __devexit wm831x_clk_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct wm831x_clk *clkdata = dev_get_drvdata(&pdev->dev);
|
||||
|
||||
clk_unregister(clkdata->clkout);
|
||||
clk_unregister(clkdata->fll);
|
||||
clk_unregister(clkdata->xtal);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver wm831x_clk_driver = {
|
||||
.probe = wm831x_clk_probe,
|
||||
.remove = __devexit_p(wm831x_clk_remove),
|
||||
.driver = {
|
||||
.name = "wm831x-clk",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(wm831x_clk_driver);
|
||||
|
||||
/* Module information */
|
||||
MODULE_AUTHOR("Mark Brown <[email protected]>");
|
||||
MODULE_DESCRIPTION("WM831x clock driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS("platform:wm831x-clk");
|
||||
|
|
@ -16,6 +16,7 @@
|
|||
#include <linux/err.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
static DEFINE_SPINLOCK(enable_lock);
|
||||
static DEFINE_MUTEX(prepare_lock);
|
||||
|
|
@ -1235,8 +1236,8 @@ int __clk_init(struct device *dev, struct clk *clk)
|
|||
* If clk->parents is not NULL we skip this entire block. This allows
|
||||
* for clock drivers to statically initialize clk->parents.
|
||||
*/
|
||||
if (clk->num_parents && !clk->parents) {
|
||||
clk->parents = kmalloc((sizeof(struct clk*) * clk->num_parents),
|
||||
if (clk->num_parents > 1 && !clk->parents) {
|
||||
clk->parents = kzalloc((sizeof(struct clk*) * clk->num_parents),
|
||||
GFP_KERNEL);
|
||||
/*
|
||||
* __clk_lookup returns NULL for parents that have not been
|
||||
|
|
@ -1550,3 +1551,142 @@ int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
|
|||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_notifier_unregister);
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
/**
|
||||
* struct of_clk_provider - Clock provider registration structure
|
||||
* @link: Entry in global list of clock providers
|
||||
* @node: Pointer to device tree node of clock provider
|
||||
* @get: Get clock callback. Returns NULL or a struct clk for the
|
||||
* given clock specifier
|
||||
* @data: context pointer to be passed into @get callback
|
||||
*/
|
||||
struct of_clk_provider {
|
||||
struct list_head link;
|
||||
|
||||
struct device_node *node;
|
||||
struct clk *(*get)(struct of_phandle_args *clkspec, void *data);
|
||||
void *data;
|
||||
};
|
||||
|
||||
static LIST_HEAD(of_clk_providers);
|
||||
static DEFINE_MUTEX(of_clk_lock);
|
||||
|
||||
struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
|
||||
void *data)
|
||||
{
|
||||
return data;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_clk_src_simple_get);
|
||||
|
||||
/**
|
||||
* of_clk_add_provider() - Register a clock provider for a node
|
||||
* @np: Device node pointer associated with clock provider
|
||||
* @clk_src_get: callback for decoding clock
|
||||
* @data: context pointer for @clk_src_get callback.
|
||||
*/
|
||||
int of_clk_add_provider(struct device_node *np,
|
||||
struct clk *(*clk_src_get)(struct of_phandle_args *clkspec,
|
||||
void *data),
|
||||
void *data)
|
||||
{
|
||||
struct of_clk_provider *cp;
|
||||
|
||||
cp = kzalloc(sizeof(struct of_clk_provider), GFP_KERNEL);
|
||||
if (!cp)
|
||||
return -ENOMEM;
|
||||
|
||||
cp->node = of_node_get(np);
|
||||
cp->data = data;
|
||||
cp->get = clk_src_get;
|
||||
|
||||
mutex_lock(&of_clk_lock);
|
||||
list_add(&cp->link, &of_clk_providers);
|
||||
mutex_unlock(&of_clk_lock);
|
||||
pr_debug("Added clock from %s\n", np->full_name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_clk_add_provider);
|
||||
|
||||
/**
|
||||
* of_clk_del_provider() - Remove a previously registered clock provider
|
||||
* @np: Device node pointer associated with clock provider
|
||||
*/
|
||||
void of_clk_del_provider(struct device_node *np)
|
||||
{
|
||||
struct of_clk_provider *cp;
|
||||
|
||||
mutex_lock(&of_clk_lock);
|
||||
list_for_each_entry(cp, &of_clk_providers, link) {
|
||||
if (cp->node == np) {
|
||||
list_del(&cp->link);
|
||||
of_node_put(cp->node);
|
||||
kfree(cp);
|
||||
break;
|
||||
}
|
||||
}
|
||||
mutex_unlock(&of_clk_lock);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_clk_del_provider);
|
||||
|
||||
struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec)
|
||||
{
|
||||
struct of_clk_provider *provider;
|
||||
struct clk *clk = ERR_PTR(-ENOENT);
|
||||
|
||||
/* Check if we have such a provider in our array */
|
||||
mutex_lock(&of_clk_lock);
|
||||
list_for_each_entry(provider, &of_clk_providers, link) {
|
||||
if (provider->node == clkspec->np)
|
||||
clk = provider->get(clkspec, provider->data);
|
||||
if (!IS_ERR(clk))
|
||||
break;
|
||||
}
|
||||
mutex_unlock(&of_clk_lock);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
const char *of_clk_get_parent_name(struct device_node *np, int index)
|
||||
{
|
||||
struct of_phandle_args clkspec;
|
||||
const char *clk_name;
|
||||
int rc;
|
||||
|
||||
if (index < 0)
|
||||
return NULL;
|
||||
|
||||
rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", index,
|
||||
&clkspec);
|
||||
if (rc)
|
||||
return NULL;
|
||||
|
||||
if (of_property_read_string_index(clkspec.np, "clock-output-names",
|
||||
clkspec.args_count ? clkspec.args[0] : 0,
|
||||
&clk_name) < 0)
|
||||
clk_name = clkspec.np->name;
|
||||
|
||||
of_node_put(clkspec.np);
|
||||
return clk_name;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_clk_get_parent_name);
|
||||
|
||||
/**
|
||||
* of_clk_init() - Scan and init clock providers from the DT
|
||||
* @matches: array of compatible values and init functions for providers.
|
||||
*
|
||||
* This function scans the device tree for matching clock providers and
|
||||
* calls their initialization functions
|
||||
*/
|
||||
void __init of_clk_init(const struct of_device_id *matches)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
for_each_matching_node(np, matches) {
|
||||
const struct of_device_id *match = of_match_node(matches, np);
|
||||
of_clk_init_cb_t clk_init_cb = match->data;
|
||||
clk_init_cb(np);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -19,10 +19,80 @@
|
|||
#include <linux/mutex.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
static LIST_HEAD(clocks);
|
||||
static DEFINE_MUTEX(clocks_mutex);
|
||||
|
||||
#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK)
|
||||
struct clk *of_clk_get(struct device_node *np, int index)
|
||||
{
|
||||
struct of_phandle_args clkspec;
|
||||
struct clk *clk;
|
||||
int rc;
|
||||
|
||||
if (index < 0)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", index,
|
||||
&clkspec);
|
||||
if (rc)
|
||||
return ERR_PTR(rc);
|
||||
|
||||
clk = of_clk_get_from_provider(&clkspec);
|
||||
of_node_put(clkspec.np);
|
||||
return clk;
|
||||
}
|
||||
EXPORT_SYMBOL(of_clk_get);
|
||||
|
||||
/**
|
||||
* of_clk_get_by_name() - Parse and lookup a clock referenced by a device node
|
||||
* @np: pointer to clock consumer node
|
||||
* @name: name of consumer's clock input, or NULL for the first clock reference
|
||||
*
|
||||
* This function parses the clocks and clock-names properties,
|
||||
* and uses them to look up the struct clk from the registered list of clock
|
||||
* providers.
|
||||
*/
|
||||
struct clk *of_clk_get_by_name(struct device_node *np, const char *name)
|
||||
{
|
||||
struct clk *clk = ERR_PTR(-ENOENT);
|
||||
|
||||
/* Walk up the tree of devices looking for a clock that matches */
|
||||
while (np) {
|
||||
int index = 0;
|
||||
|
||||
/*
|
||||
* For named clocks, first look up the name in the
|
||||
* "clock-names" property. If it cannot be found, then
|
||||
* index will be an error code, and of_clk_get() will fail.
|
||||
*/
|
||||
if (name)
|
||||
index = of_property_match_string(np, "clock-names", name);
|
||||
clk = of_clk_get(np, index);
|
||||
if (!IS_ERR(clk))
|
||||
break;
|
||||
else if (name && index >= 0) {
|
||||
pr_err("ERROR: could not get clock %s:%s(%i)\n",
|
||||
np->full_name, name ? name : "", index);
|
||||
return clk;
|
||||
}
|
||||
|
||||
/*
|
||||
* No matching clock found on this node. If the parent node
|
||||
* has a "clock-ranges" property, then we can try one of its
|
||||
* clocks.
|
||||
*/
|
||||
np = np->parent;
|
||||
if (np && !of_get_property(np, "clock-ranges", NULL))
|
||||
break;
|
||||
}
|
||||
|
||||
return clk;
|
||||
}
|
||||
EXPORT_SYMBOL(of_clk_get_by_name);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Find the correct struct clk for the device and connection ID.
|
||||
* We do slightly fuzzy matching here:
|
||||
|
|
@ -83,6 +153,13 @@ EXPORT_SYMBOL(clk_get_sys);
|
|||
struct clk *clk_get(struct device *dev, const char *con_id)
|
||||
{
|
||||
const char *dev_id = dev ? dev_name(dev) : NULL;
|
||||
struct clk *clk;
|
||||
|
||||
if (dev) {
|
||||
clk = of_clk_get_by_name(dev->of_node, con_id);
|
||||
if (!IS_ERR(clk) && __clk_get(clk))
|
||||
return clk;
|
||||
}
|
||||
|
||||
return clk_get_sys(dev_id, con_id);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -106,7 +106,7 @@ static struct clk_lookup lcdif_lookups[] = {
|
|||
|
||||
static struct clk_lookup gpmi_lookups[] = {
|
||||
{ .dev_id = "imx23-gpmi-nand", },
|
||||
{ .dev_id = "8000c000.gpmi", },
|
||||
{ .dev_id = "8000c000.gpmi-nand", },
|
||||
};
|
||||
|
||||
static const char *sel_pll[] __initconst = { "pll", "ref_xtal", };
|
||||
|
|
@ -189,6 +189,7 @@ int __init mx23_clocks_init(void)
|
|||
}
|
||||
|
||||
clk_register_clkdev(clks[clk32k], NULL, "timrot");
|
||||
clk_register_clkdev(clks[pwm], NULL, "80064000.pwm");
|
||||
clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups));
|
||||
clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups));
|
||||
clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups));
|
||||
|
|
|
|||
|
|
@ -112,11 +112,11 @@ static void __init clk_misc_init(void)
|
|||
|
||||
/*
|
||||
* 480 MHz seems too high to be ssp clock source directly,
|
||||
* so set frac0 to get a 288 MHz ref_io0.
|
||||
* so set frac0 to get a 288 MHz ref_io0 and ref_io1.
|
||||
*/
|
||||
val = readl_relaxed(FRAC0);
|
||||
val &= ~(0x3f << BP_FRAC0_IO0FRAC);
|
||||
val |= 30 << BP_FRAC0_IO0FRAC;
|
||||
val &= ~((0x3f << BP_FRAC0_IO0FRAC) | (0x3f << BP_FRAC0_IO1FRAC));
|
||||
val |= (30 << BP_FRAC0_IO0FRAC) | (30 << BP_FRAC0_IO1FRAC);
|
||||
writel_relaxed(val, FRAC0);
|
||||
}
|
||||
|
||||
|
|
@ -174,7 +174,7 @@ static struct clk_lookup lcdif_lookups[] = {
|
|||
|
||||
static struct clk_lookup gpmi_lookups[] = {
|
||||
{ .dev_id = "imx28-gpmi-nand", },
|
||||
{ .dev_id = "8000c000.gpmi", },
|
||||
{ .dev_id = "8000c000.gpmi-nand", },
|
||||
};
|
||||
|
||||
static struct clk_lookup fec_lookups[] = {
|
||||
|
|
@ -314,6 +314,7 @@ int __init mx28_clocks_init(void)
|
|||
|
||||
clk_register_clkdev(clks[clk32k], NULL, "timrot");
|
||||
clk_register_clkdev(clks[enet_out], NULL, "enet_out");
|
||||
clk_register_clkdev(clks[pwm], NULL, "80064000.pwm");
|
||||
clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups));
|
||||
clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups));
|
||||
clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups));
|
||||
|
|
@ -328,6 +329,10 @@ int __init mx28_clocks_init(void)
|
|||
clk_register_clkdevs(clks[fec], fec_lookups, ARRAY_SIZE(fec_lookups));
|
||||
clk_register_clkdevs(clks[can0], can0_lookups, ARRAY_SIZE(can0_lookups));
|
||||
clk_register_clkdevs(clks[can1], can1_lookups, ARRAY_SIZE(can1_lookups));
|
||||
clk_register_clkdev(clks[usb0_pwr], NULL, "8007c000.usbphy");
|
||||
clk_register_clkdev(clks[usb1_pwr], NULL, "8007e000.usbphy");
|
||||
clk_register_clkdev(clks[usb0], NULL, "80080000.usb");
|
||||
clk_register_clkdev(clks[usb1], NULL, "80090000.usb");
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
|
||||
clk_prepare_enable(clks[clks_init_on[i]]);
|
||||
|
|
|
|||
3
drivers/clk/versatile/Makefile
Normal file
3
drivers/clk/versatile/Makefile
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
# Makefile for Versatile-specific clocks
|
||||
obj-$(CONFIG_ICST) += clk-icst.o
|
||||
obj-$(CONFIG_ARCH_INTEGRATOR) += clk-integrator.o
|
||||
100
drivers/clk/versatile/clk-icst.c
Normal file
100
drivers/clk/versatile/clk-icst.c
Normal file
|
|
@ -0,0 +1,100 @@
|
|||
/*
|
||||
* Driver for the ICST307 VCO clock found in the ARM Reference designs.
|
||||
* We wrap the custom interface from <asm/hardware/icst.h> into the generic
|
||||
* clock framework.
|
||||
*
|
||||
* TODO: when all ARM reference designs are migrated to generic clocks, the
|
||||
* ICST clock code from the ARM tree should probably be merged into this
|
||||
* file.
|
||||
*/
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk-provider.h>
|
||||
|
||||
#include "clk-icst.h"
|
||||
|
||||
/**
|
||||
* struct clk_icst - ICST VCO clock wrapper
|
||||
* @hw: corresponding clock hardware entry
|
||||
* @params: parameters for this ICST instance
|
||||
* @rate: current rate
|
||||
* @setvco: function to commit ICST settings to hardware
|
||||
*/
|
||||
struct clk_icst {
|
||||
struct clk_hw hw;
|
||||
const struct icst_params *params;
|
||||
unsigned long rate;
|
||||
struct icst_vco (*getvco)(void);
|
||||
void (*setvco)(struct icst_vco);
|
||||
};
|
||||
|
||||
#define to_icst(_hw) container_of(_hw, struct clk_icst, hw)
|
||||
|
||||
static unsigned long icst_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_icst *icst = to_icst(hw);
|
||||
struct icst_vco vco;
|
||||
|
||||
vco = icst->getvco();
|
||||
icst->rate = icst_hz(icst->params, vco);
|
||||
return icst->rate;
|
||||
}
|
||||
|
||||
static long icst_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
struct clk_icst *icst = to_icst(hw);
|
||||
struct icst_vco vco;
|
||||
|
||||
vco = icst_hz_to_vco(icst->params, rate);
|
||||
return icst_hz(icst->params, vco);
|
||||
}
|
||||
|
||||
static int icst_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_icst *icst = to_icst(hw);
|
||||
struct icst_vco vco;
|
||||
|
||||
vco = icst_hz_to_vco(icst->params, rate);
|
||||
icst->rate = icst_hz(icst->params, vco);
|
||||
icst->setvco(vco);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops icst_ops = {
|
||||
.recalc_rate = icst_recalc_rate,
|
||||
.round_rate = icst_round_rate,
|
||||
.set_rate = icst_set_rate,
|
||||
};
|
||||
|
||||
struct clk * __init icst_clk_register(struct device *dev,
|
||||
const struct clk_icst_desc *desc)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_icst *icst;
|
||||
struct clk_init_data init;
|
||||
|
||||
icst = kzalloc(sizeof(struct clk_icst), GFP_KERNEL);
|
||||
if (!icst) {
|
||||
pr_err("could not allocate ICST clock!\n");
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
init.name = "icst";
|
||||
init.ops = &icst_ops;
|
||||
init.flags = CLK_IS_ROOT;
|
||||
init.parent_names = NULL;
|
||||
init.num_parents = 0;
|
||||
icst->hw.init = &init;
|
||||
icst->params = desc->params;
|
||||
icst->getvco = desc->getvco;
|
||||
icst->setvco = desc->setvco;
|
||||
|
||||
clk = clk_register(dev, &icst->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(icst);
|
||||
|
||||
return clk;
|
||||
}
|
||||
10
drivers/clk/versatile/clk-icst.h
Normal file
10
drivers/clk/versatile/clk-icst.h
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
#include <asm/hardware/icst.h>
|
||||
|
||||
struct clk_icst_desc {
|
||||
const struct icst_params *params;
|
||||
struct icst_vco (*getvco)(void);
|
||||
void (*setvco)(struct icst_vco);
|
||||
};
|
||||
|
||||
struct clk *icst_clk_register(struct device *dev,
|
||||
const struct clk_icst_desc *desc);
|
||||
111
drivers/clk/versatile/clk-integrator.c
Normal file
111
drivers/clk/versatile/clk-integrator.c
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clk-provider.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/platform.h>
|
||||
|
||||
#include "clk-icst.h"
|
||||
|
||||
/*
|
||||
* Implementation of the ARM Integrator/AP and Integrator/CP clock tree.
|
||||
* Inspired by portions of:
|
||||
* plat-versatile/clock.c and plat-versatile/include/plat/clock.h
|
||||
*/
|
||||
#define CM_LOCK (__io_address(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
|
||||
#define CM_AUXOSC (__io_address(INTEGRATOR_HDR_BASE)+0x1c)
|
||||
|
||||
/**
|
||||
* cp_auxvco_get() - get ICST VCO settings for the Integrator/CP
|
||||
* @vco: ICST VCO parameters to update with hardware status
|
||||
*/
|
||||
static struct icst_vco cp_auxvco_get(void)
|
||||
{
|
||||
u32 val;
|
||||
struct icst_vco vco;
|
||||
|
||||
val = readl(CM_AUXOSC);
|
||||
vco.v = val & 0x1ff;
|
||||
vco.r = (val >> 9) & 0x7f;
|
||||
vco.s = (val >> 16) & 03;
|
||||
return vco;
|
||||
}
|
||||
|
||||
/**
|
||||
* cp_auxvco_set() - commit changes to Integrator/CP ICST VCO
|
||||
* @vco: ICST VCO parameters to commit
|
||||
*/
|
||||
static void cp_auxvco_set(struct icst_vco vco)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = readl(CM_AUXOSC) & ~0x7ffff;
|
||||
val |= vco.v | (vco.r << 9) | (vco.s << 16);
|
||||
|
||||
/* This magic unlocks the CM VCO so it can be controlled */
|
||||
writel(0xa05f, CM_LOCK);
|
||||
writel(val, CM_AUXOSC);
|
||||
/* This locks the CM again */
|
||||
writel(0, CM_LOCK);
|
||||
}
|
||||
|
||||
static const struct icst_params cp_auxvco_params = {
|
||||
.ref = 24000000,
|
||||
.vco_max = ICST525_VCO_MAX_5V,
|
||||
.vco_min = ICST525_VCO_MIN,
|
||||
.vd_min = 8,
|
||||
.vd_max = 263,
|
||||
.rd_min = 3,
|
||||
.rd_max = 65,
|
||||
.s2div = icst525_s2div,
|
||||
.idx2s = icst525_idx2s,
|
||||
};
|
||||
|
||||
static const struct clk_icst_desc __initdata cp_icst_desc = {
|
||||
.params = &cp_auxvco_params,
|
||||
.getvco = cp_auxvco_get,
|
||||
.setvco = cp_auxvco_set,
|
||||
};
|
||||
|
||||
/*
|
||||
* integrator_clk_init() - set up the integrator clock tree
|
||||
* @is_cp: pass true if it's the Integrator/CP else AP is assumed
|
||||
*/
|
||||
void __init integrator_clk_init(bool is_cp)
|
||||
{
|
||||
struct clk *clk;
|
||||
|
||||
/* APB clock dummy */
|
||||
clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
|
||||
clk_register_clkdev(clk, "apb_pclk", NULL);
|
||||
|
||||
/* UART reference clock */
|
||||
clk = clk_register_fixed_rate(NULL, "uartclk", NULL, CLK_IS_ROOT,
|
||||
14745600);
|
||||
clk_register_clkdev(clk, NULL, "uart0");
|
||||
clk_register_clkdev(clk, NULL, "uart1");
|
||||
if (is_cp)
|
||||
clk_register_clkdev(clk, NULL, "mmci");
|
||||
|
||||
/* 24 MHz clock */
|
||||
clk = clk_register_fixed_rate(NULL, "clk24mhz", NULL, CLK_IS_ROOT,
|
||||
24000000);
|
||||
clk_register_clkdev(clk, NULL, "kmi0");
|
||||
clk_register_clkdev(clk, NULL, "kmi1");
|
||||
if (!is_cp)
|
||||
clk_register_clkdev(clk, NULL, "ap_timer");
|
||||
|
||||
if (!is_cp)
|
||||
return;
|
||||
|
||||
/* 1 MHz clock */
|
||||
clk = clk_register_fixed_rate(NULL, "clk1mhz", NULL, CLK_IS_ROOT,
|
||||
1000000);
|
||||
clk_register_clkdev(clk, NULL, "sp804");
|
||||
|
||||
/* ICST VCO clock used on the Integrator/CP CLCD */
|
||||
clk = icst_clk_register(NULL, &cp_icst_desc);
|
||||
clk_register_clkdev(clk, NULL, "clcd");
|
||||
}
|
||||
Loading…
Reference in a new issue