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irqchip/gic-v3: Reset BPR during initialization

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Currently, when running on FVP, CPU 0 boots up with its BPR changed from
the reset value. This renders it impossible to (preemptively) prioritize
interrupts on CPU 0.

This is harmless on normal systems since Linux typically does not
support preemptive interrupts. It does however cause problems in
systems with additional changes (such as patches for NMI simulation).

Many thanks to Andrew Thoelke for suggesting the BPR as having the
potential to harm preemption.

Suggested-by: Andrew Thoelke <[email protected]>
Signed-off-by: Daniel Thompson <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
This commit is contained in:
Daniel Thompson 2016-08-19 17:13:09 +01:00 • committed by Marc Zyngier
commit 91ef84428a
3 changed files with 20 additions and 0 deletions
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8
drivers/irqchip/irq-gic-v3.c
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@ -495,6 +495,14 @@ static void gic_cpu_sys_reg_init(void)
/* Set priority mask register */
gic_write_pmr(DEFAULT_PMR_VALUE);
/*
* Some firmwares hand over to the kernel with the BPR changed from
* its reset value (and with a value large enough to prevent
* any pre-emptive interrupts from working at all). Writing a zero
* to BPR restores is reset value.
*/
gic_write_bpr1(0);
if (static_key_true(&supports_deactivate)) {
/* EOI drops priority only (mode 1) */
gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);