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Merge "ARM: dts: msm: Add GPUCC clock node and GDSCs for MONACO"

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This commit is contained in:
qctecmdr 2021-04-28 17:58:45 -07:00 • committed by Gerrit - the friendly Code Review server
commit 925466bdbe
2 changed files with 10 additions and 5 deletions
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4
qcom/monaco-gdsc.dtsi
View file

@ -71,7 +71,7 @@
};
gpu_cx_gdsc: qcom,gdsc@5994064 {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0x5994064 0x4>;
regulator-name = "gpu_cx_gdsc";
hw-ctl-addr = <&gpu_cx_hw_ctrl>;
@ -80,7 +80,7 @@
};
gpu_gx_gdsc: qcom,gdsc@599400c {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0x599400c 0x4>;
regulator-name = "gpu_gx_gdsc";
sw-reset = <&gpu_gx_sw_reset>;

11
qcom/monaco.dtsi
View file

@ -711,9 +711,14 @@
#reset-cells = <1>;
};
gpucc: clock-controller@5994000 {
compatible = "qcom,dummycc";
clock-output-names = "gpucc_clocks";
gpucc: clock-controller@5990000 {
compatible = "qcom,monaco-gpucc", "syscon";
reg = <0x5990000 0x9000>;
reg-names = "cc_base";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&gcc GPLL0>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "gpll0_out_main";
vdd_cx-supply = <&VDD_CX_LEVEL>;
#clock-cells = <1>;
#reset-cells = <1>;
};