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clk: tegra: Fix pllre Tegra210 and add pll_re_out1
Use a new Tegra210 version of the pll_register_pllre function to allow setting the proper settings for the m and n div fields. Additionally define PLL_RE_OUT1 on Tegra210. Signed-off-by: Rhyland Klein <[email protected]> [[email protected]: define PLLRE_OUT1 register offset] Signed-off-by: Thierry Reding <[email protected]>
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4 changed files with 67 additions and 3 deletions
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@ -346,7 +346,7 @@
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#define TEGRA210_CLK_PLL_P_OUT_HSIO 316
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#define TEGRA210_CLK_PLL_P_OUT_XUSB 317
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#define TEGRA210_CLK_XUSB_SSP_SRC 318
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/* 319 */
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#define TEGRA210_CLK_PLL_RE_OUT1 319
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/* 320 */
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/* 321 */
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/* 322 */
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