clk: tegra: Fix pllre Tegra210 and add pll_re_out1

Use a new Tegra210 version of the pll_register_pllre function to
allow setting the proper settings for the m and n div fields.

Additionally define PLL_RE_OUT1 on Tegra210.

Signed-off-by: Rhyland Klein <[email protected]>
[[email protected]: define PLLRE_OUT1 register offset]
Signed-off-by: Thierry Reding <[email protected]>
This commit is contained in:
Rhyland Klein 2016-03-21 15:58:52 -04:00 • committed by Thierry Reding
commit 926655f929
4 changed files with 67 additions and 3 deletions

View file

@ -346,7 +346,7 @@
#define TEGRA210_CLK_PLL_P_OUT_HSIO 316
#define TEGRA210_CLK_PLL_P_OUT_XUSB 317
#define TEGRA210_CLK_XUSB_SSP_SRC 318
/* 319 */
#define TEGRA210_CLK_PLL_RE_OUT1 319
/* 320 */
/* 321 */
/* 322 */