mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 11:11:45 -04:00
Merge branch 'genirq-v28-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
This merges branches irq/genirq, irq/sparseirq-v4, timers/hpet-percpu and x86/uv. The sparseirq branch is just preliminary groundwork: no sparse IRQs are actually implemented by this tree anymore - just the new APIs are added while keeping the old way intact as well (the new APIs map 1:1 to irq_desc[]). The 'real' sparse IRQ support will then be a relatively small patch ontop of this - with a v2.6.29 merge target. * 'genirq-v28-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (178 commits) genirq: improve include files intr_remapping: fix typo io_apic: make irq_mis_count available on 64-bit too genirq: fix name space collisions of nr_irqs in arch/* genirq: fix name space collision of nr_irqs in autoprobe.c genirq: use iterators for irq_desc loops proc: fixup irq iterator genirq: add reverse iterator for irq_desc x86: move ack_bad_irq() to irq.c x86: unify show_interrupts() and proc helpers x86: cleanup show_interrupts genirq: cleanup the sparseirq modifications genirq: remove artifacts from sparseirq removal genirq: revert dynarray genirq: remove irq_to_desc_alloc genirq: remove sparse irq code genirq: use inline function for irq_to_desc genirq: consolidate nr_irqs and for_each_irq_desc() x86: remove sparse irq from Kconfig genirq: define nr_irqs for architectures with GENERIC_HARDIRQS=n ...
This commit is contained in:
Linus Torvalds
commit
9301975ec2
111 changed files with 3716 additions and 6226 deletions
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@ -193,7 +193,7 @@ dmar_parse_dev(struct dmar_drhd_unit *dmaru)
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{
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struct acpi_dmar_hardware_unit *drhd;
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static int include_all;
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int ret;
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int ret = 0;
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drhd = (struct acpi_dmar_hardware_unit *) dmaru->hdr;
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@ -212,7 +212,7 @@ dmar_parse_dev(struct dmar_drhd_unit *dmaru)
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include_all = 1;
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}
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if (ret || (dmaru->devices_cnt == 0 && !dmaru->include_all)) {
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if (ret) {
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list_del(&dmaru->list);
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kfree(dmaru);
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}
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@ -289,6 +289,24 @@ dmar_table_print_dmar_entry(struct acpi_dmar_header *header)
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}
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}
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/**
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* dmar_table_detect - checks to see if the platform supports DMAR devices
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*/
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static int __init dmar_table_detect(void)
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{
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acpi_status status = AE_OK;
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/* if we could find DMAR table, then there are DMAR devices */
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status = acpi_get_table(ACPI_SIG_DMAR, 0,
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(struct acpi_table_header **)&dmar_tbl);
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if (ACPI_SUCCESS(status) && !dmar_tbl) {
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printk (KERN_WARNING PREFIX "Unable to map DMAR\n");
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status = AE_NOT_FOUND;
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}
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return (ACPI_SUCCESS(status) ? 1 : 0);
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}
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/**
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* parse_dmar_table - parses the DMA reporting table
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@ -300,6 +318,12 @@ parse_dmar_table(void)
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struct acpi_dmar_header *entry_header;
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int ret = 0;
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/*
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* Do it again, earlier dmar_tbl mapping could be mapped with
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* fixed map.
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*/
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dmar_table_detect();
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dmar = (struct acpi_table_dmar *)dmar_tbl;
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if (!dmar)
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return -ENODEV;
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@ -373,10 +397,10 @@ dmar_find_matched_drhd_unit(struct pci_dev *dev)
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int __init dmar_dev_scope_init(void)
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{
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struct dmar_drhd_unit *drhd;
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struct dmar_drhd_unit *drhd, *drhd_n;
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int ret = -ENODEV;
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for_each_drhd_unit(drhd) {
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list_for_each_entry_safe(drhd, drhd_n, &dmar_drhd_units, list) {
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ret = dmar_parse_dev(drhd);
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if (ret)
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return ret;
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@ -384,8 +408,8 @@ int __init dmar_dev_scope_init(void)
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#ifdef CONFIG_DMAR
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{
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struct dmar_rmrr_unit *rmrr;
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for_each_rmrr_units(rmrr) {
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struct dmar_rmrr_unit *rmrr, *rmrr_n;
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list_for_each_entry_safe(rmrr, rmrr_n, &dmar_rmrr_units, list) {
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ret = rmrr_parse_dev(rmrr);
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if (ret)
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return ret;
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@ -430,30 +454,11 @@ int __init dmar_table_init(void)
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return 0;
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}
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/**
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* early_dmar_detect - checks to see if the platform supports DMAR devices
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*/
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int __init early_dmar_detect(void)
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{
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acpi_status status = AE_OK;
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/* if we could find DMAR table, then there are DMAR devices */
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status = acpi_get_table(ACPI_SIG_DMAR, 0,
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(struct acpi_table_header **)&dmar_tbl);
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if (ACPI_SUCCESS(status) && !dmar_tbl) {
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printk (KERN_WARNING PREFIX "Unable to map DMAR\n");
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status = AE_NOT_FOUND;
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}
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return (ACPI_SUCCESS(status) ? 1 : 0);
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}
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void __init detect_intel_iommu(void)
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{
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int ret;
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ret = early_dmar_detect();
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ret = dmar_table_detect();
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#ifdef CONFIG_DMAR
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{
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@ -479,14 +484,16 @@ void __init detect_intel_iommu(void)
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" x2apic support\n");
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dmar_disabled = 1;
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return;
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goto end;
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}
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if (ret && !no_iommu && !iommu_detected && !swiotlb &&
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!dmar_disabled)
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iommu_detected = 1;
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}
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end:
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#endif
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dmar_tbl = NULL;
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}
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@ -126,7 +126,8 @@ int __ht_create_irq(struct pci_dev *dev, int idx, ht_irq_update_t *update)
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cfg->msg.address_hi = 0xffffffff;
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irq = create_irq();
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if (irq < 0) {
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if (irq <= 0) {
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kfree(cfg);
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return -EBUSY;
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}
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@ -1,3 +1,4 @@
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#include <linux/interrupt.h>
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#include <linux/dmar.h>
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#include <linux/spinlock.h>
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#include <linux/jiffies.h>
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@ -11,41 +12,64 @@ static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
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static int ir_ioapic_num;
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int intr_remapping_enabled;
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static struct {
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struct irq_2_iommu {
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struct intel_iommu *iommu;
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u16 irte_index;
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u16 sub_handle;
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u8 irte_mask;
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} irq_2_iommu[NR_IRQS];
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};
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static struct irq_2_iommu irq_2_iommuX[NR_IRQS];
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static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
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{
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return (irq < nr_irqs) ? irq_2_iommuX + irq : NULL;
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}
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static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
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{
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return irq_2_iommu(irq);
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}
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static DEFINE_SPINLOCK(irq_2_ir_lock);
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static struct irq_2_iommu *valid_irq_2_iommu(unsigned int irq)
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{
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struct irq_2_iommu *irq_iommu;
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irq_iommu = irq_2_iommu(irq);
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if (!irq_iommu)
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return NULL;
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if (!irq_iommu->iommu)
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return NULL;
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return irq_iommu;
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}
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int irq_remapped(int irq)
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{
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if (irq > NR_IRQS)
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return 0;
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if (!irq_2_iommu[irq].iommu)
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return 0;
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return 1;
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return valid_irq_2_iommu(irq) != NULL;
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}
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int get_irte(int irq, struct irte *entry)
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{
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int index;
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struct irq_2_iommu *irq_iommu;
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if (!entry || irq > NR_IRQS)
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if (!entry)
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return -1;
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spin_lock(&irq_2_ir_lock);
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if (!irq_2_iommu[irq].iommu) {
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irq_iommu = valid_irq_2_iommu(irq);
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if (!irq_iommu) {
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spin_unlock(&irq_2_ir_lock);
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return -1;
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}
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index = irq_2_iommu[irq].irte_index + irq_2_iommu[irq].sub_handle;
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*entry = *(irq_2_iommu[irq].iommu->ir_table->base + index);
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index = irq_iommu->irte_index + irq_iommu->sub_handle;
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*entry = *(irq_iommu->iommu->ir_table->base + index);
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spin_unlock(&irq_2_ir_lock);
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return 0;
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@ -54,6 +78,7 @@ int get_irte(int irq, struct irte *entry)
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int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
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{
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struct ir_table *table = iommu->ir_table;
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struct irq_2_iommu *irq_iommu;
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u16 index, start_index;
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unsigned int mask = 0;
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int i;
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@ -61,6 +86,10 @@ int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
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if (!count)
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return -1;
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/* protect irq_2_iommu_alloc later */
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if (irq >= nr_irqs)
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return -1;
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/*
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* start the IRTE search from index 0.
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*/
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@ -100,10 +129,11 @@ int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
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for (i = index; i < index + count; i++)
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table->base[i].present = 1;
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irq_2_iommu[irq].iommu = iommu;
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irq_2_iommu[irq].irte_index = index;
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irq_2_iommu[irq].sub_handle = 0;
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irq_2_iommu[irq].irte_mask = mask;
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irq_iommu = irq_2_iommu_alloc(irq);
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irq_iommu->iommu = iommu;
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irq_iommu->irte_index = index;
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irq_iommu->sub_handle = 0;
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irq_iommu->irte_mask = mask;
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spin_unlock(&irq_2_ir_lock);
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@ -124,31 +154,33 @@ static void qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
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int map_irq_to_irte_handle(int irq, u16 *sub_handle)
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{
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int index;
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struct irq_2_iommu *irq_iommu;
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spin_lock(&irq_2_ir_lock);
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if (irq >= NR_IRQS || !irq_2_iommu[irq].iommu) {
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irq_iommu = valid_irq_2_iommu(irq);
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if (!irq_iommu) {
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spin_unlock(&irq_2_ir_lock);
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return -1;
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}
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*sub_handle = irq_2_iommu[irq].sub_handle;
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index = irq_2_iommu[irq].irte_index;
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*sub_handle = irq_iommu->sub_handle;
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index = irq_iommu->irte_index;
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spin_unlock(&irq_2_ir_lock);
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return index;
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}
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int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle)
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{
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spin_lock(&irq_2_ir_lock);
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if (irq >= NR_IRQS || irq_2_iommu[irq].iommu) {
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spin_unlock(&irq_2_ir_lock);
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return -1;
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}
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struct irq_2_iommu *irq_iommu;
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irq_2_iommu[irq].iommu = iommu;
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irq_2_iommu[irq].irte_index = index;
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irq_2_iommu[irq].sub_handle = subhandle;
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irq_2_iommu[irq].irte_mask = 0;
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spin_lock(&irq_2_ir_lock);
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irq_iommu = irq_2_iommu_alloc(irq);
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irq_iommu->iommu = iommu;
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irq_iommu->irte_index = index;
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irq_iommu->sub_handle = subhandle;
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irq_iommu->irte_mask = 0;
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spin_unlock(&irq_2_ir_lock);
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@ -157,16 +189,19 @@ int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle)
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int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index)
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{
|
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struct irq_2_iommu *irq_iommu;
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|
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spin_lock(&irq_2_ir_lock);
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if (irq >= NR_IRQS || !irq_2_iommu[irq].iommu) {
|
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irq_iommu = valid_irq_2_iommu(irq);
|
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if (!irq_iommu) {
|
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spin_unlock(&irq_2_ir_lock);
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return -1;
|
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}
|
||||
|
||||
irq_2_iommu[irq].iommu = NULL;
|
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irq_2_iommu[irq].irte_index = 0;
|
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irq_2_iommu[irq].sub_handle = 0;
|
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irq_2_iommu[irq].irte_mask = 0;
|
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irq_iommu->iommu = NULL;
|
||||
irq_iommu->irte_index = 0;
|
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irq_iommu->sub_handle = 0;
|
||||
irq_2_iommu(irq)->irte_mask = 0;
|
||||
|
||||
spin_unlock(&irq_2_ir_lock);
|
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|
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|
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@ -178,16 +213,18 @@ int modify_irte(int irq, struct irte *irte_modified)
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int index;
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struct irte *irte;
|
||||
struct intel_iommu *iommu;
|
||||
struct irq_2_iommu *irq_iommu;
|
||||
|
||||
spin_lock(&irq_2_ir_lock);
|
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if (irq >= NR_IRQS || !irq_2_iommu[irq].iommu) {
|
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irq_iommu = valid_irq_2_iommu(irq);
|
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if (!irq_iommu) {
|
||||
spin_unlock(&irq_2_ir_lock);
|
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return -1;
|
||||
}
|
||||
|
||||
iommu = irq_2_iommu[irq].iommu;
|
||||
iommu = irq_iommu->iommu;
|
||||
|
||||
index = irq_2_iommu[irq].irte_index + irq_2_iommu[irq].sub_handle;
|
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index = irq_iommu->irte_index + irq_iommu->sub_handle;
|
||||
irte = &iommu->ir_table->base[index];
|
||||
|
||||
set_64bit((unsigned long *)irte, irte_modified->low | (1 << 1));
|
||||
|
|
@ -203,18 +240,20 @@ int flush_irte(int irq)
|
|||
{
|
||||
int index;
|
||||
struct intel_iommu *iommu;
|
||||
struct irq_2_iommu *irq_iommu;
|
||||
|
||||
spin_lock(&irq_2_ir_lock);
|
||||
if (irq >= NR_IRQS || !irq_2_iommu[irq].iommu) {
|
||||
irq_iommu = valid_irq_2_iommu(irq);
|
||||
if (!irq_iommu) {
|
||||
spin_unlock(&irq_2_ir_lock);
|
||||
return -1;
|
||||
}
|
||||
|
||||
iommu = irq_2_iommu[irq].iommu;
|
||||
iommu = irq_iommu->iommu;
|
||||
|
||||
index = irq_2_iommu[irq].irte_index + irq_2_iommu[irq].sub_handle;
|
||||
index = irq_iommu->irte_index + irq_iommu->sub_handle;
|
||||
|
||||
qi_flush_iec(iommu, index, irq_2_iommu[irq].irte_mask);
|
||||
qi_flush_iec(iommu, index, irq_iommu->irte_mask);
|
||||
spin_unlock(&irq_2_ir_lock);
|
||||
|
||||
return 0;
|
||||
|
|
@ -246,28 +285,30 @@ int free_irte(int irq)
|
|||
int index, i;
|
||||
struct irte *irte;
|
||||
struct intel_iommu *iommu;
|
||||
struct irq_2_iommu *irq_iommu;
|
||||
|
||||
spin_lock(&irq_2_ir_lock);
|
||||
if (irq >= NR_IRQS || !irq_2_iommu[irq].iommu) {
|
||||
irq_iommu = valid_irq_2_iommu(irq);
|
||||
if (!irq_iommu) {
|
||||
spin_unlock(&irq_2_ir_lock);
|
||||
return -1;
|
||||
}
|
||||
|
||||
iommu = irq_2_iommu[irq].iommu;
|
||||
iommu = irq_iommu->iommu;
|
||||
|
||||
index = irq_2_iommu[irq].irte_index + irq_2_iommu[irq].sub_handle;
|
||||
index = irq_iommu->irte_index + irq_iommu->sub_handle;
|
||||
irte = &iommu->ir_table->base[index];
|
||||
|
||||
if (!irq_2_iommu[irq].sub_handle) {
|
||||
for (i = 0; i < (1 << irq_2_iommu[irq].irte_mask); i++)
|
||||
if (!irq_iommu->sub_handle) {
|
||||
for (i = 0; i < (1 << irq_iommu->irte_mask); i++)
|
||||
set_64bit((unsigned long *)irte, 0);
|
||||
qi_flush_iec(iommu, index, irq_2_iommu[irq].irte_mask);
|
||||
qi_flush_iec(iommu, index, irq_iommu->irte_mask);
|
||||
}
|
||||
|
||||
irq_2_iommu[irq].iommu = NULL;
|
||||
irq_2_iommu[irq].irte_index = 0;
|
||||
irq_2_iommu[irq].sub_handle = 0;
|
||||
irq_2_iommu[irq].irte_mask = 0;
|
||||
irq_iommu->iommu = NULL;
|
||||
irq_iommu->irte_index = 0;
|
||||
irq_iommu->sub_handle = 0;
|
||||
irq_iommu->irte_mask = 0;
|
||||
|
||||
spin_unlock(&irq_2_ir_lock);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue