From df4f22e790ab6097b2dae060ef8581e2ad456447 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Wed, 4 Dec 2019 15:32:36 +0800 Subject: [PATCH] coresight: csr: update timestamp related registers offset TIMESTAMPCTRL, QDSSTIMEVAL0, QDSSTIMEVAL1 registers offset of AODBG CSR is different form QDSS CSR. This change add a dt config aodbg-csr-support to compatible with AODBG CSR, update those offset according to this config. Change-Id: Ieb293e4fc110c4ddad32a08f4a51e9955f1f1af3 Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-csr.c | 22 ++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-csr.c b/drivers/hwtracing/coresight/coresight-csr.c index 305f6e28d05e..788d399a1def 100644 --- a/drivers/hwtracing/coresight/coresight-csr.c +++ b/drivers/hwtracing/coresight/coresight-csr.c @@ -91,6 +91,7 @@ struct csr_drvdata { bool timestamp_support; bool enable_flush; bool msr_support; + bool aodbg_csr_support; }; DEFINE_CORESIGHT_DEVLIST(csr_devs, "csr"); @@ -322,6 +323,7 @@ static ssize_t timestamp_show(struct device *dev, uint32_t val, time_val0, time_val1; int ret; unsigned long flags; + unsigned long csr_ts_offset = 0; struct csr_drvdata *drvdata = dev_get_drvdata(dev->parent); @@ -330,6 +332,9 @@ static ssize_t timestamp_show(struct device *dev, return 0; } + if (drvdata->aodbg_csr_support) + csr_ts_offset = 0x14; + ret = clk_prepare_enable(drvdata->clk); if (ret) return ret; @@ -337,16 +342,16 @@ static ssize_t timestamp_show(struct device *dev, spin_lock_irqsave(&drvdata->spin_lock, flags); CSR_UNLOCK(drvdata); - val = csr_readl(drvdata, CSR_TIMESTAMPCTRL); + val = csr_readl(drvdata, CSR_TIMESTAMPCTRL - csr_ts_offset); val = val & ~BIT(0); - csr_writel(drvdata, val, CSR_TIMESTAMPCTRL); + csr_writel(drvdata, val, CSR_TIMESTAMPCTRL - csr_ts_offset); val = val | BIT(0); - csr_writel(drvdata, val, CSR_TIMESTAMPCTRL); + csr_writel(drvdata, val, CSR_TIMESTAMPCTRL - csr_ts_offset); - time_val0 = csr_readl(drvdata, CSR_QDSSTIMEVAL0); - time_val1 = csr_readl(drvdata, CSR_QDSSTIMEVAL1); + time_val0 = csr_readl(drvdata, CSR_QDSSTIMEVAL0 - csr_ts_offset); + time_val1 = csr_readl(drvdata, CSR_QDSSTIMEVAL1 - csr_ts_offset); CSR_LOCK(drvdata); spin_unlock_irqrestore(&drvdata->spin_lock, flags); @@ -588,6 +593,13 @@ static int csr_probe(struct platform_device *pdev) else dev_dbg(dev, "timestamp_support operation supported\n"); + drvdata->aodbg_csr_support = of_property_read_bool(pdev->dev.of_node, + "qcom,aodbg-csr-support"); + if (!drvdata->aodbg_csr_support) + dev_dbg(dev, "aodbg_csr_support operation not supported\n"); + else + dev_dbg(dev, "aodbg_csr_support operation supported\n"); + if (drvdata->usb_bam_support) drvdata->flushperiod = FLUSHPERIOD_2048; drvdata->msr_support = of_property_read_bool(pdev->dev.of_node,