mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 03:01:39 -04:00
Linux 4.10-rc8
-----BEGIN PGP SIGNATURE----- iQEcBAABAgAGBQJYoM2fAAoJEHm+PkMAQRiGr9MH/izEAMri7rJ0QMc3ejt+WmD0 8pkZw3+MVn71z6cIEgpzk4QkEWJd5rfhkETCeCp7qQ9V6cDW1FDE9+0OmPjiphDt nnzKs7t7skEBwH5Mq5xygmIfkv+Z0QGHZ20gfQWY3F56Uxo+ARF88OBHBLKhqx3v 98C7YbMFLKBslKClA78NUEIdx0UfBaRqerlERx0Lfl9aoOrbBS6WI3iuREiylpih 9o7HTrwaGKkU4Kd6NdgJP2EyWPsd1LGalxBBjeDSpm5uokX6ALTdNXDZqcQscHjE RmTqJTGRdhSThXOpNnvUJvk9L442yuNRrVme/IqLpxMdHPyjaXR3FGSIDb2SfjY= =VMy8 -----END PGP SIGNATURE----- Merge tag 'v4.10-rc8' into drm-next Linux 4.10-rc8 Backmerge Linus rc8 to fix some conflicts, but also to avoid pulling it in via a fixes pull from someone.
This commit is contained in:
Dave Airlie
commit
94000cc329
566 changed files with 5220 additions and 3088 deletions
|
|
@ -83,6 +83,13 @@ int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
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}
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break;
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}
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if (!(*out_ring && (*out_ring)->adev)) {
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DRM_ERROR("Ring %d is not initialized on IP %d\n",
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ring, ip_type);
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return -EINVAL;
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}
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return 0;
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}
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@ -627,11 +627,8 @@ static const struct drm_encoder_helper_funcs dce_virtual_encoder_helper_funcs =
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static void dce_virtual_encoder_destroy(struct drm_encoder *encoder)
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{
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struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
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kfree(amdgpu_encoder->enc_priv);
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drm_encoder_cleanup(encoder);
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kfree(amdgpu_encoder);
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kfree(encoder);
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}
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static const struct drm_encoder_funcs dce_virtual_encoder_funcs = {
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@ -254,6 +254,9 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
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}
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WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
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if (adev->mode_info.num_crtc)
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amdgpu_display_set_vga_render_state(adev, false);
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gmc_v6_0_mc_stop(adev, &save);
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if (gmc_v6_0_wait_for_idle((void *)adev)) {
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@ -283,7 +286,6 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
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dev_warn(adev->dev, "Wait for MC idle timedout !\n");
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}
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gmc_v6_0_mc_resume(adev, &save);
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amdgpu_display_set_vga_render_state(adev, false);
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}
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static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
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@ -114,6 +114,7 @@ struct ast_private {
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struct ttm_bo_kmap_obj cache_kmap;
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int next_cursor;
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bool support_wide_screen;
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bool DisableP2A;
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enum ast_tx_chip tx_chip_type;
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u8 dp501_maxclk;
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@ -124,6 +124,12 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post)
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} else
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*need_post = false;
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/* Check P2A Access */
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ast->DisableP2A = true;
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data = ast_read32(ast, 0xf004);
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if (data != 0xFFFFFFFF)
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ast->DisableP2A = false;
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/* Check if we support wide screen */
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switch (ast->chip) {
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case AST1180:
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@ -140,15 +146,17 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post)
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ast->support_wide_screen = true;
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else {
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ast->support_wide_screen = false;
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/* Read SCU7c (silicon revision register) */
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ast_write32(ast, 0xf004, 0x1e6e0000);
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ast_write32(ast, 0xf000, 0x1);
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data = ast_read32(ast, 0x1207c);
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data &= 0x300;
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if (ast->chip == AST2300 && data == 0x0) /* ast1300 */
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ast->support_wide_screen = true;
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if (ast->chip == AST2400 && data == 0x100) /* ast1400 */
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ast->support_wide_screen = true;
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if (ast->DisableP2A == false) {
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/* Read SCU7c (silicon revision register) */
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ast_write32(ast, 0xf004, 0x1e6e0000);
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ast_write32(ast, 0xf000, 0x1);
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data = ast_read32(ast, 0x1207c);
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data &= 0x300;
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if (ast->chip == AST2300 && data == 0x0) /* ast1300 */
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ast->support_wide_screen = true;
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if (ast->chip == AST2400 && data == 0x100) /* ast1400 */
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ast->support_wide_screen = true;
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}
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}
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break;
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}
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@ -216,80 +224,81 @@ static int ast_get_dram_info(struct drm_device *dev)
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uint32_t data, data2;
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uint32_t denum, num, div, ref_pll;
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ast_write32(ast, 0xf004, 0x1e6e0000);
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ast_write32(ast, 0xf000, 0x1);
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ast_write32(ast, 0x10000, 0xfc600309);
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do {
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if (pci_channel_offline(dev->pdev))
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return -EIO;
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} while (ast_read32(ast, 0x10000) != 0x01);
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data = ast_read32(ast, 0x10004);
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if (data & 0x40)
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if (ast->DisableP2A)
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{
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ast->dram_bus_width = 16;
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ast->dram_type = AST_DRAM_1Gx16;
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ast->mclk = 396;
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}
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else
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ast->dram_bus_width = 32;
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{
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ast_write32(ast, 0xf004, 0x1e6e0000);
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ast_write32(ast, 0xf000, 0x1);
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data = ast_read32(ast, 0x10004);
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if (ast->chip == AST2300 || ast->chip == AST2400) {
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switch (data & 0x03) {
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case 0:
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ast->dram_type = AST_DRAM_512Mx16;
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break;
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default:
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case 1:
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ast->dram_type = AST_DRAM_1Gx16;
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if (data & 0x40)
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ast->dram_bus_width = 16;
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else
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ast->dram_bus_width = 32;
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if (ast->chip == AST2300 || ast->chip == AST2400) {
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switch (data & 0x03) {
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case 0:
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ast->dram_type = AST_DRAM_512Mx16;
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break;
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default:
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case 1:
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ast->dram_type = AST_DRAM_1Gx16;
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break;
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case 2:
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ast->dram_type = AST_DRAM_2Gx16;
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break;
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case 3:
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ast->dram_type = AST_DRAM_4Gx16;
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break;
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}
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} else {
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switch (data & 0x0c) {
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case 0:
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case 4:
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ast->dram_type = AST_DRAM_512Mx16;
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break;
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case 8:
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if (data & 0x40)
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ast->dram_type = AST_DRAM_1Gx16;
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else
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ast->dram_type = AST_DRAM_512Mx32;
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break;
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case 0xc:
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ast->dram_type = AST_DRAM_1Gx32;
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break;
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}
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}
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data = ast_read32(ast, 0x10120);
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data2 = ast_read32(ast, 0x10170);
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if (data2 & 0x2000)
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ref_pll = 14318;
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else
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ref_pll = 12000;
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denum = data & 0x1f;
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num = (data & 0x3fe0) >> 5;
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data = (data & 0xc000) >> 14;
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switch (data) {
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case 3:
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div = 0x4;
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break;
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case 2:
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ast->dram_type = AST_DRAM_2Gx16;
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case 1:
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div = 0x2;
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break;
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case 3:
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ast->dram_type = AST_DRAM_4Gx16;
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break;
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}
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} else {
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switch (data & 0x0c) {
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case 0:
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case 4:
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ast->dram_type = AST_DRAM_512Mx16;
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break;
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case 8:
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if (data & 0x40)
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ast->dram_type = AST_DRAM_1Gx16;
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else
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ast->dram_type = AST_DRAM_512Mx32;
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break;
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case 0xc:
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ast->dram_type = AST_DRAM_1Gx32;
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default:
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div = 0x1;
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break;
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}
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ast->mclk = ref_pll * (num + 2) / (denum + 2) * (div * 1000);
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}
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data = ast_read32(ast, 0x10120);
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data2 = ast_read32(ast, 0x10170);
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if (data2 & 0x2000)
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ref_pll = 14318;
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else
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ref_pll = 12000;
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denum = data & 0x1f;
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num = (data & 0x3fe0) >> 5;
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data = (data & 0xc000) >> 14;
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switch (data) {
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case 3:
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div = 0x4;
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break;
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case 2:
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case 1:
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div = 0x2;
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break;
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default:
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div = 0x1;
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break;
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}
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ast->mclk = ref_pll * (num + 2) / (denum + 2) * (div * 1000);
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return 0;
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}
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|
|
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|
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@ -379,12 +379,20 @@ void ast_post_gpu(struct drm_device *dev)
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ast_open_key(ast);
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ast_set_def_ext_reg(dev);
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|
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if (ast->chip == AST2300 || ast->chip == AST2400)
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ast_init_dram_2300(dev);
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else
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ast_init_dram_reg(dev);
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if (ast->DisableP2A == false)
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{
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if (ast->chip == AST2300 || ast->chip == AST2400)
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ast_init_dram_2300(dev);
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else
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ast_init_dram_reg(dev);
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ast_init_3rdtx(dev);
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ast_init_3rdtx(dev);
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}
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else
|
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{
|
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if (ast->tx_chip_type != AST_TX_NONE)
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); /* Enable DVO */
|
||||
}
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}
|
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|
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/* AST 2300 DRAM settings */
|
||||
|
|
|
|||
|
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@ -286,15 +286,15 @@ drm_atomic_get_crtc_state(struct drm_atomic_state *state,
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|||
EXPORT_SYMBOL(drm_atomic_get_crtc_state);
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|
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static void set_out_fence_for_crtc(struct drm_atomic_state *state,
|
||||
struct drm_crtc *crtc, s64 __user *fence_ptr)
|
||||
struct drm_crtc *crtc, s32 __user *fence_ptr)
|
||||
{
|
||||
state->crtcs[drm_crtc_index(crtc)].out_fence_ptr = fence_ptr;
|
||||
}
|
||||
|
||||
static s64 __user *get_out_fence_for_crtc(struct drm_atomic_state *state,
|
||||
static s32 __user *get_out_fence_for_crtc(struct drm_atomic_state *state,
|
||||
struct drm_crtc *crtc)
|
||||
{
|
||||
s64 __user *fence_ptr;
|
||||
s32 __user *fence_ptr;
|
||||
|
||||
fence_ptr = state->crtcs[drm_crtc_index(crtc)].out_fence_ptr;
|
||||
state->crtcs[drm_crtc_index(crtc)].out_fence_ptr = NULL;
|
||||
|
|
@ -505,7 +505,7 @@ int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
|
|||
state->color_mgmt_changed |= replaced;
|
||||
return ret;
|
||||
} else if (property == config->prop_out_fence_ptr) {
|
||||
s64 __user *fence_ptr = u64_to_user_ptr(val);
|
||||
s32 __user *fence_ptr = u64_to_user_ptr(val);
|
||||
|
||||
if (!fence_ptr)
|
||||
return 0;
|
||||
|
|
@ -1902,7 +1902,7 @@ EXPORT_SYMBOL(drm_atomic_clean_old_fb);
|
|||
*/
|
||||
|
||||
struct drm_out_fence_state {
|
||||
s64 __user *out_fence_ptr;
|
||||
s32 __user *out_fence_ptr;
|
||||
struct sync_file *sync_file;
|
||||
int fd;
|
||||
};
|
||||
|
|
@ -1939,7 +1939,7 @@ static int prepare_crtc_signaling(struct drm_device *dev,
|
|||
return 0;
|
||||
|
||||
for_each_crtc_in_state(state, crtc, crtc_state, i) {
|
||||
u64 __user *fence_ptr;
|
||||
s32 __user *fence_ptr;
|
||||
|
||||
fence_ptr = get_out_fence_for_crtc(crtc_state->state, crtc);
|
||||
|
||||
|
|
@ -2019,13 +2019,16 @@ static void complete_crtc_signaling(struct drm_device *dev,
|
|||
}
|
||||
|
||||
for_each_crtc_in_state(state, crtc, crtc_state, i) {
|
||||
struct drm_pending_vblank_event *event = crtc_state->event;
|
||||
/*
|
||||
* TEST_ONLY and PAGE_FLIP_EVENT are mutually
|
||||
* exclusive, if they weren't, this code should be
|
||||
* called on success for TEST_ONLY too.
|
||||
* Free the allocated event. drm_atomic_helper_setup_commit
|
||||
* can allocate an event too, so only free it if it's ours
|
||||
* to prevent a double free in drm_atomic_state_clear.
|
||||
*/
|
||||
if (crtc_state->event)
|
||||
drm_event_cancel_free(dev, &crtc_state->event->base);
|
||||
if (event && (event->base.fence || event->base.file_priv)) {
|
||||
drm_event_cancel_free(dev, &event->base);
|
||||
crtc_state->event = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
if (!fence_state)
|
||||
|
|
|
|||
|
|
@ -378,6 +378,9 @@ int drm_connector_register(struct drm_connector *connector)
|
|||
{
|
||||
int ret = 0;
|
||||
|
||||
if (!connector->dev->registered)
|
||||
return 0;
|
||||
|
||||
mutex_lock(&connector->mutex);
|
||||
if (connector->registered)
|
||||
goto unlock;
|
||||
|
|
|
|||
|
|
@ -776,6 +776,8 @@ int drm_dev_register(struct drm_device *dev, unsigned long flags)
|
|||
if (ret)
|
||||
goto err_minors;
|
||||
|
||||
dev->registered = true;
|
||||
|
||||
if (dev->driver->load) {
|
||||
ret = dev->driver->load(dev, flags);
|
||||
if (ret)
|
||||
|
|
@ -823,6 +825,8 @@ void drm_dev_unregister(struct drm_device *dev)
|
|||
|
||||
drm_lastclose(dev);
|
||||
|
||||
dev->registered = false;
|
||||
|
||||
if (drm_core_check_feature(dev, DRIVER_MODESET))
|
||||
drm_modeset_unregister_all(dev);
|
||||
|
||||
|
|
|
|||
|
|
@ -481,7 +481,6 @@ struct parser_exec_state {
|
|||
(s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
|
||||
|
||||
static unsigned long bypass_scan_mask = 0;
|
||||
static bool bypass_batch_buffer_scan = true;
|
||||
|
||||
/* ring ALL, type = 0 */
|
||||
static struct sub_op_bits sub_op_mi[] = {
|
||||
|
|
@ -1543,9 +1542,6 @@ static int batch_buffer_needs_scan(struct parser_exec_state *s)
|
|||
{
|
||||
struct intel_gvt *gvt = s->vgpu->gvt;
|
||||
|
||||
if (bypass_batch_buffer_scan)
|
||||
return 0;
|
||||
|
||||
if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)) {
|
||||
/* BDW decides privilege based on address space */
|
||||
if (cmd_val(s, 0) & (1 << 8))
|
||||
|
|
|
|||
|
|
@ -364,58 +364,30 @@ static void free_workload(struct intel_vgpu_workload *workload)
|
|||
#define get_desc_from_elsp_dwords(ed, i) \
|
||||
((struct execlist_ctx_descriptor_format *)&((ed)->data[i * 2]))
|
||||
|
||||
|
||||
#define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
|
||||
#define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
|
||||
static int set_gma_to_bb_cmd(struct intel_shadow_bb_entry *entry_obj,
|
||||
unsigned long add, int gmadr_bytes)
|
||||
{
|
||||
if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8))
|
||||
return -1;
|
||||
|
||||
*((u32 *)(entry_obj->bb_start_cmd_va + (1 << 2))) = add &
|
||||
BATCH_BUFFER_ADDR_MASK;
|
||||
if (gmadr_bytes == 8) {
|
||||
*((u32 *)(entry_obj->bb_start_cmd_va + (2 << 2))) =
|
||||
add & BATCH_BUFFER_ADDR_HIGH_MASK;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
|
||||
{
|
||||
int gmadr_bytes = workload->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
|
||||
const int gmadr_bytes = workload->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
|
||||
struct intel_shadow_bb_entry *entry_obj;
|
||||
|
||||
/* pin the gem object to ggtt */
|
||||
if (!list_empty(&workload->shadow_bb)) {
|
||||
struct intel_shadow_bb_entry *entry_obj =
|
||||
list_first_entry(&workload->shadow_bb,
|
||||
struct intel_shadow_bb_entry,
|
||||
list);
|
||||
struct intel_shadow_bb_entry *temp;
|
||||
list_for_each_entry(entry_obj, &workload->shadow_bb, list) {
|
||||
struct i915_vma *vma;
|
||||
|
||||
list_for_each_entry_safe(entry_obj, temp, &workload->shadow_bb,
|
||||
list) {
|
||||
struct i915_vma *vma;
|
||||
|
||||
vma = i915_gem_object_ggtt_pin(entry_obj->obj, NULL, 0,
|
||||
4, 0);
|
||||
if (IS_ERR(vma)) {
|
||||
gvt_err("Cannot pin\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* FIXME: we are not tracking our pinned VMA leaving it
|
||||
* up to the core to fix up the stray pin_count upon
|
||||
* free.
|
||||
*/
|
||||
|
||||
/* update the relocate gma with shadow batch buffer*/
|
||||
set_gma_to_bb_cmd(entry_obj,
|
||||
i915_ggtt_offset(vma),
|
||||
gmadr_bytes);
|
||||
vma = i915_gem_object_ggtt_pin(entry_obj->obj, NULL, 0, 4, 0);
|
||||
if (IS_ERR(vma)) {
|
||||
gvt_err("Cannot pin\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* FIXME: we are not tracking our pinned VMA leaving it
|
||||
* up to the core to fix up the stray pin_count upon
|
||||
* free.
|
||||
*/
|
||||
|
||||
/* update the relocate gma with shadow batch buffer*/
|
||||
entry_obj->bb_start_cmd_va[1] = i915_ggtt_offset(vma);
|
||||
if (gmadr_bytes == 8)
|
||||
entry_obj->bb_start_cmd_va[2] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -826,7 +798,7 @@ int intel_vgpu_init_execlist(struct intel_vgpu *vgpu)
|
|||
INIT_LIST_HEAD(&vgpu->workload_q_head[i]);
|
||||
}
|
||||
|
||||
vgpu->workloads = kmem_cache_create("gvt-g vgpu workload",
|
||||
vgpu->workloads = kmem_cache_create("gvt-g_vgpu_workload",
|
||||
sizeof(struct intel_vgpu_workload), 0,
|
||||
SLAB_HWCACHE_ALIGN,
|
||||
NULL);
|
||||
|
|
|
|||
|
|
@ -262,8 +262,8 @@ static struct intel_vgpu_type *intel_gvt_find_vgpu_type(struct intel_gvt *gvt,
|
|||
return NULL;
|
||||
}
|
||||
|
||||
static ssize_t available_instance_show(struct kobject *kobj, struct device *dev,
|
||||
char *buf)
|
||||
static ssize_t available_instances_show(struct kobject *kobj,
|
||||
struct device *dev, char *buf)
|
||||
{
|
||||
struct intel_vgpu_type *type;
|
||||
unsigned int num = 0;
|
||||
|
|
@ -301,12 +301,12 @@ static ssize_t description_show(struct kobject *kobj, struct device *dev,
|
|||
type->fence);
|
||||
}
|
||||
|
||||
static MDEV_TYPE_ATTR_RO(available_instance);
|
||||
static MDEV_TYPE_ATTR_RO(available_instances);
|
||||
static MDEV_TYPE_ATTR_RO(device_api);
|
||||
static MDEV_TYPE_ATTR_RO(description);
|
||||
|
||||
static struct attribute *type_attrs[] = {
|
||||
&mdev_type_attr_available_instance.attr,
|
||||
&mdev_type_attr_available_instances.attr,
|
||||
&mdev_type_attr_device_api.attr,
|
||||
&mdev_type_attr_description.attr,
|
||||
NULL,
|
||||
|
|
|
|||
|
|
@ -113,7 +113,7 @@ struct intel_shadow_bb_entry {
|
|||
struct drm_i915_gem_object *obj;
|
||||
void *va;
|
||||
unsigned long len;
|
||||
void *bb_start_cmd_va;
|
||||
u32 *bb_start_cmd_va;
|
||||
};
|
||||
|
||||
#define workload_q_head(vgpu, ring_id) \
|
||||
|
|
|
|||
|
|
@ -213,7 +213,8 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
|
|||
} else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
|
||||
dev_priv->pch_type = PCH_KBP;
|
||||
DRM_DEBUG_KMS("Found KabyPoint PCH\n");
|
||||
WARN_ON(!IS_KABYLAKE(dev_priv));
|
||||
WARN_ON(!IS_SKYLAKE(dev_priv) &&
|
||||
!IS_KABYLAKE(dev_priv));
|
||||
} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
|
||||
(id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
|
||||
((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
|
||||
|
|
@ -2377,7 +2378,7 @@ static int intel_runtime_suspend(struct device *kdev)
|
|||
|
||||
assert_forcewakes_inactive(dev_priv);
|
||||
|
||||
if (!IS_VALLEYVIEW(dev_priv) || !IS_CHERRYVIEW(dev_priv))
|
||||
if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
|
||||
intel_hpd_poll_init(dev_priv);
|
||||
|
||||
DRM_DEBUG_KMS("Device suspended\n");
|
||||
|
|
@ -2426,6 +2427,7 @@ static int intel_runtime_resume(struct device *kdev)
|
|||
* we can do is to hope that things will still work (and disable RPM).
|
||||
*/
|
||||
i915_gem_init_swizzling(dev_priv);
|
||||
i915_gem_restore_fences(dev_priv);
|
||||
|
||||
intel_runtime_pm_enable_interrupts(dev_priv);
|
||||
|
||||
|
|
|
|||
|
|
@ -2242,6 +2242,11 @@ struct drm_i915_private {
|
|||
|
||||
struct i915_frontbuffer_tracking fb_tracking;
|
||||
|
||||
struct intel_atomic_helper {
|
||||
struct llist_head free_list;
|
||||
struct work_struct free_work;
|
||||
} atomic_helper;
|
||||
|
||||
u16 orig_clock;
|
||||
|
||||
bool mchbar_need_disable;
|
||||
|
|
|
|||
|
|
@ -2009,8 +2009,16 @@ void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv)
|
|||
for (i = 0; i < dev_priv->num_fence_regs; i++) {
|
||||
struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
|
||||
|
||||
if (WARN_ON(reg->pin_count))
|
||||
continue;
|
||||
/* Ideally we want to assert that the fence register is not
|
||||
* live at this point (i.e. that no piece of code will be
|
||||
* trying to write through fence + GTT, as that both violates
|
||||
* our tracking of activity and associated locking/barriers,
|
||||
* but also is illegal given that the hw is powered down).
|
||||
*
|
||||
* Previously we used reg->pin_count as a "liveness" indicator.
|
||||
* That is not sufficient, and we need a more fine-grained
|
||||
* tool if we want to have a sanity check here.
|
||||
*/
|
||||
|
||||
if (!reg->vma)
|
||||
continue;
|
||||
|
|
@ -3513,7 +3521,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
|
|||
vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
|
||||
|
||||
/* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */
|
||||
if (obj->cache_dirty) {
|
||||
if (obj->cache_dirty || obj->base.write_domain == I915_GEM_DOMAIN_CPU) {
|
||||
i915_gem_clflush_object(obj, true);
|
||||
intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1180,14 +1180,14 @@ validate_exec_list(struct drm_device *dev,
|
|||
if (exec[i].offset !=
|
||||
gen8_canonical_addr(exec[i].offset & PAGE_MASK))
|
||||
return -EINVAL;
|
||||
|
||||
/* From drm_mm perspective address space is continuous,
|
||||
* so from this point we're always using non-canonical
|
||||
* form internally.
|
||||
*/
|
||||
exec[i].offset = gen8_noncanonical_addr(exec[i].offset);
|
||||
}
|
||||
|
||||
/* From drm_mm perspective address space is continuous,
|
||||
* so from this point we're always using non-canonical
|
||||
* form internally.
|
||||
*/
|
||||
exec[i].offset = gen8_noncanonical_addr(exec[i].offset);
|
||||
|
||||
if (exec[i].alignment && !is_power_of_2(exec[i].alignment))
|
||||
return -EINVAL;
|
||||
|
||||
|
|
|
|||
|
|
@ -54,8 +54,16 @@ i915_gem_object_get_pages_internal(struct drm_i915_gem_object *obj)
|
|||
|
||||
max_order = MAX_ORDER;
|
||||
#ifdef CONFIG_SWIOTLB
|
||||
if (swiotlb_nr_tbl()) /* minimum max swiotlb size is IO_TLB_SEGSIZE */
|
||||
max_order = min(max_order, ilog2(IO_TLB_SEGPAGES));
|
||||
if (swiotlb_nr_tbl()) {
|
||||
unsigned int max_segment;
|
||||
|
||||
max_segment = swiotlb_max_segment();
|
||||
if (max_segment) {
|
||||
max_segment = max_t(unsigned int, max_segment,
|
||||
PAGE_SIZE) >> PAGE_SHIFT;
|
||||
max_order = min(max_order, ilog2(max_segment));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
gfp = GFP_KERNEL | __GFP_HIGHMEM | __GFP_RECLAIMABLE;
|
||||
|
|
|
|||
|
|
@ -499,6 +499,7 @@ static bool intel_crt_detect_ddc(struct drm_connector *connector)
|
|||
struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
|
||||
struct edid *edid;
|
||||
struct i2c_adapter *i2c;
|
||||
bool ret = false;
|
||||
|
||||
BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
|
||||
|
||||
|
|
@ -515,17 +516,17 @@ static bool intel_crt_detect_ddc(struct drm_connector *connector)
|
|||
*/
|
||||
if (!is_digital) {
|
||||
DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
|
||||
return true;
|
||||
ret = true;
|
||||
} else {
|
||||
DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
|
||||
}
|
||||
|
||||
DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
|
||||
} else {
|
||||
DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
|
||||
}
|
||||
|
||||
kfree(edid);
|
||||
|
||||
return false;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static enum drm_connector_status
|
||||
|
|
|
|||
|
|
@ -2578,8 +2578,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
|
|||
* We only keep the x/y offsets, so push all of the
|
||||
* gtt offset into the x/y offsets.
|
||||
*/
|
||||
_intel_adjust_tile_offset(&x, &y, tile_size,
|
||||
tile_width, tile_height, pitch_tiles,
|
||||
_intel_adjust_tile_offset(&x, &y,
|
||||
tile_width, tile_height,
|
||||
tile_size, pitch_tiles,
|
||||
gtt_offset_rotated * tile_size, 0);
|
||||
|
||||
gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
|
||||
|
|
@ -4252,10 +4253,10 @@ static void page_flip_completed(struct intel_crtc *intel_crtc)
|
|||
drm_crtc_vblank_put(&intel_crtc->base);
|
||||
|
||||
wake_up_all(&dev_priv->pending_flip_queue);
|
||||
queue_work(dev_priv->wq, &work->unpin_work);
|
||||
|
||||
trace_i915_flip_complete(intel_crtc->plane,
|
||||
work->pending_flip_obj);
|
||||
|
||||
queue_work(dev_priv->wq, &work->unpin_work);
|
||||
}
|
||||
|
||||
static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
|
||||
|
|
@ -6881,6 +6882,12 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
|
|||
}
|
||||
|
||||
state = drm_atomic_state_alloc(crtc->dev);
|
||||
if (!state) {
|
||||
DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
|
||||
crtc->base.id, crtc->name);
|
||||
return;
|
||||
}
|
||||
|
||||
state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
|
||||
|
||||
/* Everything's already locked, -EDEADLK can't happen. */
|
||||
|
|
@ -14562,8 +14569,14 @@ intel_atomic_commit_ready(struct i915_sw_fence *fence,
|
|||
break;
|
||||
|
||||
case FENCE_FREE:
|
||||
drm_atomic_state_put(&state->base);
|
||||
break;
|
||||
{
|
||||
struct intel_atomic_helper *helper =
|
||||
&to_i915(state->base.dev)->atomic_helper;
|
||||
|
||||
if (llist_add(&state->freed, &helper->free_list))
|
||||
schedule_work(&helper->free_work);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return NOTIFY_DONE;
|
||||
|
|
@ -16586,6 +16599,18 @@ fail:
|
|||
drm_modeset_acquire_fini(&ctx);
|
||||
}
|
||||
|
||||
static void intel_atomic_helper_free_state(struct work_struct *work)
|
||||
{
|
||||
struct drm_i915_private *dev_priv =
|
||||
container_of(work, typeof(*dev_priv), atomic_helper.free_work);
|
||||
struct intel_atomic_state *state, *next;
|
||||
struct llist_node *freed;
|
||||
|
||||
freed = llist_del_all(&dev_priv->atomic_helper.free_list);
|
||||
llist_for_each_entry_safe(state, next, freed, freed)
|
||||
drm_atomic_state_put(&state->base);
|
||||
}
|
||||
|
||||
int intel_modeset_init(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
|
|
@ -16605,6 +16630,9 @@ int intel_modeset_init(struct drm_device *dev)
|
|||
|
||||
dev->mode_config.funcs = &intel_mode_funcs;
|
||||
|
||||
INIT_WORK(&dev_priv->atomic_helper.free_work,
|
||||
intel_atomic_helper_free_state);
|
||||
|
||||
intel_init_quirks(dev);
|
||||
|
||||
intel_init_pm(dev_priv);
|
||||
|
|
@ -17262,6 +17290,9 @@ void intel_modeset_cleanup(struct drm_device *dev)
|
|||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
|
||||
flush_work(&dev_priv->atomic_helper.free_work);
|
||||
WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
|
||||
|
||||
intel_disable_gt_powersave(dev_priv);
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -1855,7 +1855,8 @@ bxt_get_dpll(struct intel_crtc *crtc,
|
|||
return NULL;
|
||||
|
||||
if ((encoder->type == INTEL_OUTPUT_DP ||
|
||||
encoder->type == INTEL_OUTPUT_EDP) &&
|
||||
encoder->type == INTEL_OUTPUT_EDP ||
|
||||
encoder->type == INTEL_OUTPUT_DP_MST) &&
|
||||
!bxt_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state))
|
||||
return NULL;
|
||||
|
||||
|
|
|
|||
|
|
@ -371,6 +371,8 @@ struct intel_atomic_state {
|
|||
struct skl_wm_values wm_results;
|
||||
|
||||
struct i915_sw_fence commit_ready;
|
||||
|
||||
struct llist_node freed;
|
||||
};
|
||||
|
||||
struct intel_plane_state {
|
||||
|
|
|
|||
|
|
@ -222,6 +222,7 @@ nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype)
|
|||
uint32_t mpllP;
|
||||
|
||||
pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
|
||||
mpllP = (mpllP >> 8) & 0xf;
|
||||
if (!mpllP)
|
||||
mpllP = 4;
|
||||
|
||||
|
|
@ -232,7 +233,7 @@ nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype)
|
|||
uint32_t clock;
|
||||
|
||||
pci_read_config_dword(pci_get_bus_and_slot(0, 5), 0x4c, &clock);
|
||||
return clock;
|
||||
return clock / 1000;
|
||||
}
|
||||
|
||||
ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals);
|
||||
|
|
|
|||
|
|
@ -414,7 +414,8 @@ nouveau_display_init(struct drm_device *dev)
|
|||
return ret;
|
||||
|
||||
/* enable polling for external displays */
|
||||
drm_kms_helper_poll_enable(dev);
|
||||
if (!dev->mode_config.poll_enabled)
|
||||
drm_kms_helper_poll_enable(dev);
|
||||
|
||||
/* enable hotplug interrupts */
|
||||
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
|
||||
|
|
|
|||
|
|
@ -773,7 +773,10 @@ nouveau_pmops_runtime_resume(struct device *dev)
|
|||
pci_set_master(pdev);
|
||||
|
||||
ret = nouveau_do_resume(drm_dev, true);
|
||||
drm_kms_helper_poll_enable(drm_dev);
|
||||
|
||||
if (!drm_dev->mode_config.poll_enabled)
|
||||
drm_kms_helper_poll_enable(drm_dev);
|
||||
|
||||
/* do magic */
|
||||
nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25));
|
||||
vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
|
||||
|
|
|
|||
|
|
@ -167,6 +167,8 @@ struct nouveau_drm {
|
|||
struct backlight_device *backlight;
|
||||
struct list_head bl_connectors;
|
||||
struct work_struct hpd_work;
|
||||
struct work_struct fbcon_work;
|
||||
int fbcon_new_state;
|
||||
#ifdef CONFIG_ACPI
|
||||
struct notifier_block acpi_nb;
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -473,19 +473,43 @@ static const struct drm_fb_helper_funcs nouveau_fbcon_helper_funcs = {
|
|||
.fb_probe = nouveau_fbcon_create,
|
||||
};
|
||||
|
||||
static void
|
||||
nouveau_fbcon_set_suspend_work(struct work_struct *work)
|
||||
{
|
||||
struct nouveau_drm *drm = container_of(work, typeof(*drm), fbcon_work);
|
||||
int state = READ_ONCE(drm->fbcon_new_state);
|
||||
|
||||
if (state == FBINFO_STATE_RUNNING)
|
||||
pm_runtime_get_sync(drm->dev->dev);
|
||||
|
||||
console_lock();
|
||||
if (state == FBINFO_STATE_RUNNING)
|
||||
nouveau_fbcon_accel_restore(drm->dev);
|
||||
drm_fb_helper_set_suspend(&drm->fbcon->helper, state);
|
||||
if (state != FBINFO_STATE_RUNNING)
|
||||
nouveau_fbcon_accel_save_disable(drm->dev);
|
||||
console_unlock();
|
||||
|
||||
if (state == FBINFO_STATE_RUNNING) {
|
||||
pm_runtime_mark_last_busy(drm->dev->dev);
|
||||
pm_runtime_put_sync(drm->dev->dev);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
nouveau_fbcon_set_suspend(struct drm_device *dev, int state)
|
||||
{
|
||||
struct nouveau_drm *drm = nouveau_drm(dev);
|
||||
if (drm->fbcon) {
|
||||
console_lock();
|
||||
if (state == FBINFO_STATE_RUNNING)
|
||||
nouveau_fbcon_accel_restore(dev);
|
||||
drm_fb_helper_set_suspend(&drm->fbcon->helper, state);
|
||||
if (state != FBINFO_STATE_RUNNING)
|
||||
nouveau_fbcon_accel_save_disable(dev);
|
||||
console_unlock();
|
||||
}
|
||||
|
||||
if (!drm->fbcon)
|
||||
return;
|
||||
|
||||
drm->fbcon_new_state = state;
|
||||
/* Since runtime resume can happen as a result of a sysfs operation,
|
||||
* it's possible we already have the console locked. So handle fbcon
|
||||
* init/deinit from a seperate work thread
|
||||
*/
|
||||
schedule_work(&drm->fbcon_work);
|
||||
}
|
||||
|
||||
int
|
||||
|
|
@ -505,6 +529,7 @@ nouveau_fbcon_init(struct drm_device *dev)
|
|||
return -ENOMEM;
|
||||
|
||||
drm->fbcon = fbcon;
|
||||
INIT_WORK(&drm->fbcon_work, nouveau_fbcon_set_suspend_work);
|
||||
|
||||
drm_fb_helper_prepare(dev, &fbcon->helper, &nouveau_fbcon_helper_funcs);
|
||||
|
||||
|
|
|
|||
|
|
@ -99,6 +99,7 @@ struct nv84_fence_priv {
|
|||
struct nouveau_bo *bo;
|
||||
struct nouveau_bo *bo_gart;
|
||||
u32 *suspend;
|
||||
struct mutex mutex;
|
||||
};
|
||||
|
||||
int nv84_fence_context_new(struct nouveau_channel *);
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ nouveau_led(struct drm_device *dev)
|
|||
}
|
||||
|
||||
/* nouveau_led.c */
|
||||
#if IS_ENABLED(CONFIG_LEDS_CLASS)
|
||||
#if IS_REACHABLE(CONFIG_LEDS_CLASS)
|
||||
int nouveau_led_init(struct drm_device *dev);
|
||||
void nouveau_led_suspend(struct drm_device *dev);
|
||||
void nouveau_led_resume(struct drm_device *dev);
|
||||
|
|
|
|||
|
|
@ -313,7 +313,8 @@ usif_ioctl(struct drm_file *filp, void __user *user, u32 argc)
|
|||
if (!(ret = nvif_unpack(-ENOSYS, &data, &size, argv->v0, 0, 0, true))) {
|
||||
/* block access to objects not created via this interface */
|
||||
owner = argv->v0.owner;
|
||||
if (argv->v0.object == 0ULL)
|
||||
if (argv->v0.object == 0ULL &&
|
||||
argv->v0.type != NVIF_IOCTL_V0_DEL)
|
||||
argv->v0.owner = NVDRM_OBJECT_ANY; /* except client */
|
||||
else
|
||||
argv->v0.owner = NVDRM_OBJECT_USIF;
|
||||
|
|
|
|||
|
|
@ -4050,6 +4050,11 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
|
|||
}
|
||||
}
|
||||
|
||||
for_each_crtc_in_state(state, crtc, crtc_state, i) {
|
||||
if (crtc->state->event)
|
||||
drm_crtc_vblank_get(crtc);
|
||||
}
|
||||
|
||||
/* Update plane(s). */
|
||||
for_each_plane_in_state(state, plane, plane_state, i) {
|
||||
struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane->state);
|
||||
|
|
@ -4099,6 +4104,7 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
|
|||
drm_crtc_send_vblank_event(crtc, crtc->state->event);
|
||||
spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
|
||||
crtc->state->event = NULL;
|
||||
drm_crtc_vblank_put(crtc);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -107,8 +107,10 @@ nv84_fence_context_del(struct nouveau_channel *chan)
|
|||
struct nv84_fence_chan *fctx = chan->fence;
|
||||
|
||||
nouveau_bo_wr32(priv->bo, chan->chid * 16 / 4, fctx->base.sequence);
|
||||
mutex_lock(&priv->mutex);
|
||||
nouveau_bo_vma_del(priv->bo, &fctx->vma_gart);
|
||||
nouveau_bo_vma_del(priv->bo, &fctx->vma);
|
||||
mutex_unlock(&priv->mutex);
|
||||
nouveau_fence_context_del(&fctx->base);
|
||||
chan->fence = NULL;
|
||||
nouveau_fence_context_free(&fctx->base);
|
||||
|
|
@ -134,11 +136,13 @@ nv84_fence_context_new(struct nouveau_channel *chan)
|
|||
fctx->base.sync32 = nv84_fence_sync32;
|
||||
fctx->base.sequence = nv84_fence_read(chan);
|
||||
|
||||
mutex_lock(&priv->mutex);
|
||||
ret = nouveau_bo_vma_add(priv->bo, cli->vm, &fctx->vma);
|
||||
if (ret == 0) {
|
||||
ret = nouveau_bo_vma_add(priv->bo_gart, cli->vm,
|
||||
&fctx->vma_gart);
|
||||
}
|
||||
mutex_unlock(&priv->mutex);
|
||||
|
||||
if (ret)
|
||||
nv84_fence_context_del(chan);
|
||||
|
|
@ -212,6 +216,8 @@ nv84_fence_create(struct nouveau_drm *drm)
|
|||
priv->base.context_base = dma_fence_context_alloc(priv->base.contexts);
|
||||
priv->base.uevent = true;
|
||||
|
||||
mutex_init(&priv->mutex);
|
||||
|
||||
/* Use VRAM if there is any ; otherwise fallback to system memory */
|
||||
domain = drm->client.device.info.ram_size != 0 ? TTM_PL_FLAG_VRAM :
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -59,7 +59,7 @@ gt215_hda_eld(NV50_DISP_MTHD_V1)
|
|||
);
|
||||
}
|
||||
for (i = 0; i < size; i++)
|
||||
nvkm_wr32(device, 0x61c440 + soff, (i << 8) | args->v0.data[0]);
|
||||
nvkm_wr32(device, 0x61c440 + soff, (i << 8) | args->v0.data[i]);
|
||||
for (; i < 0x60; i++)
|
||||
nvkm_wr32(device, 0x61c440 + soff, (i << 8));
|
||||
nvkm_mask(device, 0x61c448 + soff, 0x80000003, 0x80000003);
|
||||
|
|
|
|||
|
|
@ -433,8 +433,6 @@ nv50_disp_dptmds_war(struct nvkm_device *device)
|
|||
case 0x94:
|
||||
case 0x96:
|
||||
case 0x98:
|
||||
case 0xaa:
|
||||
case 0xac:
|
||||
return true;
|
||||
default:
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -97,9 +97,10 @@
|
|||
* 2.46.0 - Add PFP_SYNC_ME support on evergreen
|
||||
* 2.47.0 - Add UVD_NO_OP register support
|
||||
* 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
|
||||
* 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values
|
||||
*/
|
||||
#define KMS_DRIVER_MAJOR 2
|
||||
#define KMS_DRIVER_MINOR 48
|
||||
#define KMS_DRIVER_MINOR 49
|
||||
#define KMS_DRIVER_PATCHLEVEL 0
|
||||
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
|
||||
void radeon_driver_unload_kms(struct drm_device *dev);
|
||||
|
|
@ -366,11 +367,10 @@ static void
|
|||
radeon_pci_shutdown(struct pci_dev *pdev)
|
||||
{
|
||||
/* if we are running in a VM, make sure the device
|
||||
* torn down properly on reboot/shutdown.
|
||||
* unfortunately we can't detect certain
|
||||
* hypervisors so just do this all the time.
|
||||
* torn down properly on reboot/shutdown
|
||||
*/
|
||||
radeon_pci_remove(pdev);
|
||||
if (radeon_device_is_virtual())
|
||||
radeon_pci_remove(pdev);
|
||||
}
|
||||
|
||||
static int radeon_pmops_suspend(struct device *dev)
|
||||
|
|
|
|||
|
|
@ -220,8 +220,8 @@ int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
|
|||
|
||||
man = &rdev->mman.bdev.man[TTM_PL_VRAM];
|
||||
|
||||
args->vram_size = rdev->mc.real_vram_size;
|
||||
args->vram_visible = (u64)man->size << PAGE_SHIFT;
|
||||
args->vram_size = (u64)man->size << PAGE_SHIFT;
|
||||
args->vram_visible = rdev->mc.visible_vram_size;
|
||||
args->vram_visible -= rdev->vram_pin_size;
|
||||
args->gart_size = rdev->mc.gtt_size;
|
||||
args->gart_size -= rdev->gart_pin_size;
|
||||
|
|
|
|||
|
|
@ -843,7 +843,7 @@ static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
|
|||
|
||||
}
|
||||
|
||||
__drm_atomic_helper_crtc_destroy_state(state);
|
||||
drm_atomic_helper_crtc_destroy_state(crtc, state);
|
||||
}
|
||||
|
||||
static const struct drm_crtc_funcs vc4_crtc_funcs = {
|
||||
|
|
|
|||
|
|
@ -594,12 +594,14 @@ vc4_get_bcl(struct drm_device *dev, struct vc4_exec_info *exec)
|
|||
args->shader_rec_count);
|
||||
struct vc4_bo *bo;
|
||||
|
||||
if (uniforms_offset < shader_rec_offset ||
|
||||
if (shader_rec_offset < args->bin_cl_size ||
|
||||
uniforms_offset < shader_rec_offset ||
|
||||
exec_size < uniforms_offset ||
|
||||
args->shader_rec_count >= (UINT_MAX /
|
||||
sizeof(struct vc4_shader_state)) ||
|
||||
temp_size < exec_size) {
|
||||
DRM_ERROR("overflow in exec arguments\n");
|
||||
ret = -EINVAL;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -858,7 +858,7 @@ struct drm_plane *vc4_plane_init(struct drm_device *dev,
|
|||
}
|
||||
}
|
||||
plane = &vc4_plane->base;
|
||||
ret = drm_universal_plane_init(dev, plane, 0xff,
|
||||
ret = drm_universal_plane_init(dev, plane, 0,
|
||||
&vc4_plane_funcs,
|
||||
formats, num_formats,
|
||||
type, NULL);
|
||||
|
|
|
|||
|
|
@ -461,7 +461,7 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec,
|
|||
}
|
||||
|
||||
ret = vc4_full_res_bounds_check(exec, *obj, surf);
|
||||
if (!ret)
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
Loading…
Reference in a new issue