A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-14 00:24:41 -04:00
Code Issues Projects Releases Packages Wiki Activity

ARM: dts: msm: Add the interrupts for the APPS TGU for holi

Browse source 
Update the APSS TGU node with interrupt numbers and corrected
the number of registers supported.

Change-Id: Idacedd7eea864bc2dfc0d58ec7333d1038a1a1a0
This commit is contained in:
Raghavendra Kakarla 2020-08-31 10:53:50 +05:30
commit 94acdb1975
2 changed files with 9 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

9
bindings/arm/coresight.txt
View file

@ -137,9 +137,10 @@ its hardware characteristcs.
* arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
use the SG mode on this system.
* Optional property for CATU :
* Optional property for CATU and APSS :
* interrupts : Exactly one SPI may be listed for reporting the address
error
error for CATU and four interrupts for TGU to get trigger from four
type of events.
* Required property for TPDAs:
@ -480,6 +481,10 @@ Example:
tgu-conditions = <4>;
tgu-regs = <4>;
tgu-timer-counters = <8>;
interrupts = <GIC_SPI 23 IRQ_TYPE_TRIGGER_HIGH>,
<GIC_SPI 24 IRQ_TYPE_TRIGGER_HIGH>,
<GIC_SPI 25 IRQ_TYPE_TRIGGER_HIGH>,
<GIC_SPI 26 IRQ_TYPE_TRIGGER_HIGH>;
coresight-name = "coresight-tgu-ipcb";

4
qcom/holi-coresight.dtsi
View file

@ -45,9 +45,9 @@
reg-names = "tgu-base";
tgu-steps = <3>;
tgu-conditions = <4>;
tgu-regs = <4>;
tgu-regs = <8>;
tgu-timer-counters = <8>;
interrupts = <0 23 1>, <0 24 1>, <0 25 1>, <0 26 1>;
coresight-name = "coresight-tgu-apss";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;