From 29c1abcc486447054d7ef296df2b98c0ec5947b6 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Thu, 2 Apr 2020 19:45:33 +0530 Subject: [PATCH 1/4] dt-bindings: clocks: Add clock controller bindings for SM8150 Add clock controller bindings to support SM8150. Change-Id: I78b757d5f0bedea75f95c7686ff90d7523e6e685 --- bindings/clock/qcom,camcc.txt | 5 +++++ bindings/clock/qcom,debugcc.txt | 1 + bindings/clock/qcom,dispcc.txt | 2 ++ bindings/clock/qcom,gcc.txt | 8 ++++---- bindings/clock/qcom,gpucc.txt | 5 ++++- bindings/clock/qcom,npucc.txt | 33 +++++++++++++++++++++++++++++++++ bindings/clock/qcom,scc.txt | 23 +++++++++++++++++++++++ bindings/clock/qcom,videocc.txt | 4 ++++ 8 files changed, 76 insertions(+), 5 deletions(-) create mode 100644 bindings/clock/qcom,npucc.txt create mode 100644 bindings/clock/qcom,scc.txt diff --git a/bindings/clock/qcom,camcc.txt b/bindings/clock/qcom,camcc.txt index aaa29dc09a63..b9e3105751a5 100644 --- a/bindings/clock/qcom,camcc.txt +++ b/bindings/clock/qcom,camcc.txt @@ -7,6 +7,11 @@ Required properties : "qcom,lahaina-camcc" "qcom,lahaina-camcc-v2" "qcom,shima-camcc" + "qcom,sm8150-camcc" + "qcom,sm8150-camcc-v2" + "qcom,sa8155-camcc" + "qcom,sa8155-camcc-v2" + - reg : shall contain base register location and length. - reg-names: names of registers listed in the same order as in the reg property. diff --git a/bindings/clock/qcom,debugcc.txt b/bindings/clock/qcom,debugcc.txt index 962376860141..c7d82f90a3c8 100644 --- a/bindings/clock/qcom,debugcc.txt +++ b/bindings/clock/qcom,debugcc.txt @@ -8,6 +8,7 @@ Required properties : "qcom,shima-debugcc" "qcom,holi-debugcc" "qcom,sdxlemur-debugcc" + "qcom,sm8150-debugcc" - qcom,gcc: phandle to the GCC device node. - qcom,videocc: phandle to the Video CC device node. diff --git a/bindings/clock/qcom,dispcc.txt b/bindings/clock/qcom,dispcc.txt index feaccf643a45..80bbef3710ec 100644 --- a/bindings/clock/qcom,dispcc.txt +++ b/bindings/clock/qcom,dispcc.txt @@ -9,6 +9,8 @@ Required properties : "qcom,lahaina-dispcc" "qcom,shima-dispcc" "qcom,holi-dispcc" + "qcom,sm8150-dispcc" + "qcom,sm8150-dispcc-v2" - reg : shall contain base register location and length. - #clock-cells : from common clock binding, shall contain 1. diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt index 617a1a5125dc..f72a8ff537e6 100644 --- a/bindings/clock/qcom,gcc.txt +++ b/bindings/clock/qcom,gcc.txt @@ -24,10 +24,10 @@ Required properties : "qcom,gcc-sdm660" "qcom,gcc-sdm845" "qcom,lahaina-gcc" - "qcom,gcc-sm8150" - "qcom,gcc-sm8150-v2" - "qcom,gcc-sa8155" - "qcom,gcc-sa8155-v2" + "qcom,sm8150-gcc" + "qcom,sm8150-gcc-v2" + "qcom,sa8155-gcc" + "qcom,sa8155-gcc-v2" "qcom,shima-gcc" "qcom,holi-gcc" "qcom,sdxlemur-gcc" diff --git a/bindings/clock/qcom,gpucc.txt b/bindings/clock/qcom,gpucc.txt index 4b987a3312c1..726c24257d24 100644 --- a/bindings/clock/qcom,gpucc.txt +++ b/bindings/clock/qcom,gpucc.txt @@ -5,7 +5,10 @@ Required properties : - compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc", "qcom,lahaina-gpucc", "qcom,shima-gpucc", - "qcom,holi-gpucc". + "qcom,holi-gpucc", + "qcom,sm8150-gpucc", + "qcom,sa8155-gpucc". + - reg: shall contain base register offset and size. - reg-names: names of registers listed in the same order as in the reg property. Must contain "cc_base". diff --git a/bindings/clock/qcom,npucc.txt b/bindings/clock/qcom,npucc.txt new file mode 100644 index 000000000000..b05c0012dae5 --- /dev/null +++ b/bindings/clock/qcom,npucc.txt @@ -0,0 +1,33 @@ +Qualcomm Technologies, Inc. NPU Clock & Reset Controller Binding +---------------------------------------------------------------- + +Required properties : +- compatible : shall contain only one of the following: + "qcom,sm8150-npucc" + "qcom,sm8150-npucc-v2" + "qcom,sa8155-npucc" + "qcom,sa8155-npucc-v2" + +- reg : shall contain base register location and length. +- reg-names: names of registers listed in the same order as in + the reg property. +- vdd_cx-supply: phandle to the CX rail that needs to be voted + on behalf of the NPU CC clocks. +- vdd_gdsc-supply: phandle to the NPU core GDSC that needs to be + toggled as part of the CRC sequence. +- #clock-cells : shall contain 1. +- #reset-cells : shall contain 1. + +Optional properties : +- #power-domain-cells : from generic power domain binding, shall contain 1 + +Example: + npucc: qcom,npucc { + compatible = "qcom,npucc-sm8150"; + reg = <0x9910000 0x10000>; + reg-names = "cc_base"; + vdd_cx-supply = <&pm8150l_s6_level>; + vdd_gdsc-supply = <&npu_core_gdsc>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/bindings/clock/qcom,scc.txt b/bindings/clock/qcom,scc.txt new file mode 100644 index 000000000000..fce28e82ddb9 --- /dev/null +++ b/bindings/clock/qcom,scc.txt @@ -0,0 +1,23 @@ +Qualcomm Technologies, Inc. Sensor Clock Controller Bindings + +Required properties: +- compatible : shall contain only one of the following: + "qcom,sm8150-scc" + "qcom,sm8150-scc-v2" + "qcom,sa8155-scc" + "qcom,sa8155-scc-v2" + +- reg: shall contain base register location and length. +- vdd_scc_cx-supply: the logic rail supply. +- #clock-cells: shall contain 1. + +Optional properties : +- #power-domain-cells : from generic power domain binding, shall contain 1 + +Example: + qcom,scc@2b10000 { + compatible = "qcom,scc-sm8150"; + reg = <0x2b10000 0x30000>; + vdd_scc_cx-supply = <&VDD_CX_LEVEL>; + #clock-cells = <1>; + }; diff --git a/bindings/clock/qcom,videocc.txt b/bindings/clock/qcom,videocc.txt index 9dd9a36d2743..e46fa2db829b 100644 --- a/bindings/clock/qcom,videocc.txt +++ b/bindings/clock/qcom,videocc.txt @@ -7,6 +7,10 @@ Required properties : "qcom,sdm845-videocc" "qcom,lahaina-videocc" "qcom,shima-videocc" + "qcom,sm8150-videocc" + "qcom,sm8150-videocc-v2" + "qcom,sa8155-videocc" + "qcom,sa8155-videocc-v2" - reg : shall contain base register location and length - #clock-cells : from common clock binding, shall contain 1. From 57a890a7d1eec2c66fff10d47af1a7caae920a3b Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Wed, 8 Jul 2020 19:50:39 +0530 Subject: [PATCH 2/4] dt-bindings: interconnect: update interconnect bindings Update interconnect device bindings. These devices can be used to describe any RPMH and NoC based interconnect devices. Change-Id: Ib20f2a56509528638c4604d2fe8f755f06e25fc4 --- bindings/interconnect/qcom,sm8150.txt | 3 --- 1 file changed, 3 deletions(-) diff --git a/bindings/interconnect/qcom,sm8150.txt b/bindings/interconnect/qcom,sm8150.txt index 247fc9655b8f..a0b636af3c11 100644 --- a/bindings/interconnect/qcom,sm8150.txt +++ b/bindings/interconnect/qcom,sm8150.txt @@ -21,9 +21,6 @@ Required properties : "qcom,sm8150-mc_virt"; "qcom,sm8150-mmss_noc"; "qcom,sm8150-system_noc"; - "qcom,sm8150-gem_noc_display"; - "qcom,sm8150-mc_virt_display"; - "qcom,sm8150-mmss_noc_display"; - #interconnect-cells : should contain 1 Examples: From 1f395205116d4872a4155aeca487a4c8ce211e07 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Mon, 13 Apr 2020 15:29:30 +0530 Subject: [PATCH 3/4] dt-bindings: ufs: Add compitable string for V4 UFS PHY on SM8150 This change adds the compatible string for the V4 UFS PHY present on SM8150 chipset. Change-Id: I767c6b12d6423ddb04c0769f801c8e95cc1072dd --- bindings/ufs/ufs-qcom.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/ufs/ufs-qcom.txt b/bindings/ufs/ufs-qcom.txt index c3db1a85b6e9..c4e221a8c05e 100644 --- a/bindings/ufs/ufs-qcom.txt +++ b/bindings/ufs/ufs-qcom.txt @@ -16,6 +16,8 @@ Required properties: for sdm845 emulation, "qcom,ufs-phy-qmp-v4-lahaina" for V4 ufs phy present on Lahaina chipset. + "qcom,ufs-phy-qmp-v4" for V4 ufs phy present + on SM8150 chipset. "qcom,ufs-phy-qmp-v3" for V3 ufs phy present on holi chipset. - reg : should contain PHY register address space (mandatory), From 1d31bf7079283291fa4a94caa865bd791d4f7b34 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Tue, 3 Nov 2020 11:50:51 +0530 Subject: [PATCH 4/4] dt-bindings: interconnect: add OSM L3 bindings Add bindings for the new interconnect OSM L3 driver. Change-Id: Ib240d9e8d900539fc6f8112c9fe55d530d51ae95 --- bindings/interconnect/qcom,osm-l3.txt | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 bindings/interconnect/qcom,osm-l3.txt diff --git a/bindings/interconnect/qcom,osm-l3.txt b/bindings/interconnect/qcom,osm-l3.txt new file mode 100644 index 000000000000..4d323fd7750b --- /dev/null +++ b/bindings/interconnect/qcom,osm-l3.txt @@ -0,0 +1,25 @@ +Qualcomm Technologies, Inc. EPSS L3 interconnect driver binding +----------------------------------------------------------- + +The EPSS L3 Interconnect provider supports the scaling of L3 cache +performance states of the CPU subsystem. + +Required properties : +- compatible : shall contain only one of the following: + "qcom,sdm845-osm-l3", + "qcom,sm8150-osm-l3"; +- reg : Address and length of the register set for the device +- clock-names: should contain "xo", "alternate" +- clocks: list of phandle and clock specifier pairs corresponding to + entries in the clock-names property. +- #interconnect-cells : should contain 1 + +Examples: + +osm_l3: interconnect@0x18321000 { + reg = <0x18321000 0x1400>; + compatible = "qcom,sm8150-osm-l3"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; +};