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Merge fdffed7083 on remote branch

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Change-Id: Idc36c3726c02d2c71d229d563955c25d4c1b3091
This commit is contained in:
Linux Build Service Account 2020-07-22 07:46:08 -07:00
commit 94fa530d56
17 changed files with 1162 additions and 183 deletions
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12
include/uapi/vidc/media/msm_vidc_utils.h
View file

@ -72,18 +72,6 @@ enum v4l2_mpeg_vidc_video_bitrate_mode {
V4L2_MPEG_VIDEO_BITRATE_MODE_MBR_VFR,
V4L2_MPEG_VIDEO_BITRATE_MODE_CQ,
};
enum v4l2_mpeg_vidc_video_h264_profile {
V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH =
V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH + 1,
};
enum v4l2_mpeg_vidc_video_h264_level {
V4L2_MPEG_VIDEO_H264_LEVEL_5_2 = V4L2_MPEG_VIDEO_H264_LEVEL_5_1 + 1,
V4L2_MPEG_VIDEO_H264_LEVEL_6_0,
V4L2_MPEG_VIDEO_H264_LEVEL_6_1,
V4L2_MPEG_VIDEO_H264_LEVEL_6_2,
};
/* missing v4l2 entries end */
/* vendor controls start */

2
msm/vidc/hfi_common.c
View file

@ -3107,7 +3107,7 @@ int __reset_ahb2axi_bridge_common(struct venus_hfi_device *device, u32 sid)
}
/* wait for deassert */
usleep_range(150, 250);
usleep_range(400, 500);
rc = __handle_reset_clk(device->res, i, DEASSERT, sid);
if (rc) {

27
msm/vidc/msm_v4l2_vidc.c
View file

@ -261,17 +261,28 @@ static int read_platform_resources(struct msm_vidc_core *core,
__func__, core, pdev);
return -EINVAL;
}
if (!pdev->dev.of_node) {
d_vpr_e("%s: pdev node is NULL\n", __func__);
return -EINVAL;
}
core->hfi_type = VIDC_HFI_VENUS;
core->resources.pdev = pdev;
if (pdev->dev.of_node) {
/* Target supports DT, parse from it */
rc = read_platform_resources_from_drv_data(core);
rc = read_platform_resources_from_dt(&core->resources);
} else {
d_vpr_e("pdev node is NULL\n");
rc = -EINVAL;
/* Target supports DT, parse from it */
rc = read_platform_resources_from_drv_data(core);
if (rc) {
d_vpr_e("%s: read platform resources from driver failed\n",
__func__);
return rc;
}
return rc;
rc = read_platform_resources_from_dt(&core->resources);
if (rc) {
d_vpr_e("%s: read platform resources from dt failed\n",
__func__);
return rc;
}
return 0;
}
static int msm_vidc_initialize_core(struct platform_device *pdev,

178
msm/vidc/msm_venc.c
View file

@ -601,10 +601,11 @@ static struct msm_vidc_ctrl msm_venc_ctrls[] = {
.id = V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_TYPE,
.name = "Set Hier coding type",
.type = V4L2_CTRL_TYPE_MENU,
.minimum = V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P,
.minimum = V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B,
.maximum = V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P,
.default_value = V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P,
.menu_skip_mask = ~(
(1 << V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B) |
(1 << V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P)
),
.qmenu = NULL,
@ -2451,8 +2452,19 @@ int msm_venc_set_intra_period(struct msm_vidc_inst *inst)
{
int rc = 0;
struct hfi_device *hdev;
struct v4l2_ctrl *ctrl;
struct hfi_intra_period intra_period;
struct v4l2_ctrl *gop_size = NULL;
struct v4l2_ctrl *bframes = NULL;
struct v4l2_ctrl *max_layer = NULL;
struct v4l2_ctrl *frame_t = NULL;
struct hfi_intra_period intra_period = {
.pframes = 0,
.bframes = 0
};
struct hfi_adaptive_p_b_intra_period adaptive_p_b_intra_period = {
.nframes = 0
};
u32 codec;
bool adaptive_bframes = false;
if (!inst || !inst->core) {
d_vpr_e("%s: invalid params %pK\n", __func__, inst);
@ -2460,38 +2472,78 @@ int msm_venc_set_intra_period(struct msm_vidc_inst *inst)
}
hdev = inst->core->device;
msm_venc_adjust_gop_size(inst);
frame_t = get_ctrl(inst, V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_TYPE);
gop_size = get_ctrl(inst, V4L2_CID_MPEG_VIDEO_GOP_SIZE);
max_layer = get_ctrl(inst,
V4L2_CID_MPEG_VIDC_VIDEO_HEVC_MAX_HIER_CODING_LAYER);
codec = get_v4l2_codec(inst);
ctrl = get_ctrl(inst, V4L2_CID_MPEG_VIDEO_GOP_SIZE);
intra_period.pframes = ctrl->val;
if (!max_layer->val && codec == V4L2_PIX_FMT_H264) {
intra_period.pframes = gop_size->val;
/*
* At this point we've already made decision on bframe.
* Control value gives updated bframe value.
*/
bframes = get_ctrl(inst, V4L2_CID_MPEG_VIDEO_B_FRAMES);
intra_period.bframes = bframes->val;
if (intra_period.bframes)
adaptive_bframes = true;
}
/*
* At this point we have already made decision on bframe
* Control value gives updated bframe value.
*/
ctrl = get_ctrl(inst, V4L2_CID_MPEG_VIDEO_B_FRAMES);
intra_period.bframes = ctrl->val;
if (max_layer->val > 1) {
if (frame_t->val ==
V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B) {
if (codec == V4L2_PIX_FMT_HEVC) {
adaptive_p_b_intra_period.nframes =
gop_size->val;
adaptive_bframes = true;
} else {
d_vpr_e("%s: Hier-B supported for HEVC only\n",
__func__);
return -EINVAL;
}
} else if (frame_t->val ==
V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P) {
msm_venc_adjust_gop_size(inst);
intra_period.pframes = gop_size->val;
intra_period.bframes = 0;
adaptive_bframes = false;
}
}
if (inst->state == MSM_VIDC_START_DONE &&
!intra_period.pframes && !intra_period.bframes) {
!intra_period.pframes && !intra_period.bframes) {
s_vpr_h(inst->sid,
"%s: Switch from IPPP to All Intra is not allowed\n",
__func__);
return rc;
}
s_vpr_h(inst->sid, "%s: %d %d\n", __func__, intra_period.pframes,
intra_period.bframes);
rc = call_hfi_op(hdev, session_set_property, inst->session,
HFI_PROPERTY_CONFIG_VENC_INTRA_PERIOD, &intra_period,
sizeof(intra_period));
if (frame_t->val ==
V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B &&
codec == V4L2_PIX_FMT_HEVC) {
s_vpr_h(inst->sid, "%s: nframes: %d\n",
__func__, adaptive_p_b_intra_period.nframes);
rc = call_hfi_op(hdev, session_set_property, inst->session,
HFI_PROPERTY_CONFIG_VENC_INTRA_PERIOD,
&adaptive_p_b_intra_period,
sizeof(adaptive_p_b_intra_period));
} else {
s_vpr_h(inst->sid, "%s: pframes: %d bframes: %d\n",
__func__, intra_period.pframes,
intra_period.bframes);
rc = call_hfi_op(hdev, session_set_property, inst->session,
HFI_PROPERTY_CONFIG_VENC_INTRA_PERIOD,
&intra_period, sizeof(intra_period));
}
if (rc) {
s_vpr_e(inst->sid, "%s: set property failed\n", __func__);
return rc;
}
if (intra_period.bframes) {
/* Enable adaptive bframes as nbframes!= 0 */
if (adaptive_bframes) {
rc = msm_venc_set_adaptive_bframes(inst);
if (rc) {
s_vpr_e(inst->sid, "%s: set property failed\n",
@ -2499,6 +2551,7 @@ int msm_venc_set_intra_period(struct msm_vidc_inst *inst)
return rc;
}
}
return rc;
}
@ -2764,14 +2817,14 @@ int msm_venc_set_layer_bitrate(struct msm_vidc_inst *inst)
if (!max_layer->val || !layer->val) {
s_vpr_h(inst->sid,
"%s: Hierp layer not set. Ignore layer bitrate\n",
"%s: Hier-P layer not set. Ignore layer bitrate\n",
__func__);
goto error;
}
if (max_layer->val < layer->val) {
s_vpr_h(inst->sid,
"%s: Hierp layer greater than max isn't allowed\n",
"%s: Hier-P layer greater than max isn't allowed\n",
__func__);
goto error;
}
@ -3611,7 +3664,7 @@ int msm_venc_set_base_layer_priority_id(struct msm_vidc_inst *inst)
max_layer = get_ctrl(inst,
V4L2_CID_MPEG_VIDC_VIDEO_HEVC_MAX_HIER_CODING_LAYER);
if (max_layer->val <= 0) {
s_vpr_h(inst->sid, "%s: Layer id can only be set with Hierp\n",
s_vpr_h(inst->sid, "%s: Layer id can only be set with Hier-P\n",
__func__);
return 0;
}
@ -3629,11 +3682,54 @@ int msm_venc_set_base_layer_priority_id(struct msm_vidc_inst *inst)
return rc;
}
int msm_venc_set_hb_max_layer(struct msm_vidc_inst *inst)
{
int rc = 0;
struct hfi_device *hdev;
struct v4l2_ctrl *frame_t = NULL;
struct v4l2_ctrl *max_layer = NULL;
u32 hb_layer = 0;
u32 codec;
if (!inst || !inst->core) {
d_vpr_e("%s: invalid params %pK\n", __func__, inst);
return -EINVAL;
}
hdev = inst->core->device;
codec = get_v4l2_codec(inst);
if (codec != V4L2_PIX_FMT_HEVC)
return 0;
max_layer = get_ctrl(inst,
V4L2_CID_MPEG_VIDC_VIDEO_HEVC_MAX_HIER_CODING_LAYER);
frame_t = get_ctrl(inst, V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_TYPE);
if (max_layer->val < 2 ||
frame_t->val != V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B) {
s_vpr_h(inst->sid,
"%s: Hier-B not requested for this session\n",
__func__);
return 0;
}
hb_layer = max_layer->val - 1;
s_vpr_h(inst->sid, "%s: Hier-B max layer: %d\n",
__func__, hb_layer);
rc = call_hfi_op(hdev, session_set_property, inst->session,
HFI_PROPERTY_PARAM_VENC_HIER_B_MAX_NUM_ENH_LAYER,
&hb_layer, sizeof(hb_layer));
if (rc)
s_vpr_e(inst->sid, "%s: set property failed\n", __func__);
return rc;
}
int msm_venc_set_hp_max_layer(struct msm_vidc_inst *inst)
{
int rc = 0;
struct hfi_device *hdev;
struct v4l2_ctrl *ctrl;
struct v4l2_ctrl *frame_t = NULL;
struct v4l2_ctrl *max_layer = NULL;
u32 hp_layer = 0;
u32 codec;
@ -3647,12 +3743,20 @@ int msm_venc_set_hp_max_layer(struct msm_vidc_inst *inst)
if (codec != V4L2_PIX_FMT_H264 && codec != V4L2_PIX_FMT_HEVC)
return 0;
ctrl = get_ctrl(inst,
max_layer = get_ctrl(inst,
V4L2_CID_MPEG_VIDC_VIDEO_HEVC_MAX_HIER_CODING_LAYER);
frame_t = get_ctrl(inst, V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_TYPE);
if (max_layer->val < 2 ||
frame_t->val != V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P) {
s_vpr_h(inst->sid,
"%s: Hier-P not requested for this session\n",
__func__);
return 0;
}
rc = msm_venc_enable_hybrid_hp(inst);
if (rc) {
s_vpr_e(inst->sid, "%s: get hybrid hp decision failed\n",
s_vpr_e(inst->sid, "%s: get hybrid hier-P decision failed\n",
__func__);
return rc;
}
@ -3661,17 +3765,17 @@ int msm_venc_set_hp_max_layer(struct msm_vidc_inst *inst)
* We send enhancement layer count to FW,
* hence, input 0/1 indicates absence of layer encoding.
*/
if (ctrl->val)
hp_layer = ctrl->val - 1;
if (max_layer->val)
hp_layer = max_layer->val - 1;
if (inst->hybrid_hp) {
s_vpr_h(inst->sid, "%s: Hybrid hierp layer: %d\n",
s_vpr_h(inst->sid, "%s: Hybrid hier-P layer: %d\n",
__func__, hp_layer);
rc = call_hfi_op(hdev, session_set_property, inst->session,
HFI_PROPERTY_PARAM_VENC_HIER_P_HYBRID_MODE,
&hp_layer, sizeof(hp_layer));
} else {
s_vpr_h(inst->sid, "%s: Hierp max layer: %d\n",
s_vpr_h(inst->sid, "%s: Hier-P max layer: %d\n",
__func__, hp_layer);
rc = call_hfi_op(hdev, session_set_property, inst->session,
HFI_PROPERTY_PARAM_VENC_HIER_P_MAX_NUM_ENH_LAYER,
@ -3686,6 +3790,7 @@ int msm_venc_set_hp_layer(struct msm_vidc_inst *inst)
{
int rc = 0;
struct hfi_device *hdev;
struct v4l2_ctrl *frame_t = NULL;
struct v4l2_ctrl *ctrl = NULL;
struct v4l2_ctrl *max_layer = NULL;
u32 hp_layer = 0;
@ -3697,6 +3802,14 @@ int msm_venc_set_hp_layer(struct msm_vidc_inst *inst)
}
hdev = inst->core->device;
frame_t = get_ctrl(inst, V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_TYPE);
if (frame_t->val != V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P) {
s_vpr_h(inst->sid,
"%s: Hier-P layer can be set for P type frame only\n",
__func__);
return 0;
}
codec = get_v4l2_codec(inst);
if (codec != V4L2_PIX_FMT_H264 && codec != V4L2_PIX_FMT_HEVC)
return 0;
@ -3728,7 +3841,7 @@ int msm_venc_set_hp_layer(struct msm_vidc_inst *inst)
if (ctrl->val)
hp_layer = ctrl->val - 1;
s_vpr_h(inst->sid, "%s: Hierp enhancement layer: %d\n",
s_vpr_h(inst->sid, "%s: Hier-P enhancement layer: %d\n",
__func__, hp_layer);
rc = call_hfi_op(hdev, session_set_property, inst->session,
HFI_PROPERTY_CONFIG_VENC_HIER_P_ENH_LAYER,
@ -4735,6 +4848,9 @@ int msm_venc_set_properties(struct msm_vidc_inst *inst)
if (rc)
goto exit;
rc = msm_venc_set_ltr_mode(inst);
if (rc)
goto exit;
rc = msm_venc_set_hb_max_layer(inst);
if (rc)
goto exit;
rc = msm_venc_set_hp_max_layer(inst);

1
msm/vidc/msm_venc.h
View file

@ -35,6 +35,7 @@ int msm_venc_set_ltr_markframe(struct msm_vidc_inst *inst);
int msm_venc_set_dyn_qp(struct msm_vidc_inst *inst, struct v4l2_ctrl *ctrl);
int msm_venc_set_request_keyframe(struct msm_vidc_inst *inst);
int msm_venc_set_intra_refresh_mode(struct msm_vidc_inst *inst);
int msm_venc_set_hb_max_layer(struct msm_vidc_inst *inst);
int msm_venc_set_hp_max_layer(struct msm_vidc_inst *inst);
int msm_venc_set_hp_layer(struct msm_vidc_inst *inst);
int msm_venc_set_base_layer_priority_id(struct msm_vidc_inst *inst);

40
msm/vidc/msm_vidc.c
View file

@ -380,13 +380,21 @@ int msm_vidc_qbuf(void *instance, struct media_device *mdev,
return -EINVAL;
}
q = msm_comm_get_vb2q(inst, b->type);
if (!q) {
s_vpr_e(inst->sid,
"Failed to find buffer queue. type %d\n", b->type);
return -EINVAL;
}
mutex_lock(&q->lock);
if ((inst->out_flush && b->type == OUTPUT_MPLANE) || inst->in_flush) {
s_vpr_e(inst->sid,
"%s: in flush, discarding qbuf, type %u, index %u\n",
__func__, b->type, b->index);
return -EINVAL;
rc = -EINVAL;
goto unlock;
}
inst->last_qbuf_time_ns = ktime_get_ns();
for (i = 0; i < b->length; i++) {
@ -409,15 +417,17 @@ int msm_vidc_qbuf(void *instance, struct media_device *mdev,
0, inst->sid);
if (rc) {
s_vpr_e(inst->sid, "Failed to store input tag");
return -EINVAL;
rc = -EINVAL;
goto unlock;
}
}
/*
* set perf mode for image session buffers so that
* they will be processed quickly
* set perf mode for image and thumbnail session buffers
* so that they will be processed quickly
*/
if (is_grid_session(inst) && b->type == INPUT_MPLANE)
if ((is_grid_session(inst) || is_thumbnail_session(inst))
&& b->type == INPUT_MPLANE)
b->flags |= V4L2_BUF_FLAG_PERF_MODE;
timestamp_us = (u64)((b->timestamp.tv_sec * 1000000ULL) +
@ -429,7 +439,7 @@ int msm_vidc_qbuf(void *instance, struct media_device *mdev,
rc = msm_comm_store_timestamp(inst, timestamp_us);
if (rc)
return rc;
goto unlock;
inst->clk_data.frame_rate = msm_comm_get_max_framerate(inst);
}
if (is_encode_session(inst) && b->type == INPUT_MPLANE) {
@ -439,21 +449,14 @@ int msm_vidc_qbuf(void *instance, struct media_device *mdev,
rc = msm_venc_store_timestamp(inst, timestamp_us);
if (rc)
return rc;
goto unlock;
}
q = msm_comm_get_vb2q(inst, b->type);
if (!q) {
s_vpr_e(inst->sid,
"Failed to find buffer queue. type %d\n", b->type);
return -EINVAL;
}
mutex_lock(&q->lock);
rc = vb2_qbuf(&q->vb2_bufq, mdev, b);
mutex_unlock(&q->lock);
if (rc)
s_vpr_e(inst->sid, "Failed to qbuf, %d\n", rc);
unlock:
mutex_unlock(&q->lock);
return rc;
}
@ -1484,7 +1487,6 @@ void *msm_vidc_open(int core_id, int session_type)
mutex_init(&inst->bufq[OUTPUT_PORT].lock);
mutex_init(&inst->bufq[INPUT_PORT].lock);
mutex_init(&inst->lock);
mutex_init(&inst->flush_lock);
mutex_init(&inst->ubwc_stats_lock);
INIT_MSM_VIDC_LIST(&inst->scratchbufs);
@ -1595,7 +1597,6 @@ fail_bufq_capture:
mutex_destroy(&inst->bufq[OUTPUT_PORT].lock);
mutex_destroy(&inst->bufq[INPUT_PORT].lock);
mutex_destroy(&inst->lock);
mutex_destroy(&inst->flush_lock);
DEINIT_MSM_VIDC_LIST(&inst->scratchbufs);
DEINIT_MSM_VIDC_LIST(&inst->persistbufs);
@ -1741,7 +1742,6 @@ int msm_vidc_destroy(struct msm_vidc_inst *inst)
mutex_destroy(&inst->bufq[OUTPUT_PORT].lock);
mutex_destroy(&inst->bufq[INPUT_PORT].lock);
mutex_destroy(&inst->lock);
mutex_destroy(&inst->flush_lock);
msm_vidc_debugfs_deinit_inst(inst);

105
msm/vidc/msm_vidc_buffer_calculations.c
View file

@ -142,7 +142,7 @@
#define LCU_MAX_SIZE_PELS 64
#define LCU_MIN_SIZE_PELS 16
#define H265D_MAX_SLICE 1200
#define H265D_MAX_SLICE 3600
#define SIZE_H265D_HW_PIC_T SIZE_H264D_HW_PIC_T
#define SIZE_H265D_BSE_CMD_PER_BUF (16 * sizeof(u32))
#define SIZE_H265D_VPP_CMD_PER_BUF 256
@ -269,13 +269,17 @@ static int msm_vidc_get_extra_input_buff_count(struct msm_vidc_inst *inst);
static int msm_vidc_get_extra_output_buff_count(struct msm_vidc_inst *inst);
static inline u32 calculate_h264d_scratch_size(struct msm_vidc_inst *inst,
u32 width, u32 height, bool is_interlaced, u32 delay);
u32 width, u32 height, bool is_interlaced, u32 delay,
u32 num_vpp_pipes);
static inline u32 calculate_h265d_scratch_size(struct msm_vidc_inst *inst,
u32 width, u32 height, bool is_interlaced, u32 delay);
u32 width, u32 height, bool is_interlaced, u32 delay,
u32 num_vpp_pipes);
static inline u32 calculate_vpxd_scratch_size(struct msm_vidc_inst *inst,
u32 width, u32 height, bool is_interlaced, u32 delay);
u32 width, u32 height, bool is_interlaced, u32 delay,
u32 num_vpp_pipes);
static inline u32 calculate_mpeg2d_scratch_size(struct msm_vidc_inst *inst,
u32 width, u32 height, bool is_interlaced, u32 delay);
u32 width, u32 height, bool is_interlaced, u32 delay,
u32 num_vpp_pipes);
static inline u32 calculate_enc_scratch_size(struct msm_vidc_inst *inst,
u32 width, u32 height, u32 work_mode, u32 lcu_size, u32 num_vpp_pipes);
@ -376,13 +380,15 @@ int msm_vidc_get_decoder_internal_buffer_sizes(struct msm_vidc_inst *inst)
struct msm_vidc_dec_buff_size_calculators *dec_calculators;
u32 width, height, i, out_min_count, num_vpp_pipes;
struct v4l2_format *f;
u32 vpp_delay = inst->bse_vpp_delay;
u32 vpp_delay;
if (!inst || !inst->core || !inst->core->platform_data) {
d_vpr_e("%s: Instance is null!", __func__);
return -EINVAL;
}
vpp_delay = inst->bse_vpp_delay;
num_vpp_pipes = inst->core->platform_data->num_vpp_pipes;
f = &inst->fmts[INPUT_PORT].v4l2_fmt;
switch (f->fmt.pix_mp.pixelformat) {
@ -423,7 +429,7 @@ int msm_vidc_get_decoder_internal_buffer_sizes(struct msm_vidc_inst *inst)
curr_req->buffer_size =
dec_calculators->calculate_scratch_size(
inst, width, height, is_interlaced,
vpp_delay);
vpp_delay, num_vpp_pipes);
valid_buffer_type = true;
} else if (curr_req->buffer_type ==
HAL_BUFFER_INTERNAL_SCRATCH_1) {
@ -459,10 +465,11 @@ int msm_vidc_get_decoder_internal_buffer_sizes(struct msm_vidc_inst *inst)
int msm_vidc_get_num_ref_frames(struct msm_vidc_inst *inst)
{
int num_ref = 1;
int num_bframes = -1, ltr_count = -1, num_hp_layers;
struct v4l2_ctrl *bframe_ctrl;
struct v4l2_ctrl *ltr_ctrl;
struct v4l2_ctrl *layer_ctrl;
int num_bframes = -1, ltr_count = -1;
struct v4l2_ctrl *bframe_ctrl = NULL;
struct v4l2_ctrl *ltr_ctrl = NULL;
struct v4l2_ctrl *frame_t = NULL;
struct v4l2_ctrl *max_layer = NULL;
u32 codec;
bframe_ctrl = get_ctrl(inst, V4L2_CID_MPEG_VIDEO_B_FRAMES);
@ -476,21 +483,27 @@ int msm_vidc_get_num_ref_frames(struct msm_vidc_inst *inst)
if (ltr_count > 0)
num_ref = num_ref + ltr_count;
layer_ctrl = get_ctrl(inst,
frame_t = get_ctrl(inst, V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_TYPE);
max_layer = get_ctrl(inst,
V4L2_CID_MPEG_VIDC_VIDEO_HEVC_MAX_HIER_CODING_LAYER);
num_hp_layers = layer_ctrl->val;
codec = get_v4l2_codec(inst);
if (num_hp_layers > 0) {
if (frame_t->val == V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P &&
max_layer->val > 0) {
codec = get_v4l2_codec(inst);
/* LTR and B - frame not supported with hybrid HP */
if (inst->hybrid_hp)
num_ref = (num_hp_layers - 1);
num_ref = (max_layer->val - 1);
else if (codec == V4L2_PIX_FMT_HEVC)
num_ref = ((num_hp_layers + 1) / 2) + ltr_count;
else if ((codec == V4L2_PIX_FMT_H264) && (num_hp_layers <= 4))
num_ref = ((1 << (num_hp_layers - 1)) - 1) + ltr_count;
num_ref = ((max_layer->val + 1) / 2) + ltr_count;
else if ((codec == V4L2_PIX_FMT_H264) && (max_layer->val <= 4))
num_ref = ((1 << (max_layer->val - 1)) - 1) + ltr_count;
else
num_ref = ((num_hp_layers + 1) / 2) + ltr_count;
num_ref = ((max_layer->val + 1) / 2) + ltr_count;
}
if (is_hier_b_session(inst)) {
num_ref = (1 << (max_layer->val - 1)) / 2 + 1;
}
return num_ref;
}
@ -620,6 +633,7 @@ int msm_vidc_calculate_input_buffer_count(struct msm_vidc_inst *inst)
{
struct msm_vidc_format *fmt;
int extra_buff_count = 0;
struct v4l2_ctrl *max_layer = NULL;
if (!inst) {
d_vpr_e("%s: invalid params\n", __func__);
@ -649,6 +663,13 @@ int msm_vidc_calculate_input_buffer_count(struct msm_vidc_inst *inst)
extra_buff_count = msm_vidc_get_extra_buff_count(inst,
HAL_BUFFER_INPUT);
fmt->count_min = MIN_INPUT_BUFFERS;
if (is_hier_b_session(inst)) {
max_layer = get_ctrl(inst,
V4L2_CID_MPEG_VIDC_VIDEO_HEVC_MAX_HIER_CODING_LAYER);
fmt->count_min = (1 << (max_layer->val - 1)) + 2;
}
fmt->count_min_host = fmt->count_actual =
fmt->count_min + extra_buff_count;
@ -1151,7 +1172,8 @@ static inline u32 hfi_iris2_h264d_non_comv_size(u32 width, u32 height,
return size;
}
static inline u32 size_h264d_hw_bin_buffer(u32 width, u32 height, u32 delay)
static inline u32 size_h264d_hw_bin_buffer(u32 width, u32 height, u32 delay,
u32 num_vpp_pipes)
{
u32 size_yuv, size_bin_hdr, size_bin_res;
u32 size = 0;
@ -1166,14 +1188,16 @@ static inline u32 size_h264d_hw_bin_buffer(u32 width, u32 height, u32 delay)
size_bin_res = size_yuv * H264_CABAC_RES_RATIO_HD_TOT;
size_bin_hdr = size_bin_hdr * (((((u32)(delay)) & 31) / 10) + 2) / 2;
size_bin_res = size_bin_res * (((((u32)(delay)) & 31) / 10) + 2) / 2;
size_bin_hdr = ALIGN(size_bin_hdr, VENUS_DMA_ALIGNMENT);
size_bin_res = ALIGN(size_bin_res, VENUS_DMA_ALIGNMENT);
size_bin_hdr = ALIGN(size_bin_hdr / num_vpp_pipes,
VENUS_DMA_ALIGNMENT) * num_vpp_pipes;
size_bin_res = ALIGN(size_bin_res / num_vpp_pipes,
VENUS_DMA_ALIGNMENT) * num_vpp_pipes;
size = size_bin_hdr + size_bin_res;
return size;
}
static inline u32 calculate_h264d_scratch_size(struct msm_vidc_inst *inst,
u32 width, u32 height, bool is_interlaced, u32 delay)
u32 width, u32 height, bool is_interlaced, u32 delay, u32 num_vpp_pipes)
{
u32 aligned_width = ALIGN(width, BUFFER_ALIGNMENT_SIZE(16));
u32 aligned_height = ALIGN(height, BUFFER_ALIGNMENT_SIZE(16));
@ -1181,7 +1205,7 @@ static inline u32 calculate_h264d_scratch_size(struct msm_vidc_inst *inst,
if (!is_interlaced)
size = size_h264d_hw_bin_buffer(aligned_width, aligned_height,
delay);
delay, num_vpp_pipes);
else
size = 0;
@ -1270,7 +1294,8 @@ static inline u32 hfi_iris2_h265d_non_comv_size(u32 width, u32 height,
return size;
}
static inline u32 size_h265d_hw_bin_buffer(u32 width, u32 height, u32 delay)
static inline u32 size_h265d_hw_bin_buffer(u32 width, u32 height, u32 delay,
u32 num_vpp_pipes)
{
u32 size = 0;
u32 size_yuv, size_bin_hdr, size_bin_res;
@ -1284,15 +1309,17 @@ static inline u32 size_h265d_hw_bin_buffer(u32 width, u32 height, u32 delay)
size_bin_res = size_yuv * H265_CABAC_RES_RATIO_HD_TOT;
size_bin_hdr = size_bin_hdr * (((((u32)(delay)) & 31) / 10) + 2) / 2;
size_bin_res = size_bin_res * (((((u32)(delay)) & 31) / 10) + 2) / 2;
size_bin_hdr = ALIGN(size_bin_hdr, VENUS_DMA_ALIGNMENT);
size_bin_res = ALIGN(size_bin_res, VENUS_DMA_ALIGNMENT);
size_bin_hdr = ALIGN(size_bin_hdr / num_vpp_pipes,
VENUS_DMA_ALIGNMENT) * num_vpp_pipes;
size_bin_res = ALIGN(size_bin_res / num_vpp_pipes,
VENUS_DMA_ALIGNMENT) * num_vpp_pipes;
size = size_bin_hdr + size_bin_res;
return size;
}
static inline u32 calculate_h265d_scratch_size(struct msm_vidc_inst *inst,
u32 width, u32 height, bool is_interlaced, u32 delay)
u32 width, u32 height, bool is_interlaced, u32 delay, u32 num_vpp_pipes)
{
u32 aligned_width = ALIGN(width, BUFFER_ALIGNMENT_SIZE(16));
u32 aligned_height = ALIGN(height, BUFFER_ALIGNMENT_SIZE(16));
@ -1300,7 +1327,7 @@ static inline u32 calculate_h265d_scratch_size(struct msm_vidc_inst *inst,
if (!is_interlaced)
size = size_h265d_hw_bin_buffer(aligned_width, aligned_height,
delay);
delay, num_vpp_pipes);
else
size = 0;
@ -1308,7 +1335,7 @@ static inline u32 calculate_h265d_scratch_size(struct msm_vidc_inst *inst,
}
static inline u32 calculate_vpxd_scratch_size(struct msm_vidc_inst *inst,
u32 width, u32 height, bool is_interlaced, u32 delay)
u32 width, u32 height, bool is_interlaced, u32 delay, u32 num_vpp_pipes)
{
u32 aligned_width = ALIGN(width, BUFFER_ALIGNMENT_SIZE(16));
u32 aligned_height = ALIGN(height, BUFFER_ALIGNMENT_SIZE(16));
@ -1317,20 +1344,22 @@ static inline u32 calculate_vpxd_scratch_size(struct msm_vidc_inst *inst,
if (!is_interlaced) {
/* binbuffer1_size + binbufer2_size */
u32 binbuffer1_size = 0, binbufer2_size = 0;
u32 binbuffer1_size = 0, binbuffer2_size = 0;
binbuffer1_size = max_t(u32, size_yuv,
binbuffer1_size = ALIGN(max_t(u32, size_yuv,
((BIN_BUFFER_THRESHOLD * 3) >> 1)) *
VPX_DECODER_FRAME_CONCURENCY_LVL *
VPX_DECODER_FRAME_BIN_HDR_BUDGET_RATIO_NUM /
VPX_DECODER_FRAME_BIN_HDR_BUDGET_RATIO_DEN;
binbufer2_size = max_t(u32, size_yuv,
VPX_DECODER_FRAME_BIN_HDR_BUDGET_RATIO_DEN,
VENUS_DMA_ALIGNMENT);
binbuffer2_size = ALIGN(max_t(u32, size_yuv,
((BIN_BUFFER_THRESHOLD * 3) >> 1)) *
VPX_DECODER_FRAME_CONCURENCY_LVL *
VPX_DECODER_FRAME_BIN_RES_BUDGET_RATIO_NUM /
VPX_DECODER_FRAME_BIN_RES_BUDGET_RATIO_DEN;
size = ALIGN(binbuffer1_size + binbufer2_size,
VPX_DECODER_FRAME_BIN_RES_BUDGET_RATIO_DEN,
VENUS_DMA_ALIGNMENT);
size = binbuffer1_size + binbuffer2_size;
size = size * num_vpp_pipes;
} else {
size = 0;
}
@ -1339,7 +1368,7 @@ static inline u32 calculate_vpxd_scratch_size(struct msm_vidc_inst *inst,
}
static inline u32 calculate_mpeg2d_scratch_size(struct msm_vidc_inst *inst,
u32 width, u32 height, bool is_interlaced, u32 delay)
u32 width, u32 height, bool is_interlaced, u32 delay, u32 num_vpp_pipes)
{
return 0;
}

2
msm/vidc/msm_vidc_buffer_calculations.h
View file

@ -12,7 +12,7 @@
struct msm_vidc_dec_buff_size_calculators {
u32 (*calculate_scratch_size)(struct msm_vidc_inst *inst, u32 width,
u32 height, bool is_interlaced, u32 delay);
u32 height, bool is_interlaced, u32 delay, u32 num_vpp_pipes);
u32 (*calculate_scratch1_size)(struct msm_vidc_inst *inst, u32 width,
u32 height, u32 min_buf_count, bool split_mode_enabled,
u32 num_vpp_pipes);

7
msm/vidc/msm_vidc_clocks.c
View file

@ -1118,7 +1118,8 @@ int msm_vidc_decide_work_route_iris2(struct msm_vidc_inst *inst)
u32 codec;
uint32_t vpu;
if (!inst || !inst->core || !inst->core->device) {
if (!inst || !inst->core || !inst->core->device ||
!inst->core->platform_data) {
d_vpr_e("%s: Invalid args: Inst = %pK\n",
__func__, inst);
return -EINVAL;
@ -1127,7 +1128,7 @@ int msm_vidc_decide_work_route_iris2(struct msm_vidc_inst *inst)
vpu = inst->core->platform_data->vpu_ver;
hdev = inst->core->device;
is_legacy_cbr = inst->clk_data.is_legacy_cbr;
pdata.video_work_route = 4;
pdata.video_work_route = inst->core->platform_data->num_vpp_pipes;
if (vpu == VPU_VERSION_IRIS2_1) {
pdata.video_work_route = 1;
@ -1318,7 +1319,7 @@ int msm_vidc_decide_work_mode_iris2(struct msm_vidc_inst *inst)
if (inst->session_type == MSM_VIDC_DECODER) {
height = out_f->fmt.pix_mp.height;
width = out_f->fmt.pix_mp.width;
res_ok = res_is_less_than(width, height, 1280, 720);
res_ok = res_is_less_than_or_equal_to(width, height, 1280, 720);
if (inp_f->fmt.pix_mp.pixelformat == V4L2_PIX_FMT_MPEG2 ||
inst->pic_struct != MSM_VIDC_PIC_STRUCT_PROGRESSIVE ||
inst->clk_data.low_latency_mode || res_ok) {

62
msm/vidc/msm_vidc_common.c
View file

@ -735,15 +735,20 @@ int msm_comm_get_inst_load(struct msm_vidc_inst *inst,
* | Power Request Load = |
* | res * max(op, fps)|
* ----------------|----------------------------|
* NON-REALTIME/ | Admission Control Load = 0 |
* THUMBNAIL | Power Request Load = |
* NON-REALTIME | Admission Control Load = 0 |
* | Power Request Load = |
* | res * max(op, fps)|
* ----------------|----------------------------|
* THUMBNAIL | Always Load = 0 |
* | Perf mode added for |
* | thumbnail session buffers |
* | for faster decoding. |
* ----------------|----------------------------|
*/
if ((is_thumbnail_session(inst) ||
!is_realtime_session(inst)) &&
quirks == LOAD_ADMISSION_CONTROL) {
if (is_thumbnail_session(inst) ||
(!is_realtime_session(inst) &&
quirks == LOAD_ADMISSION_CONTROL)) {
load = 0;
} else {
load = msm_comm_get_mbs_per_sec(inst, quirks);
@ -2023,7 +2028,10 @@ static void handle_session_flush(enum hal_command_response cmd, void *data)
return;
}
mutex_lock(&inst->flush_lock);
if (response->data.flush_type & HAL_FLUSH_INPUT)
mutex_lock(&inst->bufq[INPUT_PORT].lock);
if (response->data.flush_type & HAL_FLUSH_OUTPUT)
mutex_lock(&inst->bufq[OUTPUT_PORT].lock);
if (msm_comm_get_stream_output_mode(inst) ==
HAL_VIDEO_DECODER_SECONDARY) {
@ -2073,7 +2081,10 @@ static void handle_session_flush(enum hal_command_response cmd, void *data)
v4l2_event_queue_fh(&inst->event_handler, &flush_event);
exit:
mutex_unlock(&inst->flush_lock);
if (response->data.flush_type & HAL_FLUSH_OUTPUT)
mutex_unlock(&inst->bufq[OUTPUT_PORT].lock);
if (response->data.flush_type & HAL_FLUSH_INPUT)
mutex_unlock(&inst->bufq[INPUT_PORT].lock);
s_vpr_l(inst->sid, "handled: SESSION_FLUSH_DONE\n");
put_inst(inst);
}
@ -2285,7 +2296,7 @@ struct vb2_buffer *msm_comm_get_vb_using_vidc_buffer(
return NULL;
}
mutex_lock(&inst->bufq[port].lock);
WARN_ON(!mutex_is_locked(&inst->bufq[port].lock));
found = false;
q = &inst->bufq[port].vb2_bufq;
if (!q->streaming) {
@ -2301,7 +2312,6 @@ struct vb2_buffer *msm_comm_get_vb_using_vidc_buffer(
}
}
unlock:
mutex_unlock(&inst->bufq[port].lock);
if (!found) {
print_vidc_buffer(VIDC_ERR, "vb2 not found for", inst, mbuf);
return NULL;
@ -2316,6 +2326,7 @@ int msm_comm_vb2_buffer_done(struct msm_vidc_inst *inst,
struct vb2_buffer *vb2;
struct vb2_v4l2_buffer *vbuf;
u32 i, port;
int rc = 0;
if (!inst || !mbuf) {
d_vpr_e("%s: invalid params %pK %pK\n",
@ -2330,16 +2341,19 @@ int msm_comm_vb2_buffer_done(struct msm_vidc_inst *inst,
else
return -EINVAL;
vb2 = msm_comm_get_vb_using_vidc_buffer(inst, mbuf);
if (!vb2)
return -EINVAL;
/*
* access vb2 buffer under q->lock and if streaming only to
* ensure the buffer was not free'd by vb2 framework while
* we are accessing it here.
*/
mutex_lock(&inst->bufq[port].lock);
vb2 = msm_comm_get_vb_using_vidc_buffer(inst, mbuf);
if (!vb2) {
s_vpr_e(inst->sid, "%s: port %d buffer not found\n",
__func__, port);
rc = -EINVAL;
goto unlock;
}
if (inst->bufq[port].vb2_bufq.streaming) {
vbuf = to_vb2_v4l2_buffer(vb2);
vbuf->flags = mbuf->vvb.flags;
@ -2355,9 +2369,10 @@ int msm_comm_vb2_buffer_done(struct msm_vidc_inst *inst,
s_vpr_e(inst->sid, "%s: port %d is not streaming\n",
__func__, port);
}
unlock:
mutex_unlock(&inst->bufq[port].lock);
return 0;
return rc;
}
static bool is_eos_buffer(struct msm_vidc_inst *inst, u32 device_addr)
@ -5511,7 +5526,6 @@ int msm_comm_flush(struct msm_vidc_inst *inst, u32 flags)
ip_flush = !!(flags & V4L2_CMD_FLUSH_OUTPUT);
op_flush = !!(flags & V4L2_CMD_FLUSH_CAPTURE);
if (ip_flush && !op_flush) {
s_vpr_e(inst->sid,
"Input only flush not supported, making it flush all\n");
@ -5534,7 +5548,10 @@ int msm_comm_flush(struct msm_vidc_inst *inst, u32 flags)
goto exit;
}
mutex_lock(&inst->flush_lock);
if (ip_flush)
mutex_lock(&inst->bufq[INPUT_PORT].lock);
if (op_flush)
mutex_lock(&inst->bufq[OUTPUT_PORT].lock);
/* enable in flush */
inst->in_flush = ip_flush;
inst->out_flush = op_flush;
@ -5590,7 +5607,10 @@ int msm_comm_flush(struct msm_vidc_inst *inst, u32 flags)
rc = call_hfi_op(hdev, session_flush, inst->session,
HAL_FLUSH_OUTPUT);
}
mutex_unlock(&inst->flush_lock);
if (op_flush)
mutex_unlock(&inst->bufq[OUTPUT_PORT].lock);
if (ip_flush)
mutex_unlock(&inst->bufq[INPUT_PORT].lock);
if (rc) {
s_vpr_e(inst->sid,
"Sending flush to firmware failed, flush out all buffers\n");
@ -6656,7 +6676,6 @@ int msm_comm_flush_vidc_buffer(struct msm_vidc_inst *inst,
else
return -EINVAL;
mutex_lock(&inst->bufq[port].lock);
if (inst->bufq[port].vb2_bufq.streaming) {
vb->planes[0].bytesused = 0;
vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
@ -6664,7 +6683,6 @@ int msm_comm_flush_vidc_buffer(struct msm_vidc_inst *inst,
s_vpr_e(inst->sid, "%s: port %d is not streaming\n",
__func__, port);
}
mutex_unlock(&inst->bufq[port].lock);
return 0;
}
@ -7010,7 +7028,7 @@ void handle_release_buffer_reference(struct msm_vidc_inst *inst,
unsigned int i = 0;
u32 planes[VIDEO_MAX_PLANES] = {0};
mutex_lock(&inst->flush_lock);
mutex_lock(&inst->bufq[OUTPUT_PORT].lock);
mutex_lock(&inst->registeredbufs.lock);
found = false;
/* check if mbuf was not removed by any chance */
@ -7099,7 +7117,7 @@ unlock:
print_vidc_buffer(VIDC_ERR,
"rbr qbuf failed", inst, mbuf);
}
mutex_unlock(&inst->flush_lock);
mutex_unlock(&inst->bufq[OUTPUT_PORT].lock);
}
int msm_comm_unmap_vidc_buffer(struct msm_vidc_inst *inst,
@ -7746,7 +7764,7 @@ int msm_comm_fetch_ts_framerate(struct msm_vidc_inst *inst,
}
/* do not update is_valid flag for subframe buffer */
if (!(b->flags & HAL_BUFFERFLAG_ENDOFSUBFRAME))
if (!(b->flags & V4L2_BUF_FLAG_END_OF_SUBFRAME))
node->is_valid = false;
b->timestamp.tv_sec = node->timestamp_us / 1000000ull;

19
msm/vidc/msm_vidc_common.h
View file

@ -190,6 +190,25 @@ static inline bool is_internal_buffer(enum hal_buffer type)
return !!(buf_type & type);
}
static inline bool is_hier_b_session(struct msm_vidc_inst *inst)
{
struct v4l2_ctrl *max_layer = NULL;
struct v4l2_ctrl *frame_t = NULL;
if (inst->session_type == MSM_VIDC_ENCODER) {
max_layer = get_ctrl(inst,
V4L2_CID_MPEG_VIDC_VIDEO_HEVC_MAX_HIER_CODING_LAYER);
frame_t = get_ctrl(inst,
V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_TYPE);
if (get_v4l2_codec(inst) == V4L2_PIX_FMT_HEVC &&
max_layer->val > 1 &&
frame_t->val ==
V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B)
return true;
}
return false;
}
static inline int msm_comm_g_ctrl(struct msm_vidc_inst *inst,
struct v4l2_control *ctrl)
{

4
msm/vidc/msm_vidc_debug.h
View file

@ -228,7 +228,7 @@ static inline char *get_debug_level_str(int level)
static inline void tic(struct msm_vidc_inst *i, enum profiling_points p,
char *b)
{
struct timeval __ddl_tv;
struct timeval __ddl_tv = { 0 };
if (!i->debug.pdata[p].name[0])
memcpy(i->debug.pdata[p].name, b, 64);
@ -243,7 +243,7 @@ static inline void tic(struct msm_vidc_inst *i, enum profiling_points p,
static inline void toc(struct msm_vidc_inst *i, enum profiling_points p)
{
struct timeval __ddl_tv;
struct timeval __ddl_tv = { 0 };
if ((msm_vidc_debug & VIDC_PERF) &&
!i->debug.pdata[p].sampling) {

4
msm/vidc/msm_vidc_internal.h
View file

@ -289,6 +289,8 @@ struct msm_vidc_platform_data {
unsigned int common_data_length;
struct msm_vidc_codec_data *codec_data;
unsigned int codec_data_length;
struct allowed_clock_rates_table *clock_data;
unsigned int clock_data_length;
struct msm_vidc_codec *codecs;
uint32_t codecs_count;
struct msm_vidc_codec_capability *codec_caps;
@ -494,7 +496,7 @@ struct msm_vidc_inst_smem_ops {
struct msm_vidc_inst {
struct list_head list;
struct mutex sync_lock, lock, flush_lock;
struct mutex sync_lock, lock;
struct msm_vidc_core *core;
enum session_type session_type;
void *session;

823
msm/vidc/msm_vidc_platform.c
View file

@ -71,6 +71,15 @@ static struct msm_vidc_codec_data bengal_codec_data[] = {
CODEC_ENTRY(V4L2_PIX_FMT_VP9, MSM_VIDC_DECODER, 0, 440, 440),
};
static struct msm_vidc_codec_data shima_codec_data[] = {
CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_ENCODER, 0, 675, 320),
CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_ENCODER, 0, 675, 320),
CODEC_ENTRY(V4L2_PIX_FMT_MPEG2, MSM_VIDC_DECODER, 0, 200, 200),
CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_DECODER, 0, 200, 200),
CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_DECODER, 0, 200, 200),
CODEC_ENTRY(V4L2_PIX_FMT_VP9, MSM_VIDC_DECODER, 0, 200, 200),
};
static struct msm_vidc_codec_data holi_codec_data[] = {
CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_ENCODER, 0, 675, 320),
CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_ENCODER, 0, 675, 320),
@ -95,6 +104,12 @@ static struct msm_vidc_codec bengal_codecs[] = {
{ENC, H264}, {ENC, HEVC},
};
static struct msm_vidc_codec shima_codecs[] = {
/* {domain, codec} */
{DEC, H264}, {DEC, HEVC}, {DEC, VP9}, {DEC, MPEG2},
{ENC, H264}, {ENC, HEVC},
};
static struct msm_vidc_codec holi_codecs[] = {
/* {domain, codec} */
{DEC, H264}, {DEC, HEVC}, {DEC, VP9},
@ -229,12 +244,16 @@ static struct msm_vidc_codec_capability bengal_capabilities_v1[] = {
static struct msm_vidc_codec_capability holi_capabilities[] = {
/* {cap_type, domains, codecs, min, max, step_size, default_value} */
{CAP_FRAME_WIDTH, DOMAINS_ALL, CODECS_ALL, 128, 1920, 1, 1920},
{CAP_FRAME_HEIGHT, DOMAINS_ALL, CODECS_ALL, 128, 1920, 1, 1080},
{CAP_FRAME_WIDTH, DEC, CODECS_ALL, 96, 1920, 1, 1920},
{CAP_FRAME_HEIGHT, DEC, CODECS_ALL, 96, 1920, 1, 1080},
{CAP_FRAME_WIDTH, ENC, CODECS_ALL, 128, 1920, 1, 1920},
{CAP_FRAME_HEIGHT, ENC, CODECS_ALL, 128, 1920, 1, 1080},
/* ((1920 * 1088) / 256) */
{CAP_MBS_PER_FRAME, DOMAINS_ALL, CODECS_ALL, 64, 8160, 1, 8160},
{CAP_MBS_PER_FRAME, DEC, CODECS_ALL, 36, 8160, 1, 8160},
{CAP_MBS_PER_FRAME, ENC, CODECS_ALL, 64, 8160, 1, 8160},
/* 1080@30 decode + 1080@30 encode */
{CAP_MBS_PER_SECOND, DOMAINS_ALL, CODECS_ALL, 64, 489600, 1, 244800},
{CAP_MBS_PER_SECOND, DEC, CODECS_ALL, 36, 489600, 1, 244800},
{CAP_MBS_PER_SECOND, ENC, CODECS_ALL, 64, 489600, 1, 244800},
{CAP_FRAMERATE, DOMAINS_ALL, CODECS_ALL, 1, 120, 1, 30},
{CAP_BITRATE, DOMAINS_ALL, CODECS_ALL, 1, 60000000, 1, 20000000},
{CAP_CABAC_BITRATE, ENC, H264, 1, 60000000, 1, 20000000},
@ -253,8 +272,10 @@ static struct msm_vidc_codec_capability holi_capabilities[] = {
{CAP_MAX_VIDEOCORES, DOMAINS_ALL, CODECS_ALL, 0, 1, 1, 1},
/* Secure usecase specific */
{CAP_SECURE_FRAME_WIDTH, DOMAINS_ALL, CODECS_ALL, 128, 1920, 1, 1920},
{CAP_SECURE_FRAME_HEIGHT, DOMAINS_ALL, CODECS_ALL, 128, 1920, 1, 1080},
{CAP_SECURE_FRAME_WIDTH, DEC, CODECS_ALL, 96, 1920, 1, 1920},
{CAP_SECURE_FRAME_HEIGHT, DEC, CODECS_ALL, 96, 1920, 1, 1080},
{CAP_SECURE_FRAME_WIDTH, ENC, CODECS_ALL, 128, 1920, 1, 1920},
{CAP_SECURE_FRAME_HEIGHT, ENC, CODECS_ALL, 128, 1920, 1, 1080},
/* (1920 * 1088) / 256 */
{CAP_SECURE_MBS_PER_FRAME, DOMAINS_ALL, CODECS_ALL, 64, 8160, 1, 8160},
{CAP_SECURE_BITRATE, DOMAINS_ALL, CODECS_ALL, 1, 35000000, 1, 20000000},
@ -390,6 +411,301 @@ static struct msm_vidc_codec_capability lahaina_capabilities[] = {
V4L2_MPEG_VIDEO_HEVC_LEVEL_5},
};
static struct msm_vidc_codec_capability shima_capabilities_v0[] = {
/* {cap_type, domains, codecs, min, max, step_size, default_value,} */
{CAP_FRAME_WIDTH, DEC, CODECS_ALL, 96, 8192, 1, 1920},
{CAP_FRAME_HEIGHT, DEC, CODECS_ALL, 96, 8192, 1, 1080},
{CAP_FRAME_WIDTH, ENC, CODECS_ALL, 128, 8192, 1, 1920},
{CAP_FRAME_HEIGHT, ENC, CODECS_ALL, 128, 8192, 1, 1080},
/* (8192 * 4320) / 256 */
{CAP_MBS_PER_FRAME, DEC, CODECS_ALL, 36, 138240, 1, 138240},
{CAP_MBS_PER_FRAME, ENC, CODECS_ALL, 64, 138240, 1, 138240},
{CAP_FRAMERATE, DOMAINS_ALL, CODECS_ALL, 1, 480, 1, 30},
/* Encode spec - 4K@60 */
/* ((3840 * 2176) / 256) * 60 fps */
{CAP_MBS_PER_SECOND, ENC, CODECS_ALL, 64, 1958400, 1, 489600},
/* Decode spec - 8K@30, 4k@120*/
/* ((8192 * 4320) / 256) * 30 fps */
{CAP_MBS_PER_SECOND, DEC, CODECS_ALL, 36, 4147200, 1, 979200},
{CAP_BITRATE, DOMAINS_ALL, CODECS_ALL, 1, 160000000, 1, 20000000},
{CAP_CABAC_BITRATE, ENC, H264, 1, 160000000, 1, 20000000},
{CAP_SCALE_X, ENC, CODECS_ALL, 8192, 65536, 1, 8192},
{CAP_SCALE_Y, ENC, CODECS_ALL, 8192, 65536, 1, 8192},
{CAP_SCALE_X, DEC, CODECS_ALL, 65536, 65536, 1, 65536},
{CAP_SCALE_Y, DEC, CODECS_ALL, 65536, 65536, 1, 65536},
{CAP_BFRAME, ENC, H264|HEVC, 0, 1, 1, 0},
{CAP_HIER_P_NUM_ENH_LAYERS, ENC, H264|HEVC, 0, 6, 1, 0},
{CAP_LTR_COUNT, ENC, H264|HEVC, 0, 4, 1, 0},
/* ((1920 * 1088) / 256) * 60 fps */
{CAP_MBS_PER_SECOND_POWER_SAVE, ENC, CODECS_ALL,
0, 489600, 1, 489600},
{CAP_I_FRAME_QP, ENC, H264|HEVC, 0, 51, 1, 10},
{CAP_P_FRAME_QP, ENC, H264|HEVC, 0, 51, 1, 20},
{CAP_B_FRAME_QP, ENC, H264|HEVC, 0, 51, 1, 20},
/* 10 slices */
{CAP_SLICE_BYTE, ENC, H264|HEVC, 1, 10, 1, 10},
{CAP_SLICE_MB, ENC, H264|HEVC, 1, 10, 1, 10},
{CAP_MAX_VIDEOCORES, DOMAINS_ALL, CODECS_ALL, 0, 1, 1, 1},
/* Mpeg2 decoder specific */
{CAP_FRAME_WIDTH, DEC, MPEG2, 96, 1920, 1, 1920},
{CAP_FRAME_HEIGHT, DEC, MPEG2, 96, 1920, 1, 1080},
/* (1920 * 1088) / 256 */
{CAP_MBS_PER_FRAME, DEC, MPEG2, 36, 8160, 1, 8160},
/* ((1920 * 1088) / 256) * 30*/
{CAP_MBS_PER_SECOND, DEC, MPEG2, 36, 244800, 1, 244800},
{CAP_FRAMERATE, DEC, MPEG2, 1, 30, 1, 30},
{CAP_BITRATE, DEC, MPEG2, 1, 40000000, 1, 20000000},
/* Secure usecase specific */
{CAP_SECURE_FRAME_WIDTH, DEC, CODECS_ALL, 96, 4096, 1, 1920},
{CAP_SECURE_FRAME_HEIGHT, DEC, CODECS_ALL, 96, 4096, 1, 1080},
{CAP_SECURE_FRAME_WIDTH, ENC, CODECS_ALL, 128, 4096, 1, 1920},
{CAP_SECURE_FRAME_HEIGHT, ENC, CODECS_ALL, 128, 4096, 1, 1080},
/* (3840 * 2176) / 256 */
{CAP_SECURE_MBS_PER_FRAME, DEC, CODECS_ALL, 36, 34816, 1, 8160},
{CAP_SECURE_MBS_PER_FRAME, ENC, CODECS_ALL, 64, 34816, 1, 8160},
{CAP_SECURE_BITRATE, DOMAINS_ALL, CODECS_ALL, 1, 40000000, 1, 20000000},
/* Batch Mode Decode */
{CAP_BATCH_MAX_MB_PER_FRAME, DEC, CODECS_ALL, 36, 8160, 1, 8160},
/* (1920 * 1088) / 256 */
{CAP_BATCH_MAX_FPS, DEC, CODECS_ALL, 1, 60, 1, 60},
/* Lossless encoding usecase specific */
{CAP_LOSSLESS_FRAME_WIDTH, ENC, H264|HEVC, 128, 4096, 1, 1920},
{CAP_LOSSLESS_FRAME_HEIGHT, ENC, H264|HEVC, 128, 4096, 1, 1080},
/* (4096 * 2176) / 256 */
{CAP_LOSSLESS_MBS_PER_FRAME, ENC, H264|HEVC, 64, 34816, 1, 8160},
/* All intra encoding usecase specific */
{CAP_ALLINTRA_MAX_FPS, ENC, H264|HEVC, 1, 120, 1, 30},
/* Image specific */
{CAP_HEVC_IMAGE_FRAME_WIDTH, ENC, HEVC, 128, 512, 1, 512},
{CAP_HEVC_IMAGE_FRAME_HEIGHT, ENC, HEVC, 128, 512, 1, 512},
{CAP_HEIC_IMAGE_FRAME_WIDTH, ENC, HEVC, 512, 16384, 1, 16384},
{CAP_HEIC_IMAGE_FRAME_HEIGHT, ENC, HEVC, 512, 16384, 1, 16384},
/*
* Level for AVC and HEVC encoder specific.
* Default for levels is UNKNOWN value. But if we use unknown
* value here to set as default, max value needs to be set to
* unknown as well, which creates a problem of allowing client
* to set higher level than supported.
*/
{CAP_H264_LEVEL, ENC, H264, V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
V4L2_MPEG_VIDEO_H264_LEVEL_5_1, 1,
V4L2_MPEG_VIDEO_H264_LEVEL_4_0},
{CAP_HEVC_LEVEL, ENC, HEVC, V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
V4L2_MPEG_VIDEO_HEVC_LEVEL_5, 1,
V4L2_MPEG_VIDEO_HEVC_LEVEL_4},
/* Level for AVC and HEVC decoder specific */
{CAP_H264_LEVEL, DEC, H264, V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
V4L2_MPEG_VIDEO_H264_LEVEL_5_2, 1,
V4L2_MPEG_VIDEO_H264_LEVEL_4_0},
{CAP_HEVC_LEVEL, DEC, HEVC, V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, 1,
V4L2_MPEG_VIDEO_HEVC_LEVEL_4},
};
static struct msm_vidc_codec_capability shima_capabilities_v1[] = {
/* {cap_type, domains, codecs, min, max, step_size, default_value,} */
{CAP_FRAME_WIDTH, DEC, CODECS_ALL, 96, 4096, 1, 1920},
{CAP_FRAME_HEIGHT, DEC, CODECS_ALL, 96, 4096, 1, 1080},
{CAP_FRAME_WIDTH, ENC, CODECS_ALL, 128, 4096, 1, 1920},
{CAP_FRAME_HEIGHT, ENC, CODECS_ALL, 128, 4096, 1, 1080},
/* ((4096 * 2176) / 256) */
{CAP_MBS_PER_FRAME, DEC, CODECS_ALL, 36, 34816, 1, 8160},
{CAP_MBS_PER_FRAME, ENC, CODECS_ALL, 64, 34816, 1, 8160},
/* ((3840 * 2176) / 256) * 60 fps */
{CAP_MBS_PER_SECOND, DEC, CODECS_ALL, 36, 1958400, 1, 489600},
{CAP_MBS_PER_SECOND, ENC, CODECS_ALL, 64, 1958400, 1, 489600},
{CAP_FRAMERATE, DOMAINS_ALL, CODECS_ALL, 1, 480, 1, 30},
{CAP_BITRATE, DOMAINS_ALL, CODECS_ALL, 1, 100000000, 1, 20000000},
{CAP_CABAC_BITRATE, ENC, H264, 1, 100000000, 1, 20000000},
{CAP_SCALE_X, ENC, CODECS_ALL, 8192, 65536, 1, 8192},
{CAP_SCALE_Y, ENC, CODECS_ALL, 8192, 65536, 1, 8192},
{CAP_SCALE_X, DEC, CODECS_ALL, 65536, 65536, 1, 65536},
{CAP_SCALE_Y, DEC, CODECS_ALL, 65536, 65536, 1, 65536},
{CAP_BFRAME, ENC, H264|HEVC, 0, 1, 1, 0},
{CAP_HIER_P_NUM_ENH_LAYERS, ENC, H264|HEVC, 0, 6, 1, 0},
{CAP_LTR_COUNT, ENC, H264|HEVC, 0, 4, 1, 0},
/* ((1920 * 1088) / 256) * 30 fps */
{CAP_MBS_PER_SECOND_POWER_SAVE, ENC, CODECS_ALL,
0, 244800, 1, 244800},
{CAP_I_FRAME_QP, ENC, H264|HEVC, 0, 51, 1, 10},
{CAP_P_FRAME_QP, ENC, H264|HEVC, 0, 51, 1, 20},
{CAP_B_FRAME_QP, ENC, H264|HEVC, 0, 51, 1, 20},
/* 10 slices */
{CAP_SLICE_BYTE, ENC, H264|HEVC, 1, 10, 1, 10},
{CAP_SLICE_MB, ENC, H264|HEVC, 1, 10, 1, 10},
{CAP_MAX_VIDEOCORES, DOMAINS_ALL, CODECS_ALL, 0, 1, 1, 1},
/* Mpeg2 decoder specific */
{CAP_FRAME_WIDTH, DEC, MPEG2, 96, 1920, 1, 1920},
{CAP_FRAME_HEIGHT, DEC, MPEG2, 96, 1920, 1, 1080},
/* (1920 * 1088) / 256 */
{CAP_MBS_PER_FRAME, DEC, MPEG2, 36, 8160, 1, 8160},
/* ((1920 * 1088) / 256) * 30 */
{CAP_MBS_PER_SECOND, DEC, MPEG2, 36, 244800, 1, 244800},
{CAP_FRAMERATE, DEC, MPEG2, 1, 30, 1, 30},
{CAP_BITRATE, DEC, MPEG2, 1, 40000000, 1, 20000000},
/* Secure usecase specific */
{CAP_SECURE_FRAME_WIDTH, DEC, CODECS_ALL, 96, 4096, 1, 1920},
{CAP_SECURE_FRAME_HEIGHT, DEC, CODECS_ALL, 96, 4096, 1, 1080},
{CAP_SECURE_FRAME_WIDTH, DOMAINS_ALL, CODECS_ALL, 128, 4096, 1, 1920},
{CAP_SECURE_FRAME_HEIGHT, DOMAINS_ALL, CODECS_ALL, 128, 4096, 1, 1080},
/* (4096 * 2176) / 256 */
{CAP_SECURE_MBS_PER_FRAME, DEC, CODECS_ALL, 36, 34816, 1, 8160},
{CAP_SECURE_MBS_PER_FRAME, ENC, CODECS_ALL, 64, 34816, 1, 8160},
{CAP_SECURE_BITRATE, DOMAINS_ALL, CODECS_ALL, 1, 40000000, 1, 20000000},
/* Batch Mode Decode */
{CAP_BATCH_MAX_MB_PER_FRAME, DEC, CODECS_ALL, 36, 8160, 1, 8160},
/* (1920 * 1088) / 256 */
{CAP_BATCH_MAX_FPS, DEC, CODECS_ALL, 1, 30, 1, 30},
/* Lossless encoding usecase specific */
{CAP_LOSSLESS_FRAME_WIDTH, ENC, H264|HEVC, 128, 3840, 1, 1920},
{CAP_LOSSLESS_FRAME_HEIGHT, ENC, H264|HEVC, 128, 3840, 1, 1080},
/* (3840 * 2176) / 256 */
{CAP_LOSSLESS_MBS_PER_FRAME, ENC, H264|HEVC, 64, 32640, 1, 8160},
/* All intra encoding usecase specific */
{CAP_ALLINTRA_MAX_FPS, ENC, H264|HEVC, 1, 120, 1, 30},
/* Image specific */
{CAP_HEVC_IMAGE_FRAME_WIDTH, ENC, HEVC, 128, 512, 1, 512},
{CAP_HEVC_IMAGE_FRAME_HEIGHT, ENC, HEVC, 128, 512, 1, 512},
{CAP_HEIC_IMAGE_FRAME_WIDTH, ENC, HEVC, 512, 16384, 1, 16384},
{CAP_HEIC_IMAGE_FRAME_HEIGHT, ENC, HEVC, 512, 16384, 1, 16384},
/*
* Level for AVC and HEVC encoder specific.
* Default for levels is UNKNOWN value. But if we use unknown
* value here to set as default, max value needs to be set to
* unknown as well, which creates a problem of allowing client
* to set higher level than supported.
*/
{CAP_H264_LEVEL, ENC, H264, V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
V4L2_MPEG_VIDEO_H264_LEVEL_5_1, 1,
V4L2_MPEG_VIDEO_H264_LEVEL_4_0},
{CAP_HEVC_LEVEL, ENC, HEVC, V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
V4L2_MPEG_VIDEO_HEVC_LEVEL_5, 1,
V4L2_MPEG_VIDEO_HEVC_LEVEL_4},
/* Level for AVC and HEVC decoder specific */
{CAP_H264_LEVEL, DEC, H264, V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
V4L2_MPEG_VIDEO_H264_LEVEL_5_1, 1,
V4L2_MPEG_VIDEO_H264_LEVEL_4_0},
{CAP_HEVC_LEVEL, DEC, HEVC, V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
V4L2_MPEG_VIDEO_HEVC_LEVEL_5, 1,
V4L2_MPEG_VIDEO_HEVC_LEVEL_4},
};
static struct msm_vidc_codec_capability shima_capabilities_v2[] = {
/* {cap_type, domains, codecs, min, max, step_size, default_value,} */
{CAP_FRAME_WIDTH, DEC, CODECS_ALL, 96, 4096, 1, 1920},
{CAP_FRAME_HEIGHT, DEC, CODECS_ALL, 96, 4096, 1, 1080},
{CAP_FRAME_WIDTH, ENC, CODECS_ALL, 128, 4096, 1, 1920},
{CAP_FRAME_HEIGHT, ENC, CODECS_ALL, 128, 4096, 1, 1080},
/* (4096 * 2176) / 256 */
{CAP_MBS_PER_FRAME, DEC, CODECS_ALL, 36, 34816, 1, 8160},
{CAP_MBS_PER_FRAME, ENC, CODECS_ALL, 64, 34816, 1, 8160},
/* ((3840 * 2176) / 256) * 30 fps */
{CAP_MBS_PER_SECOND, DEC, CODECS_ALL, 36, 979200, 1, 244800},
{CAP_MBS_PER_SECOND, ENC, CODECS_ALL, 64, 979200, 1, 244800},
{CAP_FRAMERATE, DOMAINS_ALL, CODECS_ALL, 1, 240, 1, 30},
{CAP_BITRATE, DOMAINS_ALL, CODECS_ALL, 1, 100000000, 1, 20000000},
{CAP_CABAC_BITRATE, ENC, H264, 1, 100000000, 1, 20000000},
{CAP_SCALE_X, ENC, CODECS_ALL, 8192, 65536, 1, 8192},
{CAP_SCALE_Y, ENC, CODECS_ALL, 8192, 65536, 1, 8192},
{CAP_SCALE_X, DEC, CODECS_ALL, 65536, 65536, 1, 65536},
{CAP_SCALE_Y, DEC, CODECS_ALL, 65536, 65536, 1, 65536},
{CAP_BFRAME, ENC, H264|HEVC, 0, 1, 1, 0},
{CAP_HIER_P_NUM_ENH_LAYERS, ENC, H264|HEVC, 0, 6, 1, 0},
{CAP_LTR_COUNT, ENC, H264|HEVC, 0, 2, 1, 0},
/* ((1920 * 1088) / 256) * 60 fps */
{CAP_MBS_PER_SECOND_POWER_SAVE, ENC, CODECS_ALL,
0, 244800, 1, 244800},
{CAP_I_FRAME_QP, ENC, H264|HEVC, 0, 51, 1, 10},
{CAP_P_FRAME_QP, ENC, H264|HEVC, 0, 51, 1, 20},
{CAP_B_FRAME_QP, ENC, H264|HEVC, 0, 51, 1, 20},
/* 10 slices */
{CAP_SLICE_BYTE, ENC, H264|HEVC, 1, 10, 1, 10},
{CAP_SLICE_MB, ENC, H264|HEVC, 1, 10, 1, 10},
{CAP_MAX_VIDEOCORES, DOMAINS_ALL, CODECS_ALL, 0, 1, 1, 1},
/* Mpeg2 decoder specific */
{CAP_FRAME_WIDTH, DEC, MPEG2, 96, 1920, 1, 1920},
{CAP_FRAME_HEIGHT, DEC, MPEG2, 96, 1920, 1, 1080},
/* (1920 * 1088) / 256 */
{CAP_MBS_PER_FRAME, DEC, MPEG2, 36, 8160, 1, 8160},
/* ((1920 * 1088) / 256) * 30*/
{CAP_MBS_PER_SECOND, DEC, MPEG2, 36, 244800, 1, 244800},
{CAP_FRAMERATE, DEC, MPEG2, 1, 30, 1, 30},
{CAP_BITRATE, DEC, MPEG2, 1, 40000000, 1, 20000000},
/* Secure usecase specific */
{CAP_SECURE_FRAME_WIDTH, DEC, CODECS_ALL, 96, 4096, 1, 1920},
{CAP_SECURE_FRAME_HEIGHT, DEC, CODECS_ALL, 96, 4096, 1, 1080},
{CAP_SECURE_FRAME_WIDTH, ENC, CODECS_ALL, 128, 4096, 1, 1920},
{CAP_SECURE_FRAME_HEIGHT, ENC, CODECS_ALL, 128, 4096, 1, 1080},
/* (4096 * 2176) / 256 */
{CAP_SECURE_MBS_PER_FRAME, DEC, CODECS_ALL, 36, 34816, 1, 8160},
{CAP_SECURE_MBS_PER_FRAME, ENC, CODECS_ALL, 64, 34816, 1, 8160},
{CAP_SECURE_BITRATE, DOMAINS_ALL, CODECS_ALL, 1, 40000000, 1, 20000000},
/* Batch Mode Decode */
{CAP_BATCH_MAX_MB_PER_FRAME, DEC, CODECS_ALL, 36, 8160, 1, 8160},
/* (1920 * 1088) / 256 */
{CAP_BATCH_MAX_FPS, DEC, CODECS_ALL, 1, 30, 1, 30},
/* Lossless encoding usecase specific */
{CAP_LOSSLESS_FRAME_WIDTH, ENC, H264|HEVC, 128, 4096, 1, 1920},
{CAP_LOSSLESS_FRAME_HEIGHT, ENC, H264|HEVC, 128, 4096, 1, 1080},
/* (4096 * 2176) / 256 */
{CAP_LOSSLESS_MBS_PER_FRAME, ENC, H264|HEVC, 64, 34816, 1, 8160},
/* All intra encoding usecase specific */
{CAP_ALLINTRA_MAX_FPS, ENC, H264|HEVC, 1, 120, 1, 30},
/* Image specific */
{CAP_HEVC_IMAGE_FRAME_WIDTH, ENC, HEVC, 128, 512, 1, 512},
{CAP_HEVC_IMAGE_FRAME_HEIGHT, ENC, HEVC, 128, 512, 1, 512},
{CAP_HEIC_IMAGE_FRAME_WIDTH, ENC, HEVC, 512, 16384, 1, 16384},
{CAP_HEIC_IMAGE_FRAME_HEIGHT, ENC, HEVC, 512, 16384, 1, 16384},
/*
* Level for AVC and HEVC encoder specific.
* Default for levels is UNKNOWN value. But if we use unknown
* value here to set as default, max value needs to be set to
* unknown as well, which creates a problem of allowing client
* to set higher level than supported.
*/
{CAP_H264_LEVEL, ENC, H264, V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
V4L2_MPEG_VIDEO_H264_LEVEL_5_0, 1,
V4L2_MPEG_VIDEO_H264_LEVEL_4_0},
{CAP_HEVC_LEVEL, ENC, HEVC, V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1, 1,
V4L2_MPEG_VIDEO_HEVC_LEVEL_4},
/* Level for AVC and HEVC decoder specific */
{CAP_H264_LEVEL, DEC, H264, V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
V4L2_MPEG_VIDEO_H264_LEVEL_5_0, 1,
V4L2_MPEG_VIDEO_H264_LEVEL_4_0},
{CAP_HEVC_LEVEL, DEC, HEVC, V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1, 1,
V4L2_MPEG_VIDEO_HEVC_LEVEL_4},
};
/*
* Custom conversion coefficients for resolution: 176x144 negative
* coeffs are converted to s4.9 format
@ -410,11 +726,23 @@ static u32 vpe_csc_custom_limit_coeff[HAL_MAX_LIMIT_COEFFS] = {
16, 235, 16, 240, 16, 240
};
struct allowed_clock_rates_table shima_clock_data_v0[] = {
{240000000}, {338000000}, {366000000}, {444000000}
};
struct allowed_clock_rates_table shima_clock_data_v2[] = {
{201600000}
};
static struct msm_vidc_common_data default_common_data[] = {
{
.key = "qcom,never-unload-fw",
.value = 1,
},
{
.key = "qcom,fw-unload-delay",
.value = 1000,
},
};
static struct msm_vidc_common_data lahaina_common_data[] = {
@ -422,6 +750,10 @@ static struct msm_vidc_common_data lahaina_common_data[] = {
.key = "qcom,never-unload-fw",
.value = 1,
},
{
.key = "qcom,fw-unload-delay",
.value = 1000,
},
{
.key = "qcom,sw-power-collapse",
.value = 1,
@ -548,6 +880,10 @@ static struct msm_vidc_common_data bengal_common_data_v0[] = {
.key = "qcom,never-unload-fw",
.value = 1,
},
{
.key = "qcom,fw-unload-delay",
.value = 1000,
},
{
.key = "qcom,sw-power-collapse",
.value = 1,
@ -611,6 +947,10 @@ static struct msm_vidc_common_data bengal_common_data_v1[] = {
.key = "qcom,never-unload-fw",
.value = 1,
},
{
.key = "qcom,fw-unload-delay",
.value = 1000,
},
{
.key = "qcom,sw-power-collapse",
.value = 1,
@ -669,11 +1009,355 @@ static struct msm_vidc_common_data bengal_common_data_v1[] = {
},
};
static struct msm_vidc_common_data shima_common_data_v0[] = {
{
.key = "qcom,never-unload-fw",
.value = 1,
},
{
.key = "qcom,fw-unload-delay",
.value = 1000,
},
{
.key = "qcom,sw-power-collapse",
.value = 1,
},
{
.key = "qcom,domain-attr-non-fatal-faults",
.value = 1,
},
{
.key = "qcom,max-secure-instances",
.value = 3,
},
{
.key = "qcom,max-hw-load",
.value = 4147200,
/**
* (3840x2176)/256)@120fps decode,
* (8192x4320)/256)@30fps decode
*/
},
{
.key = "qcom,max-mbpf",
.value = 138240, /* ((8192x4320)/256) */
},
{
.key = "qcom,max-hq-mbs-per-frame",
.value = 8160, /* ((1920x1088)/256) */
},
{
.key = "qcom,max-hq-mbs-per-sec",
.value = 244800, /* ((1920x1088)/256)@30fps */
},
{
.key = "qcom,power-collapse-delay",
.value = 1500,
},
{
.key = "qcom,hw-resp-timeout",
.value = 1000,
},
{
.key = "qcom,debug-timeout",
.value = 0,
},
{
.key = "qcom,decode-batching",
.value = 1,
},
{
.key = "qcom,batch-timeout",
.value = 200,
},
{
.key = "qcom,dcvs",
.value = 1,
},
{
.key = "qcom,fw-cycles",
.value = 326389,
},
{
.key = "qcom,fw-vpp-cycles",
.value = 44156,
},
{
.key = "qcom,avsync-window-size",
.value = 40,
},
{
.key = "qcom,prefetch_non_pix_buf_count",
.value = 1,
},
{
.key = "qcom,prefetch_non_pix_buf_size",
/*
* Internal buffer size is calculated for secure decode session
* of resolution 4k (4096x2160)
* Internal buf size = calculate_scratch_size() +
* calculate_scratch1_size() + calculate_persist1_size()
* Take maximum between VP9 10bit, HEVC 10bit, AVC, MPEG2 secure
* decoder sessions
*/
.value = 209715200,
},
{
.key = "qcom,prefetch_pix_buf_count",
.value = 18,
},
{
.key = "qcom,prefetch_pix_buf_size",
/*
* Calculated by VENUS_BUFFER_SIZE for 4096x2160 UBWC
*/
.value = 13434880,
},
{
.key = "qcom,ubwc_stats_in_fbd",
.value = 0,
},
{
.key = "qcom,vpp_delay_supported",
.value = 0,
},
};
static struct msm_vidc_common_data shima_common_data_v1[] = {
{
.key = "qcom,never-unload-fw",
.value = 1,
},
{
.key = "qcom,fw-unload-delay",
.value = 1000,
},
{
.key = "qcom,sw-power-collapse",
.value = 1,
},
{
.key = "qcom,domain-attr-non-fatal-faults",
.value = 1,
},
{
.key = "qcom,max-secure-instances",
.value = 3,
},
{
.key = "qcom,max-hw-load",
.value = 1958400,
/**
* (3840x2176)/256)@60fps decode
*/
},
{
.key = "qcom,max-mbpf",
.value = 130560, /* ((3840x2176)/256) x 4 */
},
{
.key = "qcom,max-hq-mbs-per-frame",
.value = 8160, /* ((1920x1088)/256) */
},
{
.key = "qcom,max-hq-mbs-per-sec",
.value = 244800, /* ((1920x1088)/256)@30fps */
},
{
.key = "qcom,power-collapse-delay",
.value = 1500,
},
{
.key = "qcom,hw-resp-timeout",
.value = 1000,
},
{
.key = "qcom,debug-timeout",
.value = 0,
},
{
.key = "qcom,decode-batching",
.value = 1,
},
{
.key = "qcom,batch-timeout",
.value = 200,
},
{
.key = "qcom,dcvs",
.value = 1,
},
{
.key = "qcom,fw-cycles",
.value = 326389,
},
{
.key = "qcom,fw-vpp-cycles",
.value = 44156,
},
{
.key = "qcom,avsync-window-size",
.value = 40,
},
{
.key = "qcom,prefetch_non_pix_buf_count",
.value = 1,
},
{
.key = "qcom,prefetch_non_pix_buf_size",
/*
* Internal buffer size is calculated for secure decode session
* of resolution 4k (4096x2160)
* Internal buf size = calculate_scratch_size() +
* calculate_scratch1_size() + calculate_persist1_size()
* Take maximum between VP9 10bit, HEVC 10bit, AVC, MPEG2 secure
* decoder sessions
*/
.value = 209715200,
},
{
.key = "qcom,prefetch_pix_buf_count",
.value = 18,
},
{
.key = "qcom,prefetch_pix_buf_size",
/*
* Calculated by VENUS_BUFFER_SIZE for 4096x2160 UBWC
*/
.value = 13434880,
},
{
.key = "qcom,ubwc_stats_in_fbd",
.value = 0,
},
{
.key = "qcom,vpp_delay_supported",
.value = 0,
},
};
static struct msm_vidc_common_data shima_common_data_v2[] = {
{
.key = "qcom,never-unload-fw",
.value = 1,
},
{
.key = "qcom,fw-unload-delay",
.value = 1000,
},
{
.key = "qcom,sw-power-collapse",
.value = 1,
},
{
.key = "qcom,domain-attr-non-fatal-faults",
.value = 1,
},
{
.key = "qcom,max-secure-instances",
.value = 3,
},
{
.key = "qcom,max-hw-load",
.value = 979200,
/**
* (3840x2176)/256)@30fps decode
*/
},
{
.key = "qcom,max-mbpf",
.value = 130560, /* ((3840x2176)/256) x 4 */
},
{
.key = "qcom,max-hq-mbs-per-frame",
.value = 8160, /* ((1920x1088)/256) */
},
{
.key = "qcom,max-hq-mbs-per-sec",
.value = 244800, /* ((1920x1088)/256)@30fps */
},
{
.key = "qcom,power-collapse-delay",
.value = 1500,
},
{
.key = "qcom,hw-resp-timeout",
.value = 1000,
},
{
.key = "qcom,debug-timeout",
.value = 0,
},
{
.key = "qcom,decode-batching",
.value = 1,
},
{
.key = "qcom,batch-timeout",
.value = 200,
},
{
.key = "qcom,dcvs",
.value = 1,
},
{
.key = "qcom,fw-cycles",
.value = 326389,
},
{
.key = "qcom,fw-vpp-cycles",
.value = 44156,
},
{
.key = "qcom,avsync-window-size",
.value = 40,
},
{
.key = "qcom,prefetch_non_pix_buf_count",
.value = 1,
},
{
.key = "qcom,prefetch_non_pix_buf_size",
/*
* Internal buffer size is calculated for secure decode session
* of resolution 4k (4096x2160)
* Internal buf size = calculate_scratch_size() +
* calculate_scratch1_size() + calculate_persist1_size()
* Take maximum between VP9 10bit, HEVC 10bit, AVC, MPEG2 secure
* decoder sessions
*/
.value = 209715200,
},
{
.key = "qcom,prefetch_pix_buf_count",
.value = 18,
},
{
.key = "qcom,prefetch_pix_buf_size",
/*
* Calculated by VENUS_BUFFER_SIZE for 4096x2160 UBWC
*/
.value = 13434880,
},
{
.key = "qcom,ubwc_stats_in_fbd",
.value = 0,
},
{
.key = "qcom,vpp_delay_supported",
.value = 0,
},
};
static struct msm_vidc_common_data holi_common_data[] = {
{
.key = "qcom,never-unload-fw",
.value = 1,
},
{
.key = "qcom,fw-unload-delay",
.value = 1000,
},
{
.key = "qcom,sw-power-collapse",
.value = 1,
@ -716,11 +1400,23 @@ static struct msm_vidc_common_data holi_common_data[] = {
},
};
static struct msm_vidc_efuse_data shima_efuse_data[] = {
/* IRIS_4K60_FMAX_LIMIT_EFUSE - max 4K@60 */
EFUSE_ENTRY(0x007801E0, 4, 0x00200000, 0x15, SKU_VERSION),
/* IRIS_MULTIPIPE_DISABLE - max 4K@30 */
EFUSE_ENTRY(0x007801E0, 4, 0x00001000, 0x0B, SKU_VERSION),
};
/* Default UBWC config for LPDDR5 */
static struct msm_vidc_ubwc_config_data lahaina_ubwc_data[] = {
UBWC_CONFIG(1, 1, 1, 0, 0, 0, 8, 32, 16, 0, 0),
};
/* Default UBWC config for LPDDR5 */
static struct msm_vidc_ubwc_config_data shima_ubwc_data[] = {
UBWC_CONFIG(1, 1, 1, 0, 0, 0, 8, 32, 15, 0, 0),
};
static struct msm_vidc_platform_data default_data = {
.codec_data = default_codec_data,
.codec_data_length = ARRAY_SIZE(default_codec_data),
@ -740,6 +1436,8 @@ static struct msm_vidc_platform_data default_data = {
static struct msm_vidc_platform_data lahaina_data = {
.codec_data = lahaina_codec_data,
.codec_data_length = ARRAY_SIZE(lahaina_codec_data),
.clock_data = NULL,
.clock_data_length = 0,
.common_data = lahaina_common_data,
.common_data_length = ARRAY_SIZE(lahaina_common_data),
.csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff,
@ -760,6 +1458,8 @@ static struct msm_vidc_platform_data lahaina_data = {
static struct msm_vidc_platform_data bengal_data = {
.codec_data = bengal_codec_data,
.codec_data_length = ARRAY_SIZE(bengal_codec_data),
.clock_data = NULL,
.clock_data_length = 0,
.common_data = bengal_common_data_v0,
.common_data_length = ARRAY_SIZE(bengal_common_data_v0),
.csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff,
@ -777,9 +1477,33 @@ static struct msm_vidc_platform_data bengal_data = {
.codec_caps_count = ARRAY_SIZE(bengal_capabilities_v0),
};
static struct msm_vidc_platform_data shima_data = {
.codec_data = shima_codec_data,
.codec_data_length = ARRAY_SIZE(shima_codec_data),
.clock_data = shima_clock_data_v0,
.clock_data_length = ARRAY_SIZE(shima_clock_data_v0),
.common_data = shima_common_data_v0,
.common_data_length = ARRAY_SIZE(shima_common_data_v0),
.csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff,
.csc_data.vpe_csc_custom_matrix_coeff = vpe_csc_custom_matrix_coeff,
.csc_data.vpe_csc_custom_limit_coeff = vpe_csc_custom_limit_coeff,
.efuse_data = shima_efuse_data,
.efuse_data_length = ARRAY_SIZE(shima_efuse_data),
.sku_version = 0,
.vpu_ver = VPU_VERSION_IRIS2,
.num_vpp_pipes = 0x2,
.ubwc_config = shima_ubwc_data,
.codecs = shima_codecs,
.codecs_count = ARRAY_SIZE(shima_codecs),
.codec_caps = shima_capabilities_v0,
.codec_caps_count = ARRAY_SIZE(shima_capabilities_v0),
};
static struct msm_vidc_platform_data holi_data = {
.codec_data = holi_codec_data,
.codec_data_length = ARRAY_SIZE(holi_codec_data),
.clock_data = NULL,
.clock_data_length = 0,
.common_data = holi_common_data,
.common_data_length = ARRAY_SIZE(holi_common_data),
.csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff,
@ -802,6 +1526,10 @@ static const struct of_device_id msm_vidc_dt_device[] = {
.compatible = "qcom,lahaina-vidc",
.data = &lahaina_data,
},
{
.compatible = "qcom,shima-vidc",
.data = &shima_data,
},
{
.compatible = "qcom,bengal-vidc",
.data = &bengal_data,
@ -815,6 +1543,48 @@ static const struct of_device_id msm_vidc_dt_device[] = {
MODULE_DEVICE_TABLE(of, msm_vidc_dt_device);
static int msm_vidc_read_efuse(
struct msm_vidc_platform_data *data, struct device *dev)
{
void __iomem *base;
uint32_t i;
u32 efuse = 0;
struct msm_vidc_efuse_data *efuse_data = data->efuse_data;
uint32_t efuse_data_count = data->efuse_data_length;
if (!efuse_data)
return 0;
for (i = 0; i < efuse_data_count; i++) {
switch ((efuse_data[i]).purpose) {
case SKU_VERSION:
base = devm_ioremap(dev, (efuse_data[i]).start_address,
(efuse_data[i]).size);
if (!base) {
d_vpr_e("failed efuse: start %#x, size %d\n",
(efuse_data[i]).start_address,
(efuse_data[i]).size);
return -EINVAL;
} else {
efuse = readl_relaxed(base);
data->sku_version =
(efuse & (efuse_data[i]).mask) >>
(efuse_data[i]).shift;
devm_iounmap(dev, base);
}
break;
default:
break;
}
if (data->sku_version) {
d_vpr_h("efuse 0x%x, platform version 0x%x\n",
efuse, data->sku_version);
break;
}
}
return 0;
}
static int msm_vidc_read_rank(
struct msm_vidc_platform_data *data, struct device *dev)
{
@ -850,6 +1620,13 @@ void *vidc_get_drv_data(struct device *dev)
if (!driver_data)
goto exit;
/* Check for sku version */
if (of_find_property(dev->of_node, "sku-index", NULL)) {
rc = msm_vidc_read_efuse(driver_data, dev);
if (rc)
goto exit;
}
if (!strcmp(match->compatible, "qcom,lahaina-vidc")) {
ddr_type = of_fdt_get_ddrtype();
if (ddr_type == -ENOENT) {
@ -878,6 +1655,40 @@ void *vidc_get_drv_data(struct device *dev)
driver_data->codec_caps_count =
ARRAY_SIZE(bengal_capabilities_v1);
}
} else if (!strcmp(match->compatible, "qcom,shima-vidc")) {
if (driver_data->sku_version == SKU_VERSION_1) {
driver_data->clock_data = NULL;
driver_data->clock_data_length = 0;
driver_data->common_data = shima_common_data_v1;
driver_data->common_data_length =
ARRAY_SIZE(shima_common_data_v1);
driver_data->codec_caps = shima_capabilities_v1;
driver_data->codec_caps_count =
ARRAY_SIZE(shima_capabilities_v1);
} else if (driver_data->sku_version == SKU_VERSION_2) {
driver_data->clock_data = shima_clock_data_v2;
driver_data->clock_data_length =
ARRAY_SIZE(shima_clock_data_v2);
driver_data->common_data = shima_common_data_v2;
driver_data->common_data_length =
ARRAY_SIZE(shima_common_data_v2);
driver_data->codec_caps = shima_capabilities_v2;
driver_data->codec_caps_count =
ARRAY_SIZE(shima_capabilities_v2);
}
ddr_type = of_fdt_get_ddrtype();
if (ddr_type == -ENOENT) {
d_vpr_e("Failed to get ddr type, use LPDDR5\n");
}
if (driver_data->ubwc_config &&
(ddr_type == DDR_TYPE_LPDDR4 ||
ddr_type == DDR_TYPE_LPDDR4X))
driver_data->ubwc_config->highest_bank_bit = 0xe;
d_vpr_h("DDR Type 0x%x hbb 0x%x\n",
ddr_type, driver_data->ubwc_config ?
driver_data->ubwc_config->highest_bank_bit : -1);
}
exit:
return driver_data;

34
msm/vidc/msm_vidc_res_parse.c
View file

@ -347,6 +347,11 @@ static int msm_vidc_load_allowed_clocks_table(
int rc = 0;
struct platform_device *pdev = res->pdev;
if (res->allowed_clks_tbl) {
d_vpr_h("allowed-clock-rates populated from platform_data\n");
return 0;
}
if (!of_find_property(pdev->dev.of_node,
"qcom,allowed-clock-rates", NULL)) {
d_vpr_h("allowed-clock-rates not found\n");
@ -692,29 +697,6 @@ static int msm_vidc_load_reset_table(
return 0;
}
static int msm_decide_dt_node(
struct msm_vidc_platform_resources *res)
{
struct platform_device *pdev = res->pdev;
int rc = 0;
u32 sku_index = 0;
rc = of_property_read_u32(pdev->dev.of_node, "sku-index",
&sku_index);
if (rc) {
d_vpr_h("'sku_index' not found in node\n");
return 0;
}
if (sku_index != res->sku_version) {
d_vpr_h("Failed to parse dt: sku_index %d sku_version %d\n",
sku_index, res->sku_version);
return -EINVAL;
}
return 0;
}
static int find_key_value(struct msm_vidc_platform_data *platform_data,
const char *key)
{
@ -749,6 +731,8 @@ int read_platform_resources_from_drv_data(
res->codec_caps_count = platform_data->codec_caps_count;
res->codec_data_count = platform_data->codec_data_length;
res->codec_data = platform_data->codec_data;
res->allowed_clks_tbl = platform_data->clock_data;
res->allowed_clks_tbl_size = platform_data->clock_data_length;
res->sku_version = platform_data->sku_version;
res->mem_limit_tbl = memory_limit_tbl_mbytes;
@ -852,10 +836,6 @@ int read_platform_resources_from_dt(
return -ENOENT;
}
rc = msm_decide_dt_node(res);
if (rc)
return rc;
INIT_LIST_HEAD(&res->context_banks);
res->firmware_base = (phys_addr_t)firmware_base;

7
msm/vidc/vidc_hfi_api.h
View file

@ -384,10 +384,9 @@ struct hal_fw_info {
};
enum hal_flush {
HAL_FLUSH_INPUT,
HAL_FLUSH_OUTPUT,
HAL_FLUSH_ALL,
HAL_UNUSED_FLUSH = 0x10000000,
HAL_FLUSH_INPUT = BIT(0),
HAL_FLUSH_OUTPUT = BIT(1),
HAL_FLUSH_ALL = HAL_FLUSH_INPUT | HAL_FLUSH_OUTPUT,
};
enum hal_event_type {

4
msm/vidc/vidc_hfi_helper.h
View file

@ -541,6 +541,10 @@ struct hfi_intra_period {
u32 bframes;
};
struct hfi_adaptive_p_b_intra_period {
u32 nframes;
};
struct hfi_multi_stream {
u32 buffer_type;
u32 enable;