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Merge "ARM: dts: msm: Add CVP device tree for Lahaina"
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152
bindings/media/msm-cvp.txt
Normal file
152
bindings/media/msm-cvp.txt
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* Qualcomm Technologies, Inc. MSM CVP
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[Root level node]
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cvp
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=====
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Required properties:
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- compatible : one of:
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- "qcom,msm-cvp"
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- "qcom,lahaina-cvp" : Invokes driver specific data for Lahaina.
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Optional properties:
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- reg : offset and length of the CSR register set for the device.
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- interrupts : should contain the cvp interrupt.
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- qcom,reg-presets : list of offset-value pairs for registers to be written.
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The offsets are from the base offset specified in 'reg'. This is mainly
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used for QoS, VBIF, etc. presets for video.
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- qcom,qdss-presets : list of physical address and memory allocation size pairs.
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when fw_debug_mode is set as HFI_DEBUG_MODE_QDSS, all firmware messages will be
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written to QDSS memory.
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- *-supply: A phandle pointing to the appropriate regulator. Number of
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regulators vary across targets.
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- clock-names: an array of clocks that the driver is supposed to be
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manipulating. The clocks names here correspond to the clock names used in
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clk_get(<name>).
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- qcom,clock-configs = an array of bitmaps of clocks' configurations. The index
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of the bitmap corresponds to the clock at the same index in qcom,clock-names.
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The bitmaps describes the actions that the device needs to take regarding the
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clock (i.e. scale it based on load).
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The bitmap is defined as:
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scalable = 0x1 (if the driver should vary the clock's frequency based on load)
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- qcom,allowed-clock-rates = an array of supported clock rates by the chipset.
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- qcom,use-non-secure-pil = A bool indicating which type of pil to use to load
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the fw.
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- qcom,fw-bias = The address at which cvp fw is loaded (manually).
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[Second level nodes]
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Context Banks
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=============
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Required properties:
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- compatible : one of:
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- "qcom,msm-cvp,context-bank"
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- iommus : A phandle parsed by smmu driver. Number of entries will vary
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across targets.
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Optional properties:
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- label - string describing iommu domain usage.
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- buffer-types : bitmap of buffer types that can be mapped into the current
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IOMMU domain.
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- Buffer types are defined as the following:
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input = 0x1
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output = 0x2
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output2 = 0x4
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extradata input = 0x8
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extradata output = 0x10
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extradata output2 = 0x20
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internal scratch = 0x40
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internal scratch1 = 0x80
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internal scratch2 = 0x100
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internal persist = 0x200
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internal persist1 = 0x400
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internal cmd queue = 0x800
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- virtual-addr-pool : offset and length of virtual address pool.
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- qcom,fw-context-bank : bool indicating firmware context bank.
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- qcom,secure-context-bank : bool indicating secure context bank.
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Buses
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=====
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Required properties:
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- compatible : one of:
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- "qcom,msm-cvp,bus"
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- label : an arbitrary name
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- qcom,bus-master : an integer descriptor of the bus master. Refer to arch/arm/\
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boot/dts/include/dt-bindings/msm/msm-bus-ids.h for list of acceptable masters
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- qcom,bus-slave : an integer descriptor of the bus slave. Refer to arch/arm/\
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boot/dts/include/dt-bindings/msm/msm-bus-ids.h for list of acceptable slaves
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Optional properties:
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- qcom,bus-governor : governor to use when scaling bus, generally any commonly
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found devfreq governor might be used. In addition to those governors, the
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custom Venus governors, "msm-vidc-ddr" or "msm-vidc-llcc" are also
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acceptable values.
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In the absence of this property the "performance" governor is used.
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- qcom,bus-rage-kbps : an array of two items (<min max>) that indicate the
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minimum and maximum acceptable votes for the bus.
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In the absence of this property <0 INT_MAX> is used.
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- qcom,ubwc-10bit : UBWC 10 bit content has different bus requirements,
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this tag will be used to pick the appropriate bus as per the session profile
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as shown below in example.
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Memory Heaps
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============
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Required properties:
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- compatible : one of:
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- "qcom,msm-vidc,mem-cdsp"
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- memory-region : phandle to the memory heap/region.
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Example:
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msm_cvp: qcom,cvp@ab00000 {
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compatible = "qcom,msm-cvp", "qcom,Lahaina-cvp";
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status = "ok";
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reg = <0xab00000 0x100000>;
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interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
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/* FIXME: LLCC Info */
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/* cache-slice-names = "vidsc0", "vidsc1"; */
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/* cache-slices = <&llcc 2>, <&llcc 3>; */
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/* Supply */
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cvp-supply = <&mvs1_gdsc>;
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/* Clocks */
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clock-names = "gcc_video_axi0",
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"gcc_video_axi1", "cvp_clk";
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clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>,
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<&clock_gcc GCC_VIDEO_AXI1_CLK>,
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<&clock_videocc VIDEO_CC_MVS1_CLK>;
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qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_axi1",
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"cvp_clk";
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qcom,clock-configs = <0x0 0x0 0x1>;
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qcom,allowed-clock-rates = <403000000 520000000
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549000000 666000000 800000000>;
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/* Buses */
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bus_cnoc {
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compatible = "qcom,msm-cvp,bus";
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label = "cnoc";
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qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
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qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
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qcom,bus-governor = "performance";
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qcom,bus-range-kbps = <1000 1000>;
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};
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/* MMUs */
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non_secure_cb {
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compatible = "qcom,msm-cvp,context-bank";
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label = "cvp_hlos";
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iommus =
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<&apps_smmu 0x2120 0x400>;
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qcom,iommu-dma = "disabled";
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buffer-types = <0xfff>;
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virtual-addr-pool = <0x4b000000 0xe0000000>;
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};
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/* Memory Heaps */
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qcom,msm-cvp,mem_cdsp {
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compatible = "qcom,msm-cvp,mem-cdsp";
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memory-region = <&cdsp_mem>;
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};
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};
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92
qcom/lahaina-cvp.dtsi
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92
qcom/lahaina-cvp.dtsi
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,ipcc.h>
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#include <dt-bindings/interconnect/qcom,lahaina.h>
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#include <dt-bindings/clock/qcom,videocc-lahaina.h>
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&soc {
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msm_cvp: qcom,cvp@ab00000 {
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compatible = "qcom,msm-cvp", "qcom,lahaina-cvp";
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status = "ok"
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reg = <0xab00000 0x100000>;
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interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
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/* LLCC Cache */
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cache-slice-names = "cvp";
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/* Supply */
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cvp-supply = <&video_cc_mvs1c_gdsc>;
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cvp-core-supply = <&video_cc_mvs1_gdsc>;
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/* Clocks */
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clock-names = "gcc_video_axi1", "cvp_clk", "core_clk";
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clocks = <&clock_gcc GCC_VIDEO_AXI1_CLK>,
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<&clock_videocc VIDEO_CC_MVS1C_CLK>,
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<&clock_videocc VIDEO_CC_MVS1_CLK>;
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qcom,proxy-clock-names = "gcc_video_axi1",
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"cvp_clk", "core_clk";
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qcom,clock-configs = <0x0 0x1 0x1>;
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qcom,allowed-clock-rates = <280000000 366000000 444000000>;
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resets = <&clock_videocc VIDEO_CC_MVS1C_CLK_ARES>;
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reset-names = "cvp_core_reset";
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qcom,reg-presets = <0xB0088 0x0>;
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/* Buses */
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cvp_cnoc {
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compatible = "qcom,msm-cvp,bus";
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label = "cvp-cnoc";
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qcom,bus-master = <MASTER_APPSS_PROC>;
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qcom,bus-slave = <SLAVE_VENUS_CFG>;
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qcom,bus-governor = "performance";
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qcom,bus-range-kbps = <1000 1000>;
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};
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cvp_bus_ddr {
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compatible = "qcom,msm-cvp,bus";
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label = "cvp-ddr";
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qcom,bus-master = <MASTER_VIDEO_PROC>;
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qcom,bus-slave = <SLAVE_EBI1>;
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qcom,bus-governor = "performance";
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qcom,bus-range-kbps = <1000 6533000>;
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};
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/* MMUs */
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cvp_non_secure_cb {
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compatible = "qcom,msm-cvp,context-bank";
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label = "cvp_hlos";
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iommus =
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<&apps_smmu 0x2120 0x400>;
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buffer-types = <0xfff>;
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qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>;
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};
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cvp_secure_nonpixel_cb {
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compatible = "qcom,msm-cvp,context-bank";
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label = "cvp_sec_nonpixel";
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iommus =
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<&apps_smmu 0x2124 0x400>;
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buffer-types = <0x741>;
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qcom,iommu-dma-addr-pool = <0x01000000 0x25800000>;
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qcom,iommu-vmid = <0xB>;
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};
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cvp_secure_pixel_cb {
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compatible = "qcom,msm-cvp,context-bank";
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label = "cvp_sec_pixel";
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iommus =
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<&apps_smmu 0x2123 0x400>;
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buffer-types = <0x106>;
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qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>;
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qcom,iommu-vmid = <0xA>;
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};
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/* Memory Heaps */
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qcom,msm-cvp,mem_cdsp {
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compatible = "qcom,msm-cvp,mem-cdsp";
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memory-region = <&cdsp_mem>;
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};
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};
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};
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@ -339,6 +339,15 @@
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size = <0x0 0x800000>;
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};
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cdsp_mem: cdsp_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x400000>;
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};
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cdsp_secure_heap: cdsp_secure_heap@9b200000 {
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reg = <0x0 0x9b200000 0x0 0x4600000>;
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};
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@ -1683,6 +1692,15 @@
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qcom,iommu-group = <>;
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};
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};
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qcom,cvpss@abb0000 {
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compatible = "qcom,pil-tz-generic";
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reg = <0xabb0000 0x2000>;
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status = "ok"
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qcom,pas-id = <26>;
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qcom,firmware-name = "cvpss";
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memory-region = <&pil_cvp_mem>;
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};
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};
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#include "lahaina-regulators.dtsi"
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@ -1694,3 +1712,4 @@
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#include "lahaina-pm.dtsi"
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#include "lahaina-qupv3.dtsi"
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#include "lahaina-vidc.dtsi"
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#include "lahaina-cvp.dtsi"
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