From be7c6ea0ced249b525ee8e51dba1cd452b675726 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 23 Sep 2020 23:39:51 +0530 Subject: [PATCH 001/122] ARM: dts: msm: Add device tree for Shima IDP/IDPS with 120fps platform Add device tree support for 1. Shima IDP with 120fps. 2. Shima IDPS digital mics support with 120fps. Change-Id: I7f2e820e2a2b6245b7377bc6432bbcf9e2f9607a --- qcom/Makefile | 12 +++++++++--- qcom/shima-idp-120fps-overlay.dts | 11 +++++++++++ qcom/shima-idp-120fps.dts | 10 ++++++++++ qcom/shima-idp-120fps.dtsi | 4 ++++ qcom/shima-idps-digital-mics-120fps-overlay.dts | 11 +++++++++++ qcom/shima-idps-digital-mics-120fps.dts | 10 ++++++++++ qcom/shima-idps-digital-mics-120fps.dtsi | 6 ++++++ 7 files changed, 61 insertions(+), 3 deletions(-) create mode 100644 qcom/shima-idp-120fps-overlay.dts create mode 100644 qcom/shima-idp-120fps.dts create mode 100644 qcom/shima-idp-120fps.dtsi create mode 100644 qcom/shima-idps-digital-mics-120fps-overlay.dts create mode 100644 qcom/shima-idps-digital-mics-120fps.dts create mode 100644 qcom/shima-idps-digital-mics-120fps.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 1a1c6f058bd8..7ed2de109fca 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -104,22 +104,28 @@ endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_SHIMA) += \ shima-rumi-overlay.dtbo \ - shima-idp-overlay.dtbo \ + shima-idp-overlay.dtbo \ + shima-idp-120fps-overlay.dtbo \ shima-atp-overlay.dtbo \ shima-qrd-overlay.dtbo \ - shima-idps-digital-mics-overlay.dtbo + shima-idps-digital-mics-overlay.dtbo \ + shima-idps-digital-mics-120fps-overlay.dtbo shima-rumi-overlay.dtbo-base := shima.dtb shima-idp-overlay.dtbo-base := shima.dtb +shima-idp-120fps-overlay.dtbo-base := shima.dtb shima-atp-overlay.dtbo-base := shima.dtb shima-qrd-overlay.dtbo-base := shima.dtb shima-idps-digital-mics-overlay.dtbo-base := shima.dtb +shima-idps-digital-mics-120fps-overlay.dtbo-base := shima.dtb else dtb-$(CONFIG_ARCH_SHIMA) += shima-rumi.dtb \ shima-idp.dtb \ + shima-idp-120fps.dtb \ shima-atp.dtb \ shima-qrd.dtb \ - shima-idps-digital-mics.dtb + shima-idps-digital-mics.dtb \ + shima-idps-digital-mics-120fps.dtb endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) diff --git a/qcom/shima-idp-120fps-overlay.dts b/qcom/shima-idp-120fps-overlay.dts new file mode 100644 index 000000000000..ef17b34fcdb7 --- /dev/null +++ b/qcom/shima-idp-120fps-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "shima-idp-120fps.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Shima IDP + 120fps"; + compatible = "qcom,shima-idp", "qcom,shima", "qcom,idp"; + qcom,msm-id = <450 0x10000>; + qcom,board-id = <34 2>; +}; diff --git a/qcom/shima-idp-120fps.dts b/qcom/shima-idp-120fps.dts new file mode 100644 index 000000000000..75ea5988bc79 --- /dev/null +++ b/qcom/shima-idp-120fps.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "shima.dtsi" +#include "shima-idp-120fps.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Shima IDP + 120fps"; + compatible = "qcom,shima-idp", "qcom,shima", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/shima-idp-120fps.dtsi b/qcom/shima-idp-120fps.dtsi new file mode 100644 index 000000000000..4f6732d3b955 --- /dev/null +++ b/qcom/shima-idp-120fps.dtsi @@ -0,0 +1,4 @@ +#include "shima-idp.dtsi" + +&soc { +}; diff --git a/qcom/shima-idps-digital-mics-120fps-overlay.dts b/qcom/shima-idps-digital-mics-120fps-overlay.dts new file mode 100644 index 000000000000..b5c784b62fb4 --- /dev/null +++ b/qcom/shima-idps-digital-mics-120fps-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "shima-idps-digital-mics-120fps.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Shima IDPS DIGITAL MICS + 120fps"; + compatible = "qcom,shima-idp", "qcom,shima", "qcom,idp"; + qcom,msm-id = <450 0x10000>; + qcom,board-id = <34 3>; +}; diff --git a/qcom/shima-idps-digital-mics-120fps.dts b/qcom/shima-idps-digital-mics-120fps.dts new file mode 100644 index 000000000000..f6773a9471eb --- /dev/null +++ b/qcom/shima-idps-digital-mics-120fps.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "shima.dtsi" +#include "shima-idps-digital-mics-120fps.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Shima IDPS DIGITAL MICS + 120fps"; + compatible = "qcom,shima-idp", "qcom,shima", "qcom,idp"; + qcom,board-id = <34 3>; +}; diff --git a/qcom/shima-idps-digital-mics-120fps.dtsi b/qcom/shima-idps-digital-mics-120fps.dtsi new file mode 100644 index 000000000000..51ccf2dd48fd --- /dev/null +++ b/qcom/shima-idps-digital-mics-120fps.dtsi @@ -0,0 +1,6 @@ +#include "shima-idps-digital-mics.dtsi" + +&soc { +}; + + From 4e5aa7697f2419bf65f15e3aff9655cbc2756be1 Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Thu, 24 Sep 2020 09:57:30 +0530 Subject: [PATCH 002/122] ARM: dts: msm: Add 144 fps touch support on shima target Add 144 fps panel touch support on shima target. Change-Id: I67d8a042a66c157acbeed0ed1452ed36e0e4c9f7 --- qcom/shima-idp.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index d0a694ca961b..a4be84ba4aee 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -180,7 +180,8 @@ panel = <&dsi_r66451_amoled_cmd &dsi_r66451_amoled_video &dsi_r66451_amoled_60hz_video - &dsi_r66451_amoled_60hz_cmd>; + &dsi_r66451_amoled_60hz_cmd + &dsi_r66451_amoled_144hz_cmd>; focaltech,trusted-touch-mode = "vm_mode"; focaltech,touch-environment = "pvm"; From 9e91b3dfefe8a159ad51c8ecf097892f1714be94 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Thu, 24 Sep 2020 17:12:58 +0530 Subject: [PATCH 003/122] ARM: dts: msm: Select 120Hz panel as default on 120Hz shima dts This change adds support to select 120Hz command mode panel as default panel on shima 120Hz IDP/IDPS platform. Change-Id: I2ca4fb9f181ad3b721ce05a4740cf18f4127bddc --- qcom/shima-idp-120fps.dtsi | 4 ++++ qcom/shima-idps-digital-mics-120fps.dtsi | 4 +++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/qcom/shima-idp-120fps.dtsi b/qcom/shima-idp-120fps.dtsi index 4f6732d3b955..f110f793bbeb 100644 --- a/qcom/shima-idp-120fps.dtsi +++ b/qcom/shima-idp-120fps.dtsi @@ -2,3 +2,7 @@ &soc { }; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; +}; diff --git a/qcom/shima-idps-digital-mics-120fps.dtsi b/qcom/shima-idps-digital-mics-120fps.dtsi index 51ccf2dd48fd..976bee956cd7 100644 --- a/qcom/shima-idps-digital-mics-120fps.dtsi +++ b/qcom/shima-idps-digital-mics-120fps.dtsi @@ -3,4 +3,6 @@ &soc { }; - +&sde_dsi { + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; +}; From 9efa409d6be1147859b9cf55566bb3755874df00 Mon Sep 17 00:00:00 2001 From: Prakash Gupta Date: Mon, 14 Sep 2020 13:07:13 +0530 Subject: [PATCH 004/122] ARM: dts: msm: enable mem_offline.bypass_send_msg for shima Enable boot param mem_offline.bypass_send_msg to skip ending AOP message for mem offline/online requests. Change-Id: Ic1edf553f4dbbcaf991257644e208b28f0625601 --- qcom/shima.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index ca7fbbd667ae..db2243b15543 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -480,7 +480,7 @@ }; chosen { - bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 mem_offline.bypass_send_msg=1"; }; soc: soc { }; From 2516aa0bf946a9595da587f9e58f3ecbdba5fd27 Mon Sep 17 00:00:00 2001 From: Prasad Sodagudi Date: Wed, 9 Sep 2020 16:13:54 -0700 Subject: [PATCH 005/122] ARM: dts: qcom: disable panic on single corruption Disable panic on the single bit corruptions on lahaina_v1 and enable for lahiana_v2 devices. Change-Id: Ib370dce0a27c0eef5515b29a5da2bac19e2d6614 --- qcom/lahaina-v2.dtsi | 5 +++++ qcom/lahaina.dtsi | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/qcom/lahaina-v2.dtsi b/qcom/lahaina-v2.dtsi index f089e5cd052f..02c849e2dba2 100644 --- a/qcom/lahaina-v2.dtsi +++ b/qcom/lahaina-v2.dtsi @@ -22,6 +22,11 @@ dynamic-power-coefficient = <760>; }; +&kryo_erp { + + /delete-property/ qcom,disable-panic-on-ce; +}; + &sde_dp { /delete-node/ qcom,pll-supply-entries; }; diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 182e5335c125..683d9a7fb4df 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -3237,11 +3237,12 @@ }; }; - kryo-erp { + kryo_erp: erp { compatible = "arm,arm64-kryo-cpu-erp"; interrupts = , ; interrupt-names = "l1-l2-faultirq","l3-scu-faultirq"; + qcom,disable-panic-on-ce; }; tcsr_mutex_block: syscon@1f40000 { From b8b5f0c1451124c2a1279f195f2a6a5bbe673d98 Mon Sep 17 00:00:00 2001 From: Raghavendra Rao Ananta Date: Thu, 24 Sep 2020 12:29:13 -0700 Subject: [PATCH 006/122] ARM: dts: msm: Vote for DDR BW for MPSS PIL on Lahaina It is possible that the DDR bandwidth requirements are not met during modem SSR. Hence, explicitly vote for DDR turbo frequency during modem PIL. Change-Id: I5134feaf593673beb8bbdafc416814a5d41fb47b --- qcom/lahaina.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 683d9a7fb4df..9d358332bd39 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -4423,6 +4423,8 @@ qcom,vdd_mss-uV-uA = ; qcom,proxy-reg-names = "vdd_cx", "vdd_mss"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,firmware-name = "modem"; memory-region = <&pil_modem_mem>; qcom,proxy-timeout-ms = <10000>; From 000ef13cbbc7a967d74fd9c270ca46c75c90fdab Mon Sep 17 00:00:00 2001 From: Manikandan Mohan Date: Fri, 25 Sep 2020 22:26:57 -0700 Subject: [PATCH 007/122] ARM: dts: msm: Update CNSS node for BT GPIO config QCA6490 requires synchronization between BT and WLAN GPIOs for PMU power up. Update CNSS device tree node for BT GPIO config. Change-Id: I0cd7050dad499378ec6d2bcfbe9d78f4a79a3384 --- bindings/cnss/cnss-wlan.txt | 3 +++ qcom/lahaina.dtsi | 1 + 2 files changed, 4 insertions(+) diff --git a/bindings/cnss/cnss-wlan.txt b/bindings/cnss/cnss-wlan.txt index 02d983d74138..c1de42da51fb 100644 --- a/bindings/cnss/cnss-wlan.txt +++ b/bindings/cnss/cnss-wlan.txt @@ -87,6 +87,9 @@ Optional properties: regulator used in internal power amplifier for QCA6490 - cnss-enable-self-recovery: Boolean property to enable self recovery when recovery is trigeered with reason link down. + - qcom,bt-en-gpio: QCA6490 requires synchronization for BT and WLAN GPIO + enable to resolve PMU power up issues. Provide BT GPIO using + this config param. Example: diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 9d358332bd39..631f39833f2b 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5355,6 +5355,7 @@ <0xb2e5510 0x690>; reg-names = "smmu_iova_ipa", "tcs_cmd"; wlan-en-gpio = <&tlmm 64 0>; + qcom,bt-en-gpio = <&tlmm 65 0>; pinctrl-names = "wlan_en_active", "wlan_en_sleep"; pinctrl-0 = <&cnss_wlan_en_active>; pinctrl-1 = <&cnss_wlan_en_sleep>; From 8cf7986f3f815e5924cd5bbea5cc9652db1372b0 Mon Sep 17 00:00:00 2001 From: Mahesh Kumar Sharma Date: Thu, 24 Sep 2020 15:13:50 -0700 Subject: [PATCH 008/122] ARM: dts: msm: add WL_EN entry in BT node Add WL_EN GPIO entry in BT device tree node to handle AON LDO fully discharge issue. Change-Id: I526d42fb58fef7942280c4fc06ded5a47f7277dd --- bindings/bluetooth/btpower.txt | 2 ++ qcom/lahaina.dtsi | 1 + 2 files changed, 3 insertions(+) diff --git a/bindings/bluetooth/btpower.txt b/bindings/bluetooth/btpower.txt index 8b7d10bda475..391361eef201 100644 --- a/bindings/bluetooth/btpower.txt +++ b/bindings/bluetooth/btpower.txt @@ -11,6 +11,7 @@ Required properties: qcom,qca6390 qcom,qca6490 - qcom,bt-reset-gpio: GPIO pin to bring BT Controller out of reset + - qcom,wl-reset-gpio: GPIO pin for WL_EN toggle Optional properties: - qcom,bt-vdd-pa-supply: Bluetooth VDD PA regulator handle @@ -38,6 +39,7 @@ Example: pinctrl-names = "default"; pinctrl-0 = <&bt_en_sleep>; qcom,bt-reset-gpio = <&tlmm 21 0>; /* BT_EN */ + qcom,wl-reset-gpio = <&tlmm 64 0>; /* WL_EN */ qcom,bt-vdd-aon-supply = <&pm8150_s6>; qcom,bt-vdd-dig-supply = <&pm8009_s2>; qcom,bt-vdd-rfa1-supply = <&pm8150_s5>; diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 631f39833f2b..4bffa6192eea 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5619,6 +5619,7 @@ /* offset=(0xC8*6) + (0x10*2) */ qcom,tcs_offset_ipa = <0x4D0>; qcom,bt-reset-gpio = <&tlmm 65 0>; /* BT_EN */ + qcom,wl-reset-gpio = <&tlmm 64 0>; /* WL_EN */ qcom,bt-sw-ctrl-gpio = <&tlmm 153 0>; /* SW_CTRL */ qcom,bt-vdd-aon-supply = <&S11B>; qcom,bt-vdd-dig-supply = <&S11B>; From 19084b516c38e99169cad7f11ce82362f61819d4 Mon Sep 17 00:00:00 2001 From: Armaan Siddiqui Date: Wed, 16 Sep 2020 16:52:46 +0530 Subject: [PATCH 009/122] ARM: dts: msm: add change to support gsi wdi polling Change done to support dynamic allocation of wdi db addr. Change-Id: Ic38446a3d34165f13f5eccd222282a6780e51a6f --- bindings/platform/msm/ipa.txt | 2 ++ qcom/lahaina.dtsi | 1 + qcom/shima.dtsi | 1 + 3 files changed, 4 insertions(+) diff --git a/bindings/platform/msm/ipa.txt b/bindings/platform/msm/ipa.txt index 93d258aa0f08..9b8bc6cead21 100644 --- a/bindings/platform/msm/ipa.txt +++ b/bindings/platform/msm/ipa.txt @@ -74,6 +74,8 @@ memory allocation over a PCIe bridge using wdi-2.0 or not - qcom,ipa-wdi3-over-gsi: Boolean context flag to indicate whether using wdi-3.0 or not +- qcom,gsi_wdi_db_polling: Boolean context flag to indicate whether + using gsi wdi db polling or not - qcom,bandwidth-vote-for-ipa: Boolean context flag to indicate whether ipa clock voting is done by bandwidth voting via msm-bus-scale driver or not diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 4bffa6192eea..c57b755b6524 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -4633,6 +4633,7 @@ qcom,wan-use-skb-page; qcom,rmnet-ctl-enable; qcom,ipa-uc-holb-monitor; + qcom,gsi_wdi_db_polling; qcom,ipa-holb-monitor-poll-period = <5>; qcom,ipa-holb-monitor-max-cnt-wlan = <10>; qcom,ipa-holb-monitor-max-cnt-usb = <10>; diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index ca7fbbd667ae..8645ca9d6303 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3720,6 +3720,7 @@ qcom,wan-use-skb-page; qcom,rmnet-ctl-enable; qcom,ipa-uc-holb-monitor; + qcom,gsi_wdi_db_polling; qcom,ipa-holb-monitor-poll-period = <5>; qcom,ipa-holb-monitor-max-cnt-wlan = <10>; qcom,ipa-holb-monitor-max-cnt-usb = <10>; From 3d5c8dca4ad6ce5452943ab5d8966f44300ec1ee Mon Sep 17 00:00:00 2001 From: Chaitanya Pratapa Date: Wed, 14 Oct 2020 11:08:01 -0700 Subject: [PATCH 010/122] Revert "ARM: dts: msm: add change to support gsi wdi polling" This reverts commit 1b10670b1648112337a06dffe97ea49396efec2d. Change-Id: I9ea5c358fde6121449a4bdc1c7b952b3f946edad --- bindings/platform/msm/ipa.txt | 2 -- qcom/lahaina.dtsi | 1 - qcom/shima.dtsi | 1 - 3 files changed, 4 deletions(-) diff --git a/bindings/platform/msm/ipa.txt b/bindings/platform/msm/ipa.txt index 9b8bc6cead21..93d258aa0f08 100644 --- a/bindings/platform/msm/ipa.txt +++ b/bindings/platform/msm/ipa.txt @@ -74,8 +74,6 @@ memory allocation over a PCIe bridge using wdi-2.0 or not - qcom,ipa-wdi3-over-gsi: Boolean context flag to indicate whether using wdi-3.0 or not -- qcom,gsi_wdi_db_polling: Boolean context flag to indicate whether - using gsi wdi db polling or not - qcom,bandwidth-vote-for-ipa: Boolean context flag to indicate whether ipa clock voting is done by bandwidth voting via msm-bus-scale driver or not diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index c57b755b6524..4bffa6192eea 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -4633,7 +4633,6 @@ qcom,wan-use-skb-page; qcom,rmnet-ctl-enable; qcom,ipa-uc-holb-monitor; - qcom,gsi_wdi_db_polling; qcom,ipa-holb-monitor-poll-period = <5>; qcom,ipa-holb-monitor-max-cnt-wlan = <10>; qcom,ipa-holb-monitor-max-cnt-usb = <10>; diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 743f16064125..db2243b15543 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3720,7 +3720,6 @@ qcom,wan-use-skb-page; qcom,rmnet-ctl-enable; qcom,ipa-uc-holb-monitor; - qcom,gsi_wdi_db_polling; qcom,ipa-holb-monitor-poll-period = <5>; qcom,ipa-holb-monitor-max-cnt-wlan = <10>; qcom,ipa-holb-monitor-max-cnt-usb = <10>; From 05bf74720f136808efef2cb35f642aed9826ca0b Mon Sep 17 00:00:00 2001 From: Salendarsingh Gaud Date: Mon, 19 Oct 2020 15:07:15 +0530 Subject: [PATCH 011/122] Revert "ARM: dts: msm: enable mem_offline.bypass_send_msg for shima" This reverts commit 9efa409d6be1147859b9cf55566bb3755874df00. Change-Id: I4306067750dc2bf545517968ecc06c2173af4340 --- qcom/shima.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index db2243b15543..ca7fbbd667ae 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -480,7 +480,7 @@ }; chosen { - bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 mem_offline.bypass_send_msg=1"; + bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; }; soc: soc { }; From bbbc938f6458d69fab65a35e912f9ea787512416 Mon Sep 17 00:00:00 2001 From: Salendarsingh Gaud Date: Tue, 20 Oct 2020 12:10:58 +0530 Subject: [PATCH 012/122] Revert "ARM: dts: msm: Select 120Hz panel as default on 120Hz shima dts" This reverts commit 9e91b3dfefe8a159ad51c8ecf097892f1714be94. Change-Id: Ia6c03797b6ca881d5cf5dc586e305cfa162f482d --- qcom/shima-idp-120fps.dtsi | 4 ---- qcom/shima-idps-digital-mics-120fps.dtsi | 4 +--- 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/qcom/shima-idp-120fps.dtsi b/qcom/shima-idp-120fps.dtsi index f110f793bbeb..4f6732d3b955 100644 --- a/qcom/shima-idp-120fps.dtsi +++ b/qcom/shima-idp-120fps.dtsi @@ -2,7 +2,3 @@ &soc { }; - -&sde_dsi { - qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; -}; diff --git a/qcom/shima-idps-digital-mics-120fps.dtsi b/qcom/shima-idps-digital-mics-120fps.dtsi index 976bee956cd7..51ccf2dd48fd 100644 --- a/qcom/shima-idps-digital-mics-120fps.dtsi +++ b/qcom/shima-idps-digital-mics-120fps.dtsi @@ -3,6 +3,4 @@ &soc { }; -&sde_dsi { - qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; -}; + From 722fc401951ff8b50289952fac5fb7f60f63e7f8 Mon Sep 17 00:00:00 2001 From: Salendarsingh Gaud Date: Tue, 20 Oct 2020 12:11:39 +0530 Subject: [PATCH 013/122] Revert "ARM: dts: msm: Add device tree for Shima IDP/IDPS with 120fps platform" This reverts commit be7c6ea0ced249b525ee8e51dba1cd452b675726. Change-Id: Iabf58725a8b908c332db460b76b0159a5221d58d --- qcom/Makefile | 12 +++--------- qcom/shima-idp-120fps-overlay.dts | 11 ----------- qcom/shima-idp-120fps.dts | 10 ---------- qcom/shima-idp-120fps.dtsi | 4 ---- qcom/shima-idps-digital-mics-120fps-overlay.dts | 11 ----------- qcom/shima-idps-digital-mics-120fps.dts | 10 ---------- qcom/shima-idps-digital-mics-120fps.dtsi | 6 ------ 7 files changed, 3 insertions(+), 61 deletions(-) delete mode 100644 qcom/shima-idp-120fps-overlay.dts delete mode 100644 qcom/shima-idp-120fps.dts delete mode 100644 qcom/shima-idp-120fps.dtsi delete mode 100644 qcom/shima-idps-digital-mics-120fps-overlay.dts delete mode 100644 qcom/shima-idps-digital-mics-120fps.dts delete mode 100644 qcom/shima-idps-digital-mics-120fps.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 7ed2de109fca..1a1c6f058bd8 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -104,28 +104,22 @@ endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_SHIMA) += \ shima-rumi-overlay.dtbo \ - shima-idp-overlay.dtbo \ - shima-idp-120fps-overlay.dtbo \ + shima-idp-overlay.dtbo \ shima-atp-overlay.dtbo \ shima-qrd-overlay.dtbo \ - shima-idps-digital-mics-overlay.dtbo \ - shima-idps-digital-mics-120fps-overlay.dtbo + shima-idps-digital-mics-overlay.dtbo shima-rumi-overlay.dtbo-base := shima.dtb shima-idp-overlay.dtbo-base := shima.dtb -shima-idp-120fps-overlay.dtbo-base := shima.dtb shima-atp-overlay.dtbo-base := shima.dtb shima-qrd-overlay.dtbo-base := shima.dtb shima-idps-digital-mics-overlay.dtbo-base := shima.dtb -shima-idps-digital-mics-120fps-overlay.dtbo-base := shima.dtb else dtb-$(CONFIG_ARCH_SHIMA) += shima-rumi.dtb \ shima-idp.dtb \ - shima-idp-120fps.dtb \ shima-atp.dtb \ shima-qrd.dtb \ - shima-idps-digital-mics.dtb \ - shima-idps-digital-mics-120fps.dtb + shima-idps-digital-mics.dtb endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) diff --git a/qcom/shima-idp-120fps-overlay.dts b/qcom/shima-idp-120fps-overlay.dts deleted file mode 100644 index ef17b34fcdb7..000000000000 --- a/qcom/shima-idp-120fps-overlay.dts +++ /dev/null @@ -1,11 +0,0 @@ -/dts-v1/; -/plugin/; - -#include "shima-idp-120fps.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. Shima IDP + 120fps"; - compatible = "qcom,shima-idp", "qcom,shima", "qcom,idp"; - qcom,msm-id = <450 0x10000>; - qcom,board-id = <34 2>; -}; diff --git a/qcom/shima-idp-120fps.dts b/qcom/shima-idp-120fps.dts deleted file mode 100644 index 75ea5988bc79..000000000000 --- a/qcom/shima-idp-120fps.dts +++ /dev/null @@ -1,10 +0,0 @@ -/dts-v1/; - -#include "shima.dtsi" -#include "shima-idp-120fps.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. Shima IDP + 120fps"; - compatible = "qcom,shima-idp", "qcom,shima", "qcom,idp"; - qcom,board-id = <34 2>; -}; diff --git a/qcom/shima-idp-120fps.dtsi b/qcom/shima-idp-120fps.dtsi deleted file mode 100644 index 4f6732d3b955..000000000000 --- a/qcom/shima-idp-120fps.dtsi +++ /dev/null @@ -1,4 +0,0 @@ -#include "shima-idp.dtsi" - -&soc { -}; diff --git a/qcom/shima-idps-digital-mics-120fps-overlay.dts b/qcom/shima-idps-digital-mics-120fps-overlay.dts deleted file mode 100644 index b5c784b62fb4..000000000000 --- a/qcom/shima-idps-digital-mics-120fps-overlay.dts +++ /dev/null @@ -1,11 +0,0 @@ -/dts-v1/; -/plugin/; - -#include "shima-idps-digital-mics-120fps.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. Shima IDPS DIGITAL MICS + 120fps"; - compatible = "qcom,shima-idp", "qcom,shima", "qcom,idp"; - qcom,msm-id = <450 0x10000>; - qcom,board-id = <34 3>; -}; diff --git a/qcom/shima-idps-digital-mics-120fps.dts b/qcom/shima-idps-digital-mics-120fps.dts deleted file mode 100644 index f6773a9471eb..000000000000 --- a/qcom/shima-idps-digital-mics-120fps.dts +++ /dev/null @@ -1,10 +0,0 @@ -/dts-v1/; - -#include "shima.dtsi" -#include "shima-idps-digital-mics-120fps.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. Shima IDPS DIGITAL MICS + 120fps"; - compatible = "qcom,shima-idp", "qcom,shima", "qcom,idp"; - qcom,board-id = <34 3>; -}; diff --git a/qcom/shima-idps-digital-mics-120fps.dtsi b/qcom/shima-idps-digital-mics-120fps.dtsi deleted file mode 100644 index 51ccf2dd48fd..000000000000 --- a/qcom/shima-idps-digital-mics-120fps.dtsi +++ /dev/null @@ -1,6 +0,0 @@ -#include "shima-idps-digital-mics.dtsi" - -&soc { -}; - - From cef007570ab3f580aa6387b289444c34a65f3641 Mon Sep 17 00:00:00 2001 From: Salendarsingh Gaud Date: Tue, 20 Oct 2020 12:13:41 +0530 Subject: [PATCH 014/122] Revert "ARM: dts: msm: Add 144 fps touch support on shima target" This reverts commit 4e5aa7697f2419bf65f15e3aff9655cbc2756be1. Change-Id: If182c913da4a436483669f2fcb23a77f2844e93b --- qcom/shima-idp.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index a4be84ba4aee..d0a694ca961b 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -180,8 +180,7 @@ panel = <&dsi_r66451_amoled_cmd &dsi_r66451_amoled_video &dsi_r66451_amoled_60hz_video - &dsi_r66451_amoled_60hz_cmd - &dsi_r66451_amoled_144hz_cmd>; + &dsi_r66451_amoled_60hz_cmd>; focaltech,trusted-touch-mode = "vm_mode"; focaltech,touch-environment = "pvm"; From 52c533baec2429cbdc567d4f300f2e526953ec55 Mon Sep 17 00:00:00 2001 From: Salendarsingh Gaud Date: Wed, 21 Oct 2020 12:37:56 +0530 Subject: [PATCH 015/122] Revert "ARM: dts: msm: add WL_EN entry in BT node" This reverts commit 8cf7986f3f815e5924cd5bbea5cc9652db1372b0. Change-Id: Iaa158a90d09410c892fd61087302b47a433f07fa --- bindings/bluetooth/btpower.txt | 2 -- qcom/lahaina.dtsi | 1 - 2 files changed, 3 deletions(-) diff --git a/bindings/bluetooth/btpower.txt b/bindings/bluetooth/btpower.txt index 391361eef201..8b7d10bda475 100644 --- a/bindings/bluetooth/btpower.txt +++ b/bindings/bluetooth/btpower.txt @@ -11,7 +11,6 @@ Required properties: qcom,qca6390 qcom,qca6490 - qcom,bt-reset-gpio: GPIO pin to bring BT Controller out of reset - - qcom,wl-reset-gpio: GPIO pin for WL_EN toggle Optional properties: - qcom,bt-vdd-pa-supply: Bluetooth VDD PA regulator handle @@ -39,7 +38,6 @@ Example: pinctrl-names = "default"; pinctrl-0 = <&bt_en_sleep>; qcom,bt-reset-gpio = <&tlmm 21 0>; /* BT_EN */ - qcom,wl-reset-gpio = <&tlmm 64 0>; /* WL_EN */ qcom,bt-vdd-aon-supply = <&pm8150_s6>; qcom,bt-vdd-dig-supply = <&pm8009_s2>; qcom,bt-vdd-rfa1-supply = <&pm8150_s5>; diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 4bffa6192eea..631f39833f2b 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5619,7 +5619,6 @@ /* offset=(0xC8*6) + (0x10*2) */ qcom,tcs_offset_ipa = <0x4D0>; qcom,bt-reset-gpio = <&tlmm 65 0>; /* BT_EN */ - qcom,wl-reset-gpio = <&tlmm 64 0>; /* WL_EN */ qcom,bt-sw-ctrl-gpio = <&tlmm 153 0>; /* SW_CTRL */ qcom,bt-vdd-aon-supply = <&S11B>; qcom,bt-vdd-dig-supply = <&S11B>; From 32a9c8750f040f245e0bff260329988930bb0d79 Mon Sep 17 00:00:00 2001 From: Salendarsingh Gaud Date: Wed, 21 Oct 2020 12:38:35 +0530 Subject: [PATCH 016/122] Revert "ARM: dts: msm: Update CNSS node for BT GPIO config" This reverts commit 000ef13cbbc7a967d74fd9c270ca46c75c90fdab. Change-Id: Idb485055ea11b24498e99d5e28e561e5b551a809 --- bindings/cnss/cnss-wlan.txt | 3 --- qcom/lahaina.dtsi | 1 - 2 files changed, 4 deletions(-) diff --git a/bindings/cnss/cnss-wlan.txt b/bindings/cnss/cnss-wlan.txt index c1de42da51fb..02d983d74138 100644 --- a/bindings/cnss/cnss-wlan.txt +++ b/bindings/cnss/cnss-wlan.txt @@ -87,9 +87,6 @@ Optional properties: regulator used in internal power amplifier for QCA6490 - cnss-enable-self-recovery: Boolean property to enable self recovery when recovery is trigeered with reason link down. - - qcom,bt-en-gpio: QCA6490 requires synchronization for BT and WLAN GPIO - enable to resolve PMU power up issues. Provide BT GPIO using - this config param. Example: diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 631f39833f2b..9d358332bd39 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5355,7 +5355,6 @@ <0xb2e5510 0x690>; reg-names = "smmu_iova_ipa", "tcs_cmd"; wlan-en-gpio = <&tlmm 64 0>; - qcom,bt-en-gpio = <&tlmm 65 0>; pinctrl-names = "wlan_en_active", "wlan_en_sleep"; pinctrl-0 = <&cnss_wlan_en_active>; pinctrl-1 = <&cnss_wlan_en_sleep>; From ff02206a303d173e71df3827a6819bf97779af12 Mon Sep 17 00:00:00 2001 From: Salendarsingh Gaud Date: Wed, 21 Oct 2020 12:39:15 +0530 Subject: [PATCH 017/122] Revert "ARM: dts: msm: Vote for DDR BW for MPSS PIL on Lahaina" This reverts commit b8b5f0c1451124c2a1279f195f2a6a5bbe673d98. Change-Id: I8c757e0acd536e2a8e1284896bb8ffd9f48d6a2f --- qcom/lahaina.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 9d358332bd39..683d9a7fb4df 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -4423,8 +4423,6 @@ qcom,vdd_mss-uV-uA = ; qcom,proxy-reg-names = "vdd_cx", "vdd_mss"; - interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; - qcom,firmware-name = "modem"; memory-region = <&pil_modem_mem>; qcom,proxy-timeout-ms = <10000>; From 8bf88c65361ec595326c2e4e5b671888fd3a7541 Mon Sep 17 00:00:00 2001 From: Salendarsingh Gaud Date: Wed, 21 Oct 2020 12:40:29 +0530 Subject: [PATCH 018/122] Revert "ARM: dts: qcom: disable panic on single corruption" This reverts commit 2516aa0bf946a9595da587f9e58f3ecbdba5fd27. Change-Id: I3ea4a8efb47b885fb46a9806511fcb8960bdaad4 --- qcom/lahaina-v2.dtsi | 5 ----- qcom/lahaina.dtsi | 3 +-- 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/qcom/lahaina-v2.dtsi b/qcom/lahaina-v2.dtsi index 02c849e2dba2..f089e5cd052f 100644 --- a/qcom/lahaina-v2.dtsi +++ b/qcom/lahaina-v2.dtsi @@ -22,11 +22,6 @@ dynamic-power-coefficient = <760>; }; -&kryo_erp { - - /delete-property/ qcom,disable-panic-on-ce; -}; - &sde_dp { /delete-node/ qcom,pll-supply-entries; }; diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 683d9a7fb4df..182e5335c125 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -3237,12 +3237,11 @@ }; }; - kryo_erp: erp { + kryo-erp { compatible = "arm,arm64-kryo-cpu-erp"; interrupts = , ; interrupt-names = "l1-l2-faultirq","l3-scu-faultirq"; - qcom,disable-panic-on-ce; }; tcsr_mutex_block: syscon@1f40000 { From c511467d8dc38bf2676821b5ff26bcf516c186be Mon Sep 17 00:00:00 2001 From: Prakash Gupta Date: Mon, 14 Sep 2020 13:07:13 +0530 Subject: [PATCH 019/122] ARM: dts: msm: enable mem_offline.bypass_send_msg for shima Enable boot param mem_offline.bypass_send_msg to skip ending AOP message for mem offline/online requests. Change-Id: Ifb17d1057eca014c21edb10bff42913f9ee43b2b --- qcom/shima.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 5032f9039003..47ebe349af31 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -480,7 +480,7 @@ }; chosen { - bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 mem_offline.bypass_send_msg=1"; }; soc: soc { }; From 96bd9d4898774831838cc2867b7c788775b75864 Mon Sep 17 00:00:00 2001 From: Mohammed Siddiq Date: Tue, 20 Oct 2020 10:00:52 +0530 Subject: [PATCH 020/122] ARM: dts: msm: Add cnss-enable-self-recovery flag for shima Add cnss-enable-self-recovery flag for shima. It enables self recovery on link down detected by host driver. Change-Id: I2c66bcc0d9359dbb972b7180aa40eba404cb08d8 --- qcom/shima.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 47ebe349af31..42a9abe06f7b 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3497,6 +3497,7 @@ qcom,wlan-cbc-enabled; /* RPMH_PDC_WLAN_RF_TCS<6>_CMD<0> offset */ qcom,tcs_offset_int_pow_amp_vreg = <0x4B0>; + cnss-enable-self-recovery; vdd-wlan-aon-supply = <&S2C>; qcom,vdd-wlan-aon-config = <950000 952000 0 0 1>; From 016b42b7b7eadb0223fbf4973ec6b9610883b12e Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Tue, 20 Oct 2020 18:49:53 +0530 Subject: [PATCH 021/122] ARM: dts: qcom: Update skin and cx thermal mitigation config for SHIMA Add quiet-therm skin sensor thermal config for SHIMA with modem, cdsp and gpu as cooling devices based on latest recomondations. Update nspss-2 tsens sensor thermal config mitigation for SHIMA with cdsp, gpu and modem as cooling devices based on latest recomondations. Change-Id: I6a8cf412b80a6d071bd669fafed61aa72ba41b24 --- qcom/shima-qrd.dtsi | 93 ++++++++++++++++++++++++++++++++++++ qcom/shima-thermal.dtsi | 103 +++++++++++++--------------------------- 2 files changed, 126 insertions(+), 70 deletions(-) diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index ea9a65cd8f39..3c4d58ff97f2 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -197,6 +197,99 @@ qcom,wireless-fw-name = "idt9412.bin"; }; +&thermal_zones { + quiet-therm-step { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pmk8350_adc_tm PM8350_ADC7_AMUX_THM1_100K_PU>; + + trips { + quiet_gpu_trip: quiet-gpu-trip { + temperature = <45000>; + hysteresis = <0>; + type = "passive"; + }; + + quiet_cpu4_trip: quiet-cpu4-trip { + temperature = <46000>; + hysteresis = <0>; + type = "passive"; + }; + + quiet_cpu7_trip: quiet-cpu7-trip { + temperature = <48000>; + hysteresis = <0>; + type = "passive"; + }; + + quiet_cpu0_trip: quiet-cpu0-trip { + temperature = <50000>; + hysteresis = <0>; + type = "passive"; + }; + + quiet_cx_trip: quiet-cx-trip { + temperature = <55000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu-cdev0 { + trip = <&quiet_gpu_trip>; + /* throttle to 443000000Hz */ + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>; + }; + + gpu-cdev1 { + trip = <&quiet_cx_trip>; + /* throttle to 285000000Hz */ + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpufreq0-cdev { + trip = <&quiet_cpu0_trip>; + /* throttle to 1516800KHz */ + cooling-device = <&CPU0 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-7)>; + }; + + cpufreq4-cdev { + trip = <&quiet_cpu4_trip>; + /* throttle to 1651200KHz */ + cooling-device = <&CPU4 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-5)>; + }; + + cpufreq7-cdev { + trip = <&quiet_cpu7_trip>; + /* throttle to 1862400KHz */ + cooling-device = <&CPU7 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-5)>; + }; + + cdsp-cdev { + trip = <&quiet_cx_trip>; + cooling-device = <&cdsp_sw 5 5>; + }; + + modem-pa-cdev { + trip = <&quiet_cx_trip>; + cooling-device = <&modem_pa 3 3>; + }; + + modem-tj-cdev { + trip = <&quiet_cx_trip>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; +}; + &qupv3_se10_i2c { #address-cells = <1>; #size-cells = <0>; diff --git a/qcom/shima-thermal.dtsi b/qcom/shima-thermal.dtsi index abf3371998fc..73aa20666ae0 100644 --- a/qcom/shima-thermal.dtsi +++ b/qcom/shima-thermal.dtsi @@ -1254,18 +1254,12 @@ }; nspss-0-step { - polling-delay-passive = <10>; + polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&tsens1 3>; trips { - nspss0_trip0: nspss0-trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - nspss0_trip1: nspss0-trip1 { + nspss0_trip: nspss0-trip { temperature = <100000>; hysteresis = <5000>; type = "passive"; @@ -1273,49 +1267,37 @@ }; cooling-maps { - cdsp-cdev0 { - trip = <&nspss0_trip0>; - cooling-device = <&cdsp_sw THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - - cdsp-cdev1 { - trip = <&nspss0_trip1>; - cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + cdsp-cdev { + trip = <&nspss0_trip>; + cooling-device = <&cdsp_sw 5 5>; }; gpu_cdev { - trip = <&nspss0_trip1>; - cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1) - (THERMAL_MAX_LIMIT-1)>; + trip = <&nspss0_trip>; + /* throttle to 285000000Hz */ + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; modem-pa-cdev { - trip = <&nspss0_trip1>; + trip = <&nspss0_trip>; cooling-device = <&modem_pa 3 3>; }; modem-tj-cdev { - trip = <&nspss0_trip1>; + trip = <&nspss0_trip>; cooling-device = <&modem_tj 3 3>; }; }; }; nspss-1-step { - polling-delay-passive = <10>; + polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&tsens1 4>; trips { - nspss1_trip0: nspss1-trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - nspss1_trip1: nspss1-trip1 { + nspss1_trip: nspss1-trip { temperature = <100000>; hysteresis = <5000>; type = "passive"; @@ -1323,49 +1305,37 @@ }; cooling-maps { - cdsp-cdev0 { - trip = <&nspss1_trip0>; - cooling-device = <&cdsp_sw THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - - cdsp-cdev1 { - trip = <&nspss1_trip1>; - cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + cdsp-cdev { + trip = <&nspss1_trip>; + cooling-device = <&cdsp_sw 5 5>; }; gpu_cdev { - trip = <&nspss1_trip1>; - cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1) - (THERMAL_MAX_LIMIT-1)>; + trip = <&nspss1_trip>; + /* throttle to 285000000Hz */ + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; modem-pa-cdev { - trip = <&nspss1_trip1>; + trip = <&nspss1_trip>; cooling-device = <&modem_pa 3 3>; }; modem-tj-cdev { - trip = <&nspss1_trip1>; + trip = <&nspss1_trip>; cooling-device = <&modem_tj 3 3>; }; }; }; nspss-2-step { - polling-delay-passive = <10>; + polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&tsens1 5>; trips { - nspss2_trip0: nspss2-trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - nspss2_trip1: nspss2-trip1 { + nspss2_trip: nspss2-trip { temperature = <100000>; hysteresis = <5000>; type = "passive"; @@ -1373,34 +1343,27 @@ }; cooling-maps { - cdsp-cdev0 { - trip = <&nspss2_trip0>; - cooling-device = <&cdsp_sw THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - - cdsp-cdev1 { - trip = <&nspss2_trip1>; - cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + cdsp-cdev { + trip = <&nspss2_trip>; + cooling-device = <&cdsp_sw 5 5>; }; gpu_cdev { - trip = <&nspss2_trip1>; - cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1) - (THERMAL_MAX_LIMIT-1)>; + trip = <&nspss2_trip>; + /* throttle to 285000000Hz */ + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; modem-pa-cdev { - trip = <&nspss2_trip1>; + trip = <&nspss2_trip>; cooling-device = <&modem_pa 3 3>; }; modem-tj-cdev { - trip = <&nspss2_trip1>; + trip = <&nspss2_trip>; cooling-device = <&modem_tj 3 3>; }; }; }; }; - From ebd32282a2c6598838114d7bf630a567ecf7845b Mon Sep 17 00:00:00 2001 From: Vivek Pernamitta Date: Wed, 21 Oct 2020 20:53:23 +0530 Subject: [PATCH 022/122] Revert "ARM: dts: msm: Use PCIe_MSI for Shima" This reverts commit e506b909ef43f6464f97201f193f2197bc827346. Commit e506b909ef43f6 ("ARM: dts: msm: Use PCIe_MSI for Shima") There is MSI interrupts in PCIe DRV suspend state from device, which caused NOC error when host try to read MSI status register. Change-Id: Ia0393a2005bac508c0b4a43e41341507070ea3cd --- qcom/shima-pcie.dtsi | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/qcom/shima-pcie.dtsi b/qcom/shima-pcie.dtsi index fbe74ebfb44d..32573d6def76 100644 --- a/qcom/shima-pcie.dtsi +++ b/qcom/shima-pcie.dtsi @@ -33,7 +33,7 @@ 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; - msi-parent = <&pcie0_msi_snps>; + msi-parent = <&pcie0_msi>; perst-gpio = <&tlmm 94 0>; wake-gpio = <&tlmm 96 0>; @@ -194,15 +194,6 @@ }; }; - pcie0_msi_snps: qcom,pcie0_msi@a0000000 { - compatible = "qcom,pci-msi"; - msi-controller; - reg = <0xa0000000 0x0>; - interrupt-parent = <&intc>; - interrupts = ; - qcom,snps; - }; - pcie0_msi: qcom,pcie0_msi@17a10040 { compatible = "qcom,pci-msi"; msi-controller; From e59a34706d6ca35fabb37f165554f2076bf77a13 Mon Sep 17 00:00:00 2001 From: Ashwini Muduganti Date: Mon, 19 Oct 2020 13:37:52 +0800 Subject: [PATCH 023/122] ARM: dts: msm: Update masks in codec Fs clock sequence Update masks in codec Fs clock sequence on lahaina target. Change-Id: Ideae266d2c4b1f629dfdd8dbf149e4cae02f102a --- qcom/holi-audio-overlay.dtsi | 4 ++-- qcom/lahaina-audio-overlay.dtsi | 4 ++-- qcom/shima-audio-overlay.dtsi | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/qcom/holi-audio-overlay.dtsi b/qcom/holi-audio-overlay.dtsi index 987572a7db74..acdac6359715 100644 --- a/qcom/holi-audio-overlay.dtsi +++ b/qcom/holi-audio-overlay.dtsi @@ -11,8 +11,8 @@ #size-cells = <1>; bolero-clk-rsc-mngr { compatible = "qcom,bolero-clk-rsc-mngr"; - qcom,fs-gen-sequence = <0x3000 0x1>, - <0x3004 0x1>, <0x3080 0x2>; + qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>, + <0x3004 0x3 0x1>, <0x3080 0x2 0x2>; qcom,rx_mclk_mode_muxsel = <0x0A5640D8>; qcom,va_mclk_mode_muxsel = <0x0A7A0000>; clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk", diff --git a/qcom/lahaina-audio-overlay.dtsi b/qcom/lahaina-audio-overlay.dtsi index 4908e26696d8..1b50e92a9651 100644 --- a/qcom/lahaina-audio-overlay.dtsi +++ b/qcom/lahaina-audio-overlay.dtsi @@ -11,8 +11,8 @@ #size-cells = <1>; bolero-clk-rsc-mngr { compatible = "qcom,bolero-clk-rsc-mngr"; - qcom,fs-gen-sequence = <0x3000 0x1>, - <0x3004 0x1>, <0x3080 0x2>; + qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>, + <0x3004 0x3 0x1>, <0x3080 0x2 0x2>; qcom,rx_mclk_mode_muxsel = <0x033240D8>; qcom,wsa_mclk_mode_muxsel = <0x033220D8>; qcom,va_mclk_mode_muxsel = <0x033A0000>; diff --git a/qcom/shima-audio-overlay.dtsi b/qcom/shima-audio-overlay.dtsi index 5c44652dd529..b47233eb69e5 100644 --- a/qcom/shima-audio-overlay.dtsi +++ b/qcom/shima-audio-overlay.dtsi @@ -10,8 +10,8 @@ #size-cells = <1>; bolero-clk-rsc-mngr { compatible = "qcom,bolero-clk-rsc-mngr"; - qcom,fs-gen-sequence = <0x3000 0x1>, - <0x3004 0x1>, <0x3080 0x2>; + qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>, + <0x3004 0x3 0x1>, <0x3080 0x2 0x2>; qcom,rx_mclk_mode_muxsel = <0x033240D8>; qcom,wsa_mclk_mode_muxsel = <0x033220D8>; qcom,va_mclk_mode_muxsel = <0x033A0000>; From 44d156e63f9927efec475ccd9469a1935952e919 Mon Sep 17 00:00:00 2001 From: Amine Najahi Date: Mon, 19 Oct 2020 12:52:06 -0400 Subject: [PATCH 024/122] ARM: dts: msm: add trusted touch support in PVM for Lahaina Add trusted nodes to focaltech touch controller in primary VM. This will allow PVM to enable/disable secure touch when starting/stopping a TUI session. Change-Id: Ia977e8e5269b874a0ad685926d02aa5f3f8054bc --- qcom/lahaina-cdp.dtsi | 6 ++++++ qcom/lahaina-mtp.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/qcom/lahaina-cdp.dtsi b/qcom/lahaina-cdp.dtsi index c9b2da960900..4989e97dd77e 100644 --- a/qcom/lahaina-cdp.dtsi +++ b/qcom/lahaina-cdp.dtsi @@ -102,6 +102,12 @@ panel = <&dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; + + focaltech,trusted-touch-mode = "vm_mode"; + focaltech,touch-environment = "pvm"; + focaltech,trusted-touch-spi-irq = <566>; + focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>; + focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; }; atmel_mxt_ts@4a { diff --git a/qcom/lahaina-mtp.dtsi b/qcom/lahaina-mtp.dtsi index b896ca9f97d0..39f56296aed0 100644 --- a/qcom/lahaina-mtp.dtsi +++ b/qcom/lahaina-mtp.dtsi @@ -104,6 +104,12 @@ panel = <&dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; + + focaltech,trusted-touch-mode = "vm_mode"; + focaltech,touch-environment = "pvm"; + focaltech,trusted-touch-spi-irq = <566>; + focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>; + focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; }; }; From a7f3e11caf3356120b9c56a050d7b9a9511f70c6 Mon Sep 17 00:00:00 2001 From: Ashwini Muduganti Date: Fri, 23 Oct 2020 17:52:09 -0700 Subject: [PATCH 025/122] Revert "ARM: dts: msm: add trusted touch support in PVM for Lahaina" This reverts commit 22a6f6f89ccd918b8da6fccad538ee6d43f8b86f. Change-Id: I35e370e3a8b3095a3de8390b7c710d9dd1ba6080 --- qcom/lahaina-cdp.dtsi | 6 ------ qcom/lahaina-mtp.dtsi | 6 ------ 2 files changed, 12 deletions(-) diff --git a/qcom/lahaina-cdp.dtsi b/qcom/lahaina-cdp.dtsi index 4989e97dd77e..c9b2da960900 100644 --- a/qcom/lahaina-cdp.dtsi +++ b/qcom/lahaina-cdp.dtsi @@ -102,12 +102,6 @@ panel = <&dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; - - focaltech,trusted-touch-mode = "vm_mode"; - focaltech,touch-environment = "pvm"; - focaltech,trusted-touch-spi-irq = <566>; - focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>; - focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; }; atmel_mxt_ts@4a { diff --git a/qcom/lahaina-mtp.dtsi b/qcom/lahaina-mtp.dtsi index 39f56296aed0..b896ca9f97d0 100644 --- a/qcom/lahaina-mtp.dtsi +++ b/qcom/lahaina-mtp.dtsi @@ -104,12 +104,6 @@ panel = <&dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; - - focaltech,trusted-touch-mode = "vm_mode"; - focaltech,touch-environment = "pvm"; - focaltech,trusted-touch-spi-irq = <566>; - focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>; - focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; }; }; From be1a9ee2ae9f3bab8a92737013368163fb41432c Mon Sep 17 00:00:00 2001 From: "Isaac J. Manjarres" Date: Thu, 5 Nov 2020 15:01:53 -0800 Subject: [PATCH 026/122] dt-bindings: Document the qcom,power-always-on property for SMMU devices Document the qcom,power-always-on property for SMMU devices. This property specifies that the votes for power resources for an SMMU should always be maintained. Change-Id: I854e07b65d93ed78f9d3e270149d28ef6b599039 --- bindings/iommu/arm,smmu.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/bindings/iommu/arm,smmu.txt b/bindings/iommu/arm,smmu.txt index 9e3e515e4e96..29e79cddee88 100644 --- a/bindings/iommu/arm,smmu.txt +++ b/bindings/iommu/arm,smmu.txt @@ -182,6 +182,13 @@ conditions. that interconnect votes will be maintained irrespective of the CPUSS' state (awake or asleep). +- qcom,power-always-on: + Boolean property which indicates that votes for power + resources (i.e. regulators, clocks, buses) should + always be maintained. This is required when the latency + for the SMMU's operation is greatly increased by adding and + removing votes for power resources. + ** Deprecated properties: - mmu-masters (deprecated in favour of the generic "iommus" binding) : From c62dce705698d8428488691300e24e52f48777fa Mon Sep 17 00:00:00 2001 From: "Isaac J. Manjarres" Date: Thu, 5 Nov 2020 15:05:28 -0800 Subject: [PATCH 027/122] ARM: dts: msm: Enable qcom,power-always-on for GPU SMMUs on GKI targets The IOMMU page table management code is not optimal from a performance perspective in the GKI configuration, relative to the downstream implementation. When the GPU enters slumber, and requests the SMMU driver to unmap memory from the stage 1 page tables of the GPU. When unmapping memory, the SMMU driver must access the GPU SMMU's register space, so it must vote for power resources to access the TLB invalidation registers. When the GPU is in slumber, there aren't votes for the GPU SMMU's power resources, so the SMMU driver constantly ends up enabling/disabling the power resources, which takes a considerable amount of time. When paired with the suboptimal IOMMU page table management code, this leads to performance issues where the time taken to unmap memory is large. Thus, for all targets that support GKI, add the qcom,power-always-on property for the GPU SMMUs of these targets, to remove the latency incurred by having to enable/disable power resources in the GKI configuration. Change-Id: Id3237214e44c008871d01ec6652b08c4fb24e41c --- qcom/msm-arm-smmu-holi.dtsi | 1 + qcom/msm-arm-smmu-lahaina.dtsi | 1 + qcom/msm-arm-smmu-shima.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/qcom/msm-arm-smmu-holi.dtsi b/qcom/msm-arm-smmu-holi.dtsi index 20343e67832b..0b7fb0427195 100644 --- a/qcom/msm-arm-smmu-holi.dtsi +++ b/qcom/msm-arm-smmu-holi.dtsi @@ -7,6 +7,7 @@ #iommu-cells = <1>; qcom,use-3-lvl-tables; #global-interrupts = <2>; + qcom,power-always-on; qcom,regulator-names = "vdd"; vdd-supply = <&gpu_cx_gdsc>; clock-names = "gcc_gpu_memnoc_gfx_clk"; diff --git a/qcom/msm-arm-smmu-lahaina.dtsi b/qcom/msm-arm-smmu-lahaina.dtsi index de6054d5d612..f373834017d1 100644 --- a/qcom/msm-arm-smmu-lahaina.dtsi +++ b/qcom/msm-arm-smmu-lahaina.dtsi @@ -15,6 +15,7 @@ #address-cells = <1>; ranges; dma-coherent; + qcom,power-always-on; qcom,regulator-names = "vdd"; vdd-supply = <&gpu_cc_cx_gdsc>; diff --git a/qcom/msm-arm-smmu-shima.dtsi b/qcom/msm-arm-smmu-shima.dtsi index c9c71235d746..4867686e4486 100644 --- a/qcom/msm-arm-smmu-shima.dtsi +++ b/qcom/msm-arm-smmu-shima.dtsi @@ -15,6 +15,7 @@ #address-cells = <1>; ranges; dma-coherent; + qcom,power-always-on; qcom,regulator-names = "vdd"; vdd-supply = <&gpu_cx_gdsc>; From 380b07bae34f7e168c8a48e9598d6f12a4169c3e Mon Sep 17 00:00:00 2001 From: Salendarsingh Gaud Date: Mon, 9 Nov 2020 08:49:01 -0800 Subject: [PATCH 028/122] Revert "ARM: dts: msm: Add CX and MX SDPM configuration for SHIMA" This reverts commit 75d2c9ac76ef682404f1f3f4cb73007d0d4639e4. Change-Id: I1388d4813938934d9d4066cac95a9a5f80620dbd --- qcom/shima-thermal.dtsi | 146 ---------------------------------------- 1 file changed, 146 deletions(-) diff --git a/qcom/shima-thermal.dtsi b/qcom/shima-thermal.dtsi index 0568cabd69b5..4eaab6b23736 100644 --- a/qcom/shima-thermal.dtsi +++ b/qcom/shima-thermal.dtsi @@ -64,44 +64,6 @@ "msm_skin_therm"; }; }; - - mx_sdpm@0x00636000 { - compatible = "qcom,sdpm"; - reg = <0x00636000 0x1000>; - clock-names = "cam_cc_ipe", "video_cc_mvs0"; - clocks = <&camcc CAM_CC_IPE_0_CLK_SRC>, - <&videocc VIDEO_CC_MVS0_CLK_SRC>; - cam_cc_ipe-supply = <&cam_cc_ipe_0_gdsc>; - video_cc_mvs0-supply = <&video_cc_mvs0_gdsc>; - csr-id = <1 3>; - }; - - cx_sdpm@0x00634000 { - compatible = "qcom,sdpm"; - reg = <0x00634000 0x1000>; - clock-names = "cam_cc_csi0phytiimer", "video_cc_mvs0", "disp_cc_mdss_mdp"; - clocks = <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, - <&videocc VIDEO_CC_MVS0_CLK_SRC>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; - cam_cc_csi0phytiimer-supply = <&cam_cc_titan_top_gdsc>; - video_cc_mvs0-supply = <&video_cc_mvs0_gdsc>; - disp_cc_mdss-mdp-supply = <&disp_cc_mdss_core_gdsc>; - csr-id = <0 2 5>; - }; - - mx_pe: mx_rdpm_pe@0x00637000 { - compatible = "qcom,policy-engine"; - #thermal-sensor-cells = <0>; - reg = <0x00637000 0x1000>; - interrupts = ; - }; - - cx_pe: cx_rdpm_pe@0x00635000 { - compatible = "qcom,policy-engine"; - #thermal-sensor-cells = <0>; - reg = <0x00635000 0x1000>; - interrupts = ; - }; }; &cpufreq_hw { @@ -1412,112 +1374,4 @@ }; }; }; - - mx-pe-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&mx_pe>; - thermal-governor = "step_wise"; - trips { - mx_pe_config1: mx-pe-config1 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - - mx_pe_config2: mx-pe-config2 { - temperature = <2>; - hysteresis = <1>; - type = "passive"; - }; - - mx_pe_config3: mx-pe-config3 { - temperature = <3>; - hysteresis = <1>; - type = "passive"; - }; - }; - - cooling-maps { - mx_pe_cdev_1 { - trip = <&mx_pe_config1>; - cooling-device = <&cdsp_sw 0 0>; - }; - - mx_pe_cdev_2 { - trip = <&mx_pe_config2>; - cooling-device = <&msm_gpu 0 0>; - }; - - mx_pe_cdev_3 { - trip = <&mx_pe_config3>; - cooling-device = <&modem_tj 0 0>; - }; - }; - }; - - cx-pe-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&cx_pe>; - thermal-governor = "step_wise"; - trips { - cx_pe_config1: cx-pe-config1 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - - cx_pe_config2: cx-pe-config2 { - temperature = <2>; - hysteresis = <1>; - type = "passive"; - }; - - cx_pe_config3: cx-pe-config3 { - temperature = <3>; - hysteresis = <1>; - type = "passive"; - }; - - cx_pe_config4: cx-pe-config4 { - temperature = <4>; - hysteresis = <1>; - type = "passive"; - }; - - cx_pe_config5: cx-pe-config5 { - temperature = <5>; - hysteresis = <2>; - type = "passive"; - }; - }; - - cooling-maps { - cx_pe_cdev_1 { - trip = <&cx_pe_config1>; - cooling-device = <&cdsp_sw 0 0>; - }; - - cx_pe_cdev_2 { - trip = <&cx_pe_config2>; - cooling-device = <&cdsp_sw 0 0>; - }; - - cx_pe_cdev_3 { - trip = <&cx_pe_config3>; - cooling-device = <&cdsp_sw 0 0>; - }; - - cx_pe_cdev_4 { - trip = <&cx_pe_config4>; - cooling-device = <&modem_tj 0 0>; - }; - - cx_pe_cdev_5 { - trip = <&cx_pe_config5>; - cooling-device = <&cdsp_sw 0 0>; - }; - }; - }; }; From 7581de72182e6dd90426a1d883605d4000363e5d Mon Sep 17 00:00:00 2001 From: Salendarsingh Gaud Date: Fri, 20 Nov 2020 00:27:03 -0800 Subject: [PATCH 029/122] Revert "Revert "ARM: dts: msm: Add CX and MX SDPM configuration for SHIMA"" This reverts commit 380b07bae34f7e168c8a48e9598d6f12a4169c3e. Change-Id: I0a1f41a9c0c85a3102f5e60e0377073ba172f68d --- qcom/shima-thermal.dtsi | 146 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 146 insertions(+) diff --git a/qcom/shima-thermal.dtsi b/qcom/shima-thermal.dtsi index 4eaab6b23736..0568cabd69b5 100644 --- a/qcom/shima-thermal.dtsi +++ b/qcom/shima-thermal.dtsi @@ -64,6 +64,44 @@ "msm_skin_therm"; }; }; + + mx_sdpm@0x00636000 { + compatible = "qcom,sdpm"; + reg = <0x00636000 0x1000>; + clock-names = "cam_cc_ipe", "video_cc_mvs0"; + clocks = <&camcc CAM_CC_IPE_0_CLK_SRC>, + <&videocc VIDEO_CC_MVS0_CLK_SRC>; + cam_cc_ipe-supply = <&cam_cc_ipe_0_gdsc>; + video_cc_mvs0-supply = <&video_cc_mvs0_gdsc>; + csr-id = <1 3>; + }; + + cx_sdpm@0x00634000 { + compatible = "qcom,sdpm"; + reg = <0x00634000 0x1000>; + clock-names = "cam_cc_csi0phytiimer", "video_cc_mvs0", "disp_cc_mdss_mdp"; + clocks = <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&videocc VIDEO_CC_MVS0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + cam_cc_csi0phytiimer-supply = <&cam_cc_titan_top_gdsc>; + video_cc_mvs0-supply = <&video_cc_mvs0_gdsc>; + disp_cc_mdss-mdp-supply = <&disp_cc_mdss_core_gdsc>; + csr-id = <0 2 5>; + }; + + mx_pe: mx_rdpm_pe@0x00637000 { + compatible = "qcom,policy-engine"; + #thermal-sensor-cells = <0>; + reg = <0x00637000 0x1000>; + interrupts = ; + }; + + cx_pe: cx_rdpm_pe@0x00635000 { + compatible = "qcom,policy-engine"; + #thermal-sensor-cells = <0>; + reg = <0x00635000 0x1000>; + interrupts = ; + }; }; &cpufreq_hw { @@ -1374,4 +1412,112 @@ }; }; }; + + mx-pe-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&mx_pe>; + thermal-governor = "step_wise"; + trips { + mx_pe_config1: mx-pe-config1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + + mx_pe_config2: mx-pe-config2 { + temperature = <2>; + hysteresis = <1>; + type = "passive"; + }; + + mx_pe_config3: mx-pe-config3 { + temperature = <3>; + hysteresis = <1>; + type = "passive"; + }; + }; + + cooling-maps { + mx_pe_cdev_1 { + trip = <&mx_pe_config1>; + cooling-device = <&cdsp_sw 0 0>; + }; + + mx_pe_cdev_2 { + trip = <&mx_pe_config2>; + cooling-device = <&msm_gpu 0 0>; + }; + + mx_pe_cdev_3 { + trip = <&mx_pe_config3>; + cooling-device = <&modem_tj 0 0>; + }; + }; + }; + + cx-pe-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&cx_pe>; + thermal-governor = "step_wise"; + trips { + cx_pe_config1: cx-pe-config1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config2: cx-pe-config2 { + temperature = <2>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config3: cx-pe-config3 { + temperature = <3>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config4: cx-pe-config4 { + temperature = <4>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config5: cx-pe-config5 { + temperature = <5>; + hysteresis = <2>; + type = "passive"; + }; + }; + + cooling-maps { + cx_pe_cdev_1 { + trip = <&cx_pe_config1>; + cooling-device = <&cdsp_sw 0 0>; + }; + + cx_pe_cdev_2 { + trip = <&cx_pe_config2>; + cooling-device = <&cdsp_sw 0 0>; + }; + + cx_pe_cdev_3 { + trip = <&cx_pe_config3>; + cooling-device = <&cdsp_sw 0 0>; + }; + + cx_pe_cdev_4 { + trip = <&cx_pe_config4>; + cooling-device = <&modem_tj 0 0>; + }; + + cx_pe_cdev_5 { + trip = <&cx_pe_config5>; + cooling-device = <&cdsp_sw 0 0>; + }; + }; + }; }; From 397ddd4cefcdd301e4f545f833d9df5b4c281e8b Mon Sep 17 00:00:00 2001 From: Salendarsingh Gaud Date: Fri, 20 Nov 2020 00:38:21 -0800 Subject: [PATCH 030/122] Revert "ARM: dts: msm: enable mem_offline.bypass_send_msg for shima" This reverts commit c511467d8dc38bf2676821b5ff26bcf516c186be. Change-Id: Icc5f104c632094537d338cedad5a2ee61c10dc8b --- qcom/shima.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 25ded35c02ff..8246b5473d9d 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -480,7 +480,7 @@ }; chosen { - bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 mem_offline.bypass_send_msg=1"; + bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; }; soc: soc { }; From c5628cd289f4396e2d7eb788b2a38c09c974de5d Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Tue, 27 Oct 2020 14:00:23 +0530 Subject: [PATCH 031/122] ARM: dts: msm: Enable touch for Dual DSI video mode on shima Enable touch for Dual DSI video mode panel on shima target. Change-Id: I4d7316f34d6e9a2051213435bfe22a576e667ba7 --- qcom/shima-idp.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index dd34ac6cbd57..584af558244e 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -217,7 +217,8 @@ irq-gpios = <&tlmm 23 0x2008>; atmel,panel-coords = <0 0 479 799>; atmel,display-coords = <0 0 339 729>; - panel = <&dsi_sharp_qhd_plus_dsc_cmd>; + panel = <&dsi_sharp_qhd_plus_dsc_cmd + &dsi_sharp_qhd_plus_dsc_video>; }; }; From e72b3b032978e83c93875524f295aa2d1afb4813 Mon Sep 17 00:00:00 2001 From: NITHEESH MUTHURAJ Date: Tue, 13 Oct 2020 16:45:17 -0700 Subject: [PATCH 032/122] ARM: dts: msm: Add a new power level for supported devices Add speed bin node for efuse check and create speed bins to include TURBO_L2 on supported devices. Change-Id: I9ae248a599d53134b5e7b8a71ad109a34f1dfa0d --- qcom/lahaina-gpu.dtsi | 3 + qcom/lahaina-v2-gpu.dtsi | 435 ++++++++++++++++++++++++++++----------- qcom/lahaina.dtsi | 14 ++ 3 files changed, 330 insertions(+), 122 deletions(-) diff --git a/qcom/lahaina-gpu.dtsi b/qcom/lahaina-gpu.dtsi index 69b7ad4292ea..1fc038a7f72a 100644 --- a/qcom/lahaina-gpu.dtsi +++ b/qcom/lahaina-gpu.dtsi @@ -52,6 +52,9 @@ qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */ + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr"; interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; diff --git a/qcom/lahaina-v2-gpu.dtsi b/qcom/lahaina-v2-gpu.dtsi index 46b86a1604f0..194a286726f2 100644 --- a/qcom/lahaina-v2-gpu.dtsi +++ b/qcom/lahaina-v2-gpu.dtsi @@ -1,173 +1,364 @@ &msm_gpu { qcom,chipid = <0x06060001>; - qcom,initial-pwrlevel = <9>; + /delete-property/qcom,initial-pwrlevel; + /delete-node/qcom,gpu-pwrlevels; - /* Power levels */ - qcom,gpu-pwrlevels { + /* Power levels bins */ + qcom,gpu-pwrlevel-bins { + compatible="qcom,gpu-pwrlevel-bins"; #address-cells = <1>; #size-cells = <0>; - compatible = "qcom,gpu-pwrlevels"; + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + qcom,speed-bin = <0>; + qcom,initial-pwrlevel = <9>; - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <840000000>; - qcom,level = ; + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <840000000>; + qcom,level = ; - qcom,bus-freq-ddr7 = <11>; - qcom,bus-min-ddr7 = <11>; - qcom,bus-max-ddr7 = <11>; + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; - qcom,bus-freq-ddr8 = <11>; - qcom,bus-min-ddr8 = <11>; - qcom,bus-max-ddr8 = <11>; + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882a5ffd>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <778000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82a5ffd>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <738000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82a5ffd>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <676000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <10>; + qcom,bus-min-ddr8 = <10>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882b5ffd>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <608000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82b5ffd>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <540000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0xa82c5ffd>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <491000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82c5ffd>; + }; + + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82d5ffd>; + }; + + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <379000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882e5ffd>; + }; + + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <315000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <2>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <2>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882f5ffd>; + }; - qcom,acd-level = <0x882a5ffd>; }; - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <778000000>; - qcom,level = ; + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + qcom,speed-bin = <1>; + qcom,initial-pwrlevel = <10>; - qcom,bus-freq-ddr7 = <11>; - qcom,bus-min-ddr7 = <11>; - qcom,bus-max-ddr7 = <11>; + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <900000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <11>; - qcom,bus-min-ddr8 = <11>; - qcom,bus-max-ddr8 = <11>; + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; - qcom,acd-level = <0xa82a5ffd>; - }; + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <738000000>; - qcom,level = ; + qcom,acd-level = <0x882a5ffd>; + }; - qcom,bus-freq-ddr7 = <11>; - qcom,bus-min-ddr7 = <11>; - qcom,bus-max-ddr7 = <11>; + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <840000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <11>; - qcom,bus-min-ddr8 = <11>; - qcom,bus-max-ddr8 = <11>; + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; - qcom,acd-level = <0xa82a5ffd>; - }; + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <676000000>; - qcom,level = ; + qcom,acd-level = <0x882a5ffd>; + }; - qcom,bus-freq-ddr7 = <11>; - qcom,bus-min-ddr7 = <11>; - qcom,bus-max-ddr7 = <11>; + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <778000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <10>; - qcom,bus-min-ddr8 = <10>; - qcom,bus-max-ddr8 = <11>; + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; - qcom,acd-level = <0x882b5ffd>; - }; + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <608000000>; - qcom,level = ; + qcom,acd-level = <0xa82a5ffd>; + }; - qcom,bus-freq-ddr7 = <8>; - qcom,bus-min-ddr7 = <7>; - qcom,bus-max-ddr7 = <11>; + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <738000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <7>; - qcom,bus-min-ddr8 = <7>; - qcom,bus-max-ddr8 = <11>; + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; - qcom,acd-level = <0xa82b5ffd>; - }; + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <540000000>; - qcom,level = ; + qcom,acd-level = <0xa82a5ffd>; + }; - qcom,bus-freq-ddr7 = <8>; - qcom,bus-min-ddr7 = <7>; - qcom,bus-max-ddr7 = <10>; + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <676000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <7>; - qcom,bus-min-ddr8 = <7>; - qcom,bus-max-ddr8 = <9>; + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; - qcom,acd-level = <0xa82c5ffd>; - }; + qcom,bus-freq-ddr8 = <10>; + qcom,bus-min-ddr8 = <10>; + qcom,bus-max-ddr8 = <11>; - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <491000000>; - qcom,level = ; + qcom,acd-level = <0x882b5ffd>; + }; - qcom,bus-freq-ddr7 = <8>; - qcom,bus-min-ddr7 = <6>; - qcom,bus-max-ddr7 = <10>; + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <608000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <7>; - qcom,bus-min-ddr8 = <5>; - qcom,bus-max-ddr8 = <7>; + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <11>; - qcom,acd-level = <0xa82c5ffd>; - }; + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <11>; - qcom,gpu-pwrlevel@7 { - reg = <7>; - qcom,gpu-freq = <443000000>; - qcom,level = ; + qcom,acd-level = <0xa82b5ffd>; + }; - qcom,bus-freq-ddr7 = <8>; - qcom,bus-min-ddr7 = <6>; - qcom,bus-max-ddr7 = <10>; + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <540000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <7>; - qcom,bus-min-ddr8 = <5>; - qcom,bus-max-ddr8 = <7>; + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <10>; - qcom,acd-level = <0xa82d5ffd>; - }; + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <9>; - qcom,gpu-pwrlevel@8 { - reg = <8>; - qcom,gpu-freq = <379000000>; - qcom,level = ; + qcom,acd-level = <0xa82c5ffd>; + }; - qcom,bus-freq-ddr7 = <8>; - qcom,bus-min-ddr7 = <6>; - qcom,bus-max-ddr7 = <10>; + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <491000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <6>; - qcom,bus-min-ddr8 = <5>; - qcom,bus-max-ddr8 = <7>; + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; - qcom,acd-level = <0x882e5ffd>; - }; + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; - qcom,gpu-pwrlevel@9 { - reg = <9>; - qcom,gpu-freq = <315000000>; - qcom,level = ; + qcom,acd-level = <0xa82c5ffd>; + }; - qcom,bus-freq-ddr7 = <2>; - qcom,bus-min-ddr7 = <2>; - qcom,bus-max-ddr7 = <9>; + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <443000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <2>; - qcom,bus-min-ddr8 = <2>; - qcom,bus-max-ddr8 = <7>; + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; - qcom,acd-level = <0x882f5ffd>; + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82d5ffd>; + }; + + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <379000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882e5ffd>; + }; + + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <315000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <2>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <2>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882f5ffd>; + }; }; }; }; diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 53e480f7cdcd..e7a0171f6fc1 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5659,6 +5659,20 @@ qcom,use-ap-power-save; status = "disabled"; }; + + qfprom: qfprom@784000 { + compatible = "qcom,qfprom"; + reg = <0x784000 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + + gpu_speed_bin: gpu_speed_bin@17b { + reg = <0x17b 0x1>; + bits = <5 3>; + }; + }; }; #include "ipcc-test.dtsi" From 4b2fe3ca5ff334862625042727307af8dc3bbe33 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Wed, 11 Nov 2020 21:06:43 +0530 Subject: [PATCH 033/122] ARM: dts: msm: Remove display clock as client for CX SDPM for SHIMA Remove display clock as client for CX sdpm configuration for SHIMA as support not available. Change-Id: Ifabe6c7c5554179185e7a60cdc2dda0b3ec95619 --- qcom/shima-thermal.dtsi | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/qcom/shima-thermal.dtsi b/qcom/shima-thermal.dtsi index 0568cabd69b5..6a5999deec8b 100644 --- a/qcom/shima-thermal.dtsi +++ b/qcom/shima-thermal.dtsi @@ -79,14 +79,12 @@ cx_sdpm@0x00634000 { compatible = "qcom,sdpm"; reg = <0x00634000 0x1000>; - clock-names = "cam_cc_csi0phytiimer", "video_cc_mvs0", "disp_cc_mdss_mdp"; + clock-names = "cam_cc_csi0phytiimer", "video_cc_mvs0"; clocks = <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, - <&videocc VIDEO_CC_MVS0_CLK_SRC>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + <&videocc VIDEO_CC_MVS0_CLK_SRC>; cam_cc_csi0phytiimer-supply = <&cam_cc_titan_top_gdsc>; video_cc_mvs0-supply = <&video_cc_mvs0_gdsc>; - disp_cc_mdss-mdp-supply = <&disp_cc_mdss_core_gdsc>; - csr-id = <0 2 5>; + csr-id = <0 2>; }; mx_pe: mx_rdpm_pe@0x00637000 { From 28f2b92be1a7b8c630a819f2af7341d5a3de18d9 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Mon, 23 Nov 2020 15:16:14 +0530 Subject: [PATCH 034/122] ARM: dts: msm: Disable atmel_mxt_ts Change-Id: Ib9422dc1382657513f4f8809fda906ce0e7af859 --- qcom/shima-idp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index 584af558244e..728936ec43b3 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -219,6 +219,7 @@ atmel,display-coords = <0 0 339 729>; panel = <&dsi_sharp_qhd_plus_dsc_cmd &dsi_sharp_qhd_plus_dsc_video>; + status = "disabled"; }; }; From ca3755617ab971c20397d729eb95af143d1183db Mon Sep 17 00:00:00 2001 From: Deepak Kumar Date: Mon, 5 Oct 2020 17:04:04 +0530 Subject: [PATCH 035/122] ARM: dts: msm: Add new GPU DCVS corners for Shima GPU clock plan is updated to add new corners SVS_L0 and LOW_SVS_L1. This change updates the clock plan to add these new corners. Change-Id: Ic4fb5fddb838432a3e7b1418c72fd672783fe83a --- qcom/shima-gpu.dtsi | 88 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 79 insertions(+), 9 deletions(-) diff --git a/qcom/shima-gpu.dtsi b/qcom/shima-gpu.dtsi index 9766e11225f9..84349ff83d3e 100644 --- a/qcom/shima-gpu.dtsi +++ b/qcom/shima-gpu.dtsi @@ -143,7 +143,7 @@ #size-cells = <0>; qcom,speed-bin = <0>; - qcom,initial-pwrlevel = <5>; + qcom,initial-pwrlevel = <7>; qcom,gpu-pwrlevel@0 { reg = <0>; @@ -203,6 +203,20 @@ qcom,gpu-pwrlevel@4 { reg = <4>; + qcom,gpu-freq = <490000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <6>; + qcom,bus-max-ddr8 = <10>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <443000000>; qcom,level = ; @@ -215,8 +229,22 @@ qcom,bus-max-ddr8 = <9>; }; - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <365000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <6>; + qcom,bus-min-ddr7 = <5>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <9>; + }; + + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <285000000>; qcom,level = ; @@ -235,12 +263,12 @@ #size-cells = <0>; qcom,speed-bin = <105>; - qcom,initial-pwrlevel = <2>; + qcom,initial-pwrlevel = <3>; qcom,gpu-pwrlevel@0 { reg = <0>; qcom,gpu-freq = <490000000>; - qcom,level = ; + qcom,level = ; qcom,bus-freq-ddr7 = <11>; qcom,bus-min-ddr7 = <10>; @@ -267,6 +295,20 @@ qcom,gpu-pwrlevel@2 { reg = <2>; + qcom,gpu-freq = <365000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <6>; + qcom,bus-min-ddr7 = <5>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <9>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <285000000>; qcom,level = ; @@ -290,7 +332,7 @@ qcom,gpu-pwrlevel@0 { reg = <0>; qcom,gpu-freq = <365000000>; - qcom,level = ; + qcom,level = ; qcom,bus-freq-ddr7 = <10>; qcom,bus-min-ddr7 = <8>; @@ -321,7 +363,7 @@ #size-cells = <0>; qcom,speed-bin = <158>; - qcom,initial-pwrlevel = <5>; + qcom,initial-pwrlevel = <7>; qcom,gpu-pwrlevel@0 { reg = <0>; @@ -381,6 +423,20 @@ qcom,gpu-pwrlevel@4 { reg = <4>; + qcom,gpu-freq = <490000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <6>; + qcom,bus-max-ddr8 = <10>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <443000000>; qcom,level = ; @@ -393,8 +449,22 @@ qcom,bus-max-ddr8 = <9>; }; - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <365000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <6>; + qcom,bus-min-ddr7 = <5>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <9>; + }; + + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <285000000>; qcom,level = ; From b91a302bab1cdea3200c5c0e10b0cfd6723563eb Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Tue, 24 Nov 2020 12:22:27 +0530 Subject: [PATCH 036/122] ARM: dts: msm: Change micbias no for VA DMIC for shima Update micbias no for VA DMIC as per schematics. Change-Id: I5a3dcfb2ea2938e869da71a9c77c6fa507c47634 --- qcom/shima-idps-digital-mics.dtsi | 16 ++++++++-------- qcom/shima-qrd.dtsi | 8 ++++---- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/qcom/shima-idps-digital-mics.dtsi b/qcom/shima-idps-digital-mics.dtsi index c2cd1782aca2..4d7d74fc6275 100644 --- a/qcom/shima-idps-digital-mics.dtsi +++ b/qcom/shima-idps-digital-mics.dtsi @@ -24,13 +24,13 @@ "TX DMIC0", "Digital Mic0", "TX DMIC0", "MIC BIAS1", "TX DMIC1", "Digital Mic1", - "TX DMIC1", "MIC BIAS3", + "TX DMIC1", "MIC BIAS1", "TX DMIC2", "Digital Mic2", - "TX DMIC2", "MIC BIAS4", + "TX DMIC2", "MIC BIAS3", "TX DMIC3", "Digital Mic3", - "TX DMIC3", "MIC BIAS1", + "TX DMIC3", "MIC BIAS3", "TX DMIC4", "Digital Mic4", - "TX DMIC4", "MIC BIAS3", + "TX DMIC4", "MIC BIAS4", "TX DMIC5", "Digital Mic5", "TX DMIC5", "MIC BIAS4", "IN1_HPHL", "HPHL_OUT", @@ -58,10 +58,10 @@ "VA DMIC3", "Digital Mic3", "VA DMIC4", "Digital Mic4", "VA DMIC5", "Digital Mic5", - "VA DMIC0", "VA MIC BIAS3", - "VA DMIC1", "VA MIC BIAS3", - "VA DMIC2", "VA MIC BIAS1", - "VA DMIC3", "VA MIC BIAS1", + "VA DMIC0", "VA MIC BIAS1", + "VA DMIC1", "VA MIC BIAS1", + "VA DMIC2", "VA MIC BIAS3", + "VA DMIC3", "VA MIC BIAS3", "VA DMIC4", "VA MIC BIAS4", "VA DMIC5", "VA MIC BIAS4"; qcom,msm-mbhc-hphl-swh = <1>; diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index 512c64634168..4bbe7fd29657 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -447,10 +447,10 @@ "VA DMIC4", "Digital Mic4", "VA DMIC5", "Digital Mic5", "VA DMIC0", "VA MIC BIAS1", - "VA DMIC1", "VA MIC BIAS3", - "VA DMIC2", "VA MIC BIAS4", - "VA DMIC3", "VA MIC BIAS1", - "VA DMIC4", "VA MIC BIAS3", + "VA DMIC1", "VA MIC BIAS1", + "VA DMIC2", "VA MIC BIAS3", + "VA DMIC3", "VA MIC BIAS3", + "VA DMIC4", "VA MIC BIAS4", "VA DMIC5", "VA MIC BIAS4"; qcom,swr-dmic-max-devs = <0>; From 5c0b2065c165cacbe9c81ce5325e9d0bc3f4dbae Mon Sep 17 00:00:00 2001 From: Murali Nalajala Date: Tue, 1 Dec 2020 18:43:01 -0800 Subject: [PATCH 037/122] ARM: dts: msm: add new properties to guestvm node Add new properties to support cpu isolation and unisolation when the VM boot is start. Change-Id: I56a0a344230ef22e84a375431d0be2e0ed52a130 --- qcom/lahaina.dtsi | 2 ++ qcom/shima.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index e7a0171f6fc1..018fb04e79a3 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5191,6 +5191,8 @@ qcom,guestvm_loader { compatible = "qcom,guestvm-loader"; image_to_be_loaded = "trustedvm"; + qcom,reserved-cpus = <4 5>; + qcom,unisolate-timeout-ms = <8000>; }; ssc_sensors: qcom,msm-ssc-sensors { diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 903cd3b29602..a68f4003ac83 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -1174,6 +1174,8 @@ qcom,guestvm_loader { compatible = "qcom,guestvm-loader"; image_to_be_loaded = "trustedvm"; + qcom,reserved-cpus = <4 5>; + qcom,unisolate-timeout-ms = <8000>; }; From d4d09cfd83658a67eec6e20faf4a94a82116020b Mon Sep 17 00:00:00 2001 From: Neeraj Upadhyay Date: Wed, 2 Dec 2020 00:30:52 +0530 Subject: [PATCH 038/122] dt-bindings: Update bindings for guestvm-loader Update bindings for guestvm-loader with the new properties for CPU reservation. Change-Id: Ic3f0e9282524ecf9021ded582d67e80752156301 --- bindings/soc/qcom/qcom,guestvm-loader.yaml | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/bindings/soc/qcom/qcom,guestvm-loader.yaml b/bindings/soc/qcom/qcom,guestvm-loader.yaml index 10533eb7bb46..5c0f71be6b19 100644 --- a/bindings/soc/qcom/qcom,guestvm-loader.yaml +++ b/bindings/soc/qcom/qcom,guestvm-loader.yaml @@ -16,6 +16,13 @@ properties: image_to_be_loaded: $ref: /schemas/types.yaml#/definitions/string + qcom,reserved-cpus: + Value type: + Definition: should contain cpus reserved for guestvm + + qcom,unisolate-timeout-ms: + description: timeout, in ms, for unisolating reserved cpus. + required: - compatible - image_to_be_loaded @@ -25,5 +32,7 @@ examples: qcom,guestvm_loader { compatible = "qcom,guestvm-loader"; image_to_be_loaded = "trustedvm"; + qcom,reserved-cpus = <4 5>; + qcom,unisolate-timeout-ms = <8000>; }; -... \ No newline at end of file +... From 0768b7e8d6f56eb6fef797ce858d1f0af351d89e Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Sat, 17 Oct 2020 23:07:39 +0530 Subject: [PATCH 039/122] ARM: dts: msm: Add L3 snoop bw device on Lahaina Create L3 devfreq device on Lahaina to scale L3 based on snoop bandwidth. Change-Id: I6ac8f482bde014989bb578e2f052b8d8c5f77aaa --- qcom/shima.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index a68f4003ac83..dd0dd8c13df5 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -2305,6 +2305,28 @@ qcom,count-unit = <0x10000>; }; + snoop_l3_bw: qcom,snoop-l3-bw { + compatible = "qcom,devfreq-icc-l3bw"; + reg = <0x18590100 0xa0>; + reg-names = "ftbl-base"; + qcom,bus-width = <32>; + governor = "bw_hwmon"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_SHARED>; + }; + + snoop_l3_bwmon: qcom,snoop-l3-bwmon@9091000 { + compatible = "qcom,bimc-bwmon4"; + reg = <0x90b9100 0x300>, <0x90b9000 0x200>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&snoop_l3_bw>; + qcom,count-unit = <0x10000>; + }; + cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat { compatible = "qcom,devfreq-icc-l3"; reg = <0x18590100 0xa0>; From 023d89364f707788c950a86c4baf494014f3a48c Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Fri, 23 Oct 2020 15:15:33 +0530 Subject: [PATCH 040/122] ARM: dts: msm: Add cpu7 qos latfloor device on shima Create a qos latfloor device on shima target to cover compute bound workloads running on cpu7 above 2.0 GHz. Change-Id: I4a437076d9dfb0217d6b957d010e142509641069 --- qcom/shima.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index dd0dd8c13df5..6751e1524419 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -2488,6 +2488,13 @@ mboxes = <&qmp_aop 0>; }; + cpu7_cpu_ddr_qoslatfloor: qcom,cpu7-cpu-ddr-qoslatfloor { + compatible = "qcom,devfreq-qoslat"; + governor = "mem_latency"; + operating-points-v2 = <&qoslat_opp_table>; + mboxes = <&qmp_aop 0>; + }; + cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl { qcom,core-dev-table = < 300000 300000000 >, @@ -2757,6 +2764,16 @@ < 300000 1 >, < 3000000 2 >; }; + + cpu7_qoslatmon: qcom,cpu7-qoslatmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,target-dev = <&cpu7_cpu_ddr_qoslatfloor>; + qcom,cachemiss-ev = <0x1000>; + qcom,core-dev-table = + < 2169600 1 >, + < 2707200 2 >; + }; }; qcom,sps { From e3775e205c23eff9c3b7614574aa9d27002f41b1 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Fri, 27 Nov 2020 16:05:23 +0530 Subject: [PATCH 041/122] ARM: dts: qcom: use separate thermal zone names for modem pa for shima Use separate thermal zone node names for same modem pa sensors with different thermal governors. Otherwise second thermal zone node will override first one. Change-Id: I7e2d76eb13f9466b451639ab9cea8e8b43185c67 --- qcom/shima-thermal.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/shima-thermal.dtsi b/qcom/shima-thermal.dtsi index 8d8dacd4cef4..653a24778481 100644 --- a/qcom/shima-thermal.dtsi +++ b/qcom/shima-thermal.dtsi @@ -1387,7 +1387,7 @@ }; }; - modem-lte-sub6-pa1 { + modem-lte-pa1-step { polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "step_wise"; @@ -1431,7 +1431,7 @@ }; }; - modem-lte-sub6-pa2 { + modem-lte-pa2-step { polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "step_wise"; From b0891889b5eb004c7541bbd9a1e511e05e49bec2 Mon Sep 17 00:00:00 2001 From: Raghavendra Rao Ananta Date: Wed, 9 Dec 2020 13:18:31 -0800 Subject: [PATCH 042/122] ARM: dts: msm: Add support for SM8325 platforms Add support for SM8325 platform for the MSM and APQ variants. Change-Id: If5dbbbec42ca4b51067173fab69496ef504fac14 --- qcom/lahaina-v2.1.dtsi | 2 +- qcom/lahaina-v2.dtsi | 2 +- qcom/lahaina-vm-v2.dtsi | 2 +- qcom/lahaina-vm.dtsi | 2 +- qcom/lahaina.dtsi | 2 +- qcom/lahainap-v2.1.dtsi | 2 +- qcom/lahainap-v2.dtsi | 2 +- qcom/lahainap.dtsi | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/qcom/lahaina-v2.1.dtsi b/qcom/lahaina-v2.1.dtsi index 15408d1cb09f..05d6a478c305 100644 --- a/qcom/lahaina-v2.1.dtsi +++ b/qcom/lahaina-v2.1.dtsi @@ -3,7 +3,7 @@ / { model = "Qualcomm Technologies, Inc. Lahaina v2.1"; compatible = "qcom,lahaina"; - qcom,msm-id = <415 0x20001>, <456 0x20001>; + qcom,msm-id = <415 0x20001>, <456 0x20001>, <501 0x20001>; }; &pcie0 { diff --git a/qcom/lahaina-v2.dtsi b/qcom/lahaina-v2.dtsi index 02c849e2dba2..577504633359 100644 --- a/qcom/lahaina-v2.dtsi +++ b/qcom/lahaina-v2.dtsi @@ -3,7 +3,7 @@ / { model = "Qualcomm Technologies, Inc. Lahaina v2"; compatible = "qcom,lahaina"; - qcom,msm-id = <415 0x20000>, <456 0x20000>; + qcom,msm-id = <415 0x20000>, <456 0x20000>, <501 0x20000>; }; &CPU4 { diff --git a/qcom/lahaina-vm-v2.dtsi b/qcom/lahaina-vm-v2.dtsi index 6c5494ed784f..5cddeda9c901 100644 --- a/qcom/lahaina-vm-v2.dtsi +++ b/qcom/lahaina-vm-v2.dtsi @@ -3,5 +3,5 @@ / { model = "Qualcomm Technologies, Inc. Lahaina VM v2"; compatible = "qcom,lahaina"; - qcom,msm-id = <415 0x20000>; + qcom,msm-id = <415 0x20000>, <501 0x20000>; }; diff --git a/qcom/lahaina-vm.dtsi b/qcom/lahaina-vm.dtsi index f7b2d6708460..e59a59188cba 100644 --- a/qcom/lahaina-vm.dtsi +++ b/qcom/lahaina-vm.dtsi @@ -6,7 +6,7 @@ / { #address-cells = <0x2>; #size-cells = <0x2>; - qcom,msm-id = <415 0x10000>; + qcom,msm-id = <415 0x10000>, <501 0x10000>; interrupt-parent = <&vgic>; qcom-mem-buf { diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 4817d6aa6c38..ca5c7b37f8f7 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -27,7 +27,7 @@ / { model = "Qualcomm Technologies, Inc. Lahaina"; compatible = "qcom,lahaina"; - qcom,msm-id = <415 0x10000>, <456 0x10000>; + qcom,msm-id = <415 0x10000>, <456 0x10000>, <501 0x10000>; interrupt-parent = <&intc>; #address-cells = <2>; diff --git a/qcom/lahainap-v2.1.dtsi b/qcom/lahainap-v2.1.dtsi index 99f51cf73f39..67728c60f3b9 100644 --- a/qcom/lahainap-v2.1.dtsi +++ b/qcom/lahainap-v2.1.dtsi @@ -3,5 +3,5 @@ / { model = "Qualcomm Technologies, Inc. LahainaP v2.1"; compatible = "qcom,lahainap"; - qcom,msm-id = <439 0x20001>; + qcom,msm-id = <439 0x20001>, <502 0x20001>; }; diff --git a/qcom/lahainap-v2.dtsi b/qcom/lahainap-v2.dtsi index dd53c27b15b6..118618be4b7b 100644 --- a/qcom/lahainap-v2.dtsi +++ b/qcom/lahainap-v2.dtsi @@ -3,7 +3,7 @@ / { model = "Qualcomm Technologies, Inc. LahainaP v2"; compatible = "qcom,lahainap"; - qcom,msm-id = <439 0x20000>; + qcom,msm-id = <439 0x20000>, <502 0x20000>; }; &ipa_hw { diff --git a/qcom/lahainap.dtsi b/qcom/lahainap.dtsi index dee1f6a43c26..ae99b94831d3 100644 --- a/qcom/lahainap.dtsi +++ b/qcom/lahainap.dtsi @@ -3,7 +3,7 @@ / { model = "Qualcomm Technologies, Inc. LahainaP"; compatible = "qcom,lahainap"; - qcom,msm-id = <439 0x10000>; + qcom,msm-id = <439 0x10000>, <502 0x10000>; }; &ipa_hw { From c320a62c3f1dac8b9cd71b6cca7f4b29f6bd7211 Mon Sep 17 00:00:00 2001 From: Vishvanath Singh Date: Sun, 20 Dec 2020 05:09:17 -0800 Subject: [PATCH 043/122] Revert "ARM: dts: msm: Use PCIe_MSI for Shima" This reverts commit 6b84a80dde1ab6801f606e9f81cea291ef462da7. Change-Id: Ibcdd7e71fe4256c8e54f204827e179e18b752eb8 --- qcom/shima-pcie.dtsi | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/qcom/shima-pcie.dtsi b/qcom/shima-pcie.dtsi index e5909870ea8e..15f821e9ccce 100644 --- a/qcom/shima-pcie.dtsi +++ b/qcom/shima-pcie.dtsi @@ -33,7 +33,7 @@ 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; - msi-parent = <&pcie0_msi_snps>; + msi-parent = <&pcie0_msi>; perst-gpio = <&tlmm 94 0>; wake-gpio = <&tlmm 96 0>; @@ -203,15 +203,6 @@ }; }; - pcie0_msi_snps: qcom,pcie0_msi@a0000000 { - compatible = "qcom,pci-msi"; - msi-controller; - reg = <0xa0000000 0x0>; - interrupt-parent = <&intc>; - interrupts = ; - qcom,snps; - }; - pcie0_msi: qcom,pcie0_msi@17a10040 { compatible = "qcom,pci-msi"; msi-controller; From 837c3ab345062933211876de2f6bb00b5514cf2a Mon Sep 17 00:00:00 2001 From: Prakash Gupta Date: Wed, 6 Jan 2021 11:16:29 +0530 Subject: [PATCH 044/122] ARM: dts: msm: remove kgsl smmu interconnect node for Lahaina Remove kgsl smmu interconnect node. For TCU config register access we shouldn't required DDR path votes. KGSL smmu already votes for clock and regulator so it should be fine. Change-Id: I7ecf688aeafe07c6a844220b217a5f49380b6795 --- qcom/msm-arm-smmu-lahaina.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/qcom/msm-arm-smmu-lahaina.dtsi b/qcom/msm-arm-smmu-lahaina.dtsi index f373834017d1..862492a73ce7 100644 --- a/qcom/msm-arm-smmu-lahaina.dtsi +++ b/qcom/msm-arm-smmu-lahaina.dtsi @@ -35,8 +35,6 @@ "gpu_cc_hub_cx_int_clk", "gpu_cc_hub_aon_clk"; - interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>; - qcom,actlr = /* All CBs of GFX: +15 deep PF */ <0x0 0x400 0x32B>, From 57ad3c075ad8aaac5bc887afef6d467ef9edf9ff Mon Sep 17 00:00:00 2001 From: Vishvanath Singh Date: Thu, 7 Jan 2021 23:19:25 -0800 Subject: [PATCH 045/122] Revert "ARM: dts: msm: Add camera device tree inclusions for Yupik camera" This reverts commit d8fbed3b75ea4cbe70226657a6caacd5e621171a. Change-Id: I8d11cb56316418d9c46a3fba3e8497ec5fe84e01 --- qcom/yupik.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index df4341dc8f48..cae3dadb455b 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -3857,7 +3857,6 @@ #include "msm-arm-smmu-yupik.dtsi" #include "yupik-qupv3.dtsi" #include "yupik-audio.dtsi" -#include "camera/yupik-camera.dtsi" #include "msm-rdbg.dtsi" #include "yupik-gpu.dtsi" #include "yupik-thermal.dtsi" From 5c71f4bac831a49ef1543b936281386fd0798009 Mon Sep 17 00:00:00 2001 From: Ayush Kumar Date: Mon, 23 Nov 2020 17:13:48 +0530 Subject: [PATCH 046/122] ARM: dts: msm: Add camera device tree inclusions for Yupik camera Include camera device tree nodes to enable camera functionality on Yupik target Change-Id: I3fcbd3eb89ae3363f01943a85f29190659af644c --- qcom/yupik.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index cae3dadb455b..df4341dc8f48 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -3857,6 +3857,7 @@ #include "msm-arm-smmu-yupik.dtsi" #include "yupik-qupv3.dtsi" #include "yupik-audio.dtsi" +#include "camera/yupik-camera.dtsi" #include "msm-rdbg.dtsi" #include "yupik-gpu.dtsi" #include "yupik-thermal.dtsi" From d37231e1edd8d081985da2b24c85973b930c766c Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Mon, 1 Feb 2021 16:37:13 +0530 Subject: [PATCH 047/122] ARM: dts: msm: Disable haptics for yupik atp Disable haptics for yupik atp and enable both wsa. Change-Id: I0fcfa71931aabcfdf075a765d287a1edfbd1b8a5 --- qcom/yupik-atp.dtsi | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/qcom/yupik-atp.dtsi b/qcom/yupik-atp.dtsi index 45631c00e0c6..e92d835c7d4d 100644 --- a/qcom/yupik-atp.dtsi +++ b/qcom/yupik-atp.dtsi @@ -326,11 +326,6 @@ status = "disabled"; }; -&swr_haptics { - status = "okay"; - swr-slave-supply = <&hap_swr_slave_reg>; -}; - &yupik_snd { qcom,model = "lahaina-yupikqrd-snd-card"; qcom,audio-routing = @@ -357,7 +352,6 @@ "IN1_HPHL", "HPHL_OUT", "IN2_HPHR", "HPHR_OUT", "IN3_AUX", "AUX_OUT", - "HAP_IN", "PCM_OUT", "WSA SRC0_INP", "SRC0", "WSA_TX DEC0_INP", "TX DEC0 MUX", "WSA_TX DEC1_INP", "TX DEC1 MUX", @@ -390,11 +384,13 @@ qcom,msm-mbhc-gnd-swh = <1>; asoc-codec = <&stub_codec>, <&bolero>, - <&wcd938x_codec>, <&swr_haptics>, - <&wsa883x_0222>; + <&wcd938x_codec>, + <&wsa883x_0222>, + <&ext_disp_audio_codec>; asoc-codec-names = "msm-stub-codec.1", "bolero_codec", - "wcd938x_codec", "swr-haptics", - "wsa-codec2"; + "wcd938x_codec", + "wsa-codec2", + "msm-ext-disp-audio-codec-rx"; qcom,wsa-max-devs = <1>; qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>, <&bolero>; From 74a4e6c5a340ecd76dda36503948d0d6936e0309 Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Thu, 21 Jan 2021 13:02:56 +0530 Subject: [PATCH 048/122] ARM: dts: msm: Vote vccq2 via vccq to support GKI vccq2 is supplied by eLDO and this eLDO is controlled via L9B regulator which only supports max 1.2V but since for gki build QTI flag is disabled vote for vccq2 regulator is taking default values from driver and not from dt. Hence use vccq to vote on L9B to enable eLDO for UFS2.2 devices since L9B is common regulator as both vccq & vccq2. Change-Id: Icf8c9f169d693a6dad608c16baa9ed9666905430 --- qcom/yupik-atp.dtsi | 26 ++++++++++++++++---------- qcom/yupik-idp.dtsi | 26 ++++++++++++++++---------- qcom/yupik-qrd.dtsi | 26 ++++++++++++++++---------- 3 files changed, 48 insertions(+), 30 deletions(-) diff --git a/qcom/yupik-atp.dtsi b/qcom/yupik-atp.dtsi index 45631c00e0c6..cbac0b4584c9 100644 --- a/qcom/yupik-atp.dtsi +++ b/qcom/yupik-atp.dtsi @@ -70,20 +70,26 @@ vcc-low-voltage-sup; vcc-max-microamp = <800000>; + /* + * Yupik target supports both UFS2.2 & UFS3.1, here + * vccq2 is supplied via eLDO, and that is controlled via + * L9B which supports a max voltage of 1.2V, but eLDO would + * supply 1.8V. and same L9B acts as vccq voltage for UFS3.1 + * devices. + * Here L9B can max support for 1.2V but UFS GKI driver code + * votes for 1.8V, which is leading to failure from pmic + * regulator. + * + * Now since vccq and control of eLDO are common that is L9B + * we can use vccq vote as control of eLDO for vccq2. + * Hence vccq entries shall be used for both type of UFS + * devices only. And vccq entries should not be changed/removed + * for any design alteration. + */ vccq-supply = <&L9B>; vccq-max-microamp = <900000>; vccq-min-microamp = <10000>; - /* - * Vccq2 voltage level should be 1.8V but in case of yupik - * vccq2 is supplied via eLDO, and that is controlled via - * L9B which supports a max voltage of 1.2V, but eLDO would - * supply 1.8V. - */ - vccq2-supply = <&L9B>; - vccq2-voltage-level = <1200000 1200000>; - vccq2-max-microamp = <800000>; - qcom,vddp-ref-clk-supply = <&L9B>; qcom,vddp-ref-clk-max-microamp = <100>; diff --git a/qcom/yupik-idp.dtsi b/qcom/yupik-idp.dtsi index 291879aeb65d..7b366fdab1b2 100644 --- a/qcom/yupik-idp.dtsi +++ b/qcom/yupik-idp.dtsi @@ -71,20 +71,26 @@ vcc-low-voltage-sup; vcc-max-microamp = <800000>; + /* + * Yupik target supports both UFS2.2 & UFS3.1, here + * vccq2 is supplied via eLDO, and that is controlled via + * L9B which supports a max voltage of 1.2V, but eLDO would + * supply 1.8V. and same L9B acts as vccq voltage for UFS3.1 + * devices. + * Here L9B can max support for 1.2V but UFS GKI driver code + * votes for 1.8V, which is leading to failure from pmic + * regulator. + * + * Now since vccq and control of eLDO are common that is L9B + * we can use vccq vote as control of eLDO for vccq2. + * Hence vccq entries shall be used for both type of UFS + * devices only. And vccq entries should not be changed/removed + * for any design alteration. + */ vccq-supply = <&L9B>; vccq-max-microamp = <900000>; vccq-min-microamp = <10000>; - /* - * Vccq2 voltage level should be 1.8V but in case of yupik - * vccq2 is supplied via eLDO, and that is controlled via - * L9B which supports a max voltage of 1.2V, but eLDO would - * supply 1.8V. - */ - vccq2-supply = <&L9B>; - vccq2-voltage-level = <1200000 1200000>; - vccq2-max-microamp = <800000>; - qcom,vddp-ref-clk-supply = <&L9B>; qcom,vddp-ref-clk-max-microamp = <100>; diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index 1739bd0ccf27..c3d55c5624f6 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -72,20 +72,26 @@ vcc-low-voltage-sup; vcc-max-microamp = <800000>; + /* + * Yupik target supports both UFS2.2 & UFS3.1, here + * vccq2 is supplied via eLDO, and that is controlled via + * L9B which supports a max voltage of 1.2V, but eLDO would + * supply 1.8V. and same L9B acts as vccq voltage for UFS3.1 + * devices. + * Here L9B can max support for 1.2V but UFS GKI driver code + * votes for 1.8V, which is leading to failure from pmic + * regulator. + * + * Now since vccq and control of eLDO are common that is L9B + * we can use vccq vote as control of eLDO for vccq2. + * Hence vccq entries shall be used for both type of UFS + * devices only. And vccq entries should not be changed/removed + * for any design alteration. + */ vccq-supply = <&L9B>; vccq-max-microamp = <900000>; vccq-min-microamp = <10000>; - /* - * Vccq2 voltage level should be 1.8V but in case of yupik - * vccq2 is supplied via eLDO, and that is controlled via - * L9B which supports a max voltage of 1.2V, but eLDO would - * supply 1.8V. - */ - vccq2-supply = <&L9B>; - vccq2-voltage-level = <1200000 1200000>; - vccq2-max-microamp = <800000>; - qcom,vddp-ref-clk-supply = <&L9B>; qcom,vddp-ref-clk-max-microamp = <100>; From a1775b9d5263a5f23f2858f81dc697d971bb9508 Mon Sep 17 00:00:00 2001 From: Minghao Zhang Date: Fri, 5 Feb 2021 17:23:54 +0800 Subject: [PATCH 049/122] ARM: dts: qcom: change ldo for fan controller on Lahaina HHG Change ldo to L7J and voltage/load range for fan controller. And add fan controller to cooling device and add thermal mitigation rules. Change-Id: I81a4edbc50aa94250483910fd846493dd6a0711c --- qcom/lahaina-hhg.dtsi | 217 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 207 insertions(+), 10 deletions(-) diff --git a/qcom/lahaina-hhg.dtsi b/qcom/lahaina-hhg.dtsi index b19e06ee65ff..afeeceecda68 100644 --- a/qcom/lahaina-hhg.dtsi +++ b/qcom/lahaina-hhg.dtsi @@ -60,9 +60,9 @@ }; }; -&pm8008i_l7 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3400000>; +&pm8008j_l7 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3100000>; }; &soc { @@ -83,17 +83,214 @@ fancontroller: max31760@50 { compatible = "maxim,max31760"; reg = <0x50>; - maxim,vdd-supply = <&pm8008i_l7>; + #cooling-cells = <2>; + maxim,vdd-supply = <&pm8008j_l7>; regulator-names = "maxim,vdd"; - maxim,vdd-max-uv = <3400000>; - maxim,vdd-min-uv = <3300000>; - maxim,vdd-load-ua = <300000>; maxim,vcca-supply = <&pm8350_s10>; - maxim,vcca-max-uv = <1800000>; - maxim,vcca-min-uv = <1800000>; - maxim,vcca-load-ua = <600000>; maxim,fan_en_gpio = <&tlmm 48 0x00>; status = "ok"; }; }; }; + +&thermal_zones { + cpu-1-6-step { + trips { + fan_cpu16_config0: fan-cpu16-config0 { + temperature = <50000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_cpu16_config1: fan-cpu16-config1 { + temperature = <65000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_cpu16_config2: fan-cpu16-config2 { + temperature = <80000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_cpu16_config3: fan-cpu16-config3 { + temperature = <90000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + fan_cdev_0 { + trip = <&fan_cpu16_config0>; + cooling-device = <&fancontroller 0 1>; + }; + + fan_cdev_1 { + trip = <&fan_cpu16_config1>; + cooling-device = <&fancontroller 1 2>; + }; + + fan_cdev_2 { + trip = <&fan_cpu16_config2>; + cooling-device = <&fancontroller 2 3>; + }; + + fan_cdev_3 { + trip = <&fan_cpu16_config3>; + cooling-device = <&fancontroller 3 4>; + }; + }; + }; + + cpu-1-7-step { + trips { + fan_cpu17_config0: fan-cpu17-config0 { + temperature = <50000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_cpu17_config1: fan-cpu17-config1 { + temperature = <65000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_cpu17_config2: fan-cpu17-config2 { + temperature = <80000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_cpu17_config3: fan-cpu17-config3 { + temperature = <90000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + fan_cdev_0 { + trip = <&fan_cpu17_config0>; + cooling-device = <&fancontroller 0 1>; + }; + + fan_cdev_1 { + trip = <&fan_cpu17_config1>; + cooling-device = <&fancontroller 1 2>; + }; + + fan_cdev_2 { + trip = <&fan_cpu17_config2>; + cooling-device = <&fancontroller 2 3>; + }; + + fan_cdev_3 { + trip = <&fan_cpu17_config3>; + cooling-device = <&fancontroller 3 4>; + }; + }; + }; + + gpuss-0-step { + trips { + fan_gpuss0_config0: fan-gpuss0-config0 { + temperature = <50000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_gpuss0_config1: fan-gpuss0-config1 { + temperature = <65000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_gpuss0_config2: fan-gpuss0-config2 { + temperature = <80000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_gpuss0_config3: fan-gpuss0-config3 { + temperature = <90000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + fan_cdev_0 { + trip = <&fan_gpuss0_config0>; + cooling-device = <&fancontroller 0 1>; + }; + + fan_cdev_1 { + trip = <&fan_gpuss0_config1>; + cooling-device = <&fancontroller 1 2>; + }; + + fan_cdev_2 { + trip = <&fan_gpuss0_config2>; + cooling-device = <&fancontroller 2 3>; + }; + + fan_cdev_3 { + trip = <&fan_gpuss0_config3>; + cooling-device = <&fancontroller 3 4>; + }; + }; + }; + + gpuss-1-step { + trips { + fan_gpuss1_config0: fan-gpuss1-config0 { + temperature = <50000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_gpuss1_config1: fan-gpuss1-config1 { + temperature = <65000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_gpuss1_config2: fan-gpuss1-config2 { + temperature = <80000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_gpuss1_config3: fan-gpuss1-config3 { + temperature = <90000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + fan_cdev_0 { + trip = <&fan_gpuss1_config0>; + cooling-device = <&fancontroller 0 1>; + }; + + fan_cdev_1 { + trip = <&fan_gpuss1_config1>; + cooling-device = <&fancontroller 1 2>; + }; + + fan_cdev_2 { + trip = <&fan_gpuss1_config2>; + cooling-device = <&fancontroller 2 3>; + }; + + fan_cdev_3 { + trip = <&fan_gpuss1_config3>; + cooling-device = <&fancontroller 3 4>; + }; + }; + }; +}; From 2f221a10e5145eca11e4ae355ccbfb145670c5ab Mon Sep 17 00:00:00 2001 From: Jing Li Date: Thu, 7 Jan 2021 11:13:40 +0800 Subject: [PATCH 050/122] ARM: dts: msm: Add camera device tree inclusions for lahaina hhg Need update camera sensor node for lahaina hhg platform. Change-Id: I51bbd415be7ae34bd30744e982fcaa05adbc8736 --- qcom/lahaina-hhg.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/lahaina-hhg.dtsi b/qcom/lahaina-hhg.dtsi index b19e06ee65ff..3096c4320724 100644 --- a/qcom/lahaina-hhg.dtsi +++ b/qcom/lahaina-hhg.dtsi @@ -1,4 +1,5 @@ #include "lahaina-hdk.dtsi" +#include "camera/lahaina-camera-sensor-hhg.dtsi" &wsa883x_0222 { status = "ok"; From c3ff15503bbeecff0022c06ea711d95c570f40fb Mon Sep 17 00:00:00 2001 From: Linyu Yuan Date: Tue, 26 Jan 2021 16:08:23 +0800 Subject: [PATCH 051/122] ARM: dts: qcom: enable suspend for Lahaina HHG add qcom,ignore-wakeup-src-in-hostmode property. Change-Id: Ie79f00f5695e12ecbaca39282f80e5d2569afafa --- qcom/lahaina-hhg.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/lahaina-hhg.dtsi b/qcom/lahaina-hhg.dtsi index 045d3346cbc5..1786428cdee4 100644 --- a/qcom/lahaina-hhg.dtsi +++ b/qcom/lahaina-hhg.dtsi @@ -94,6 +94,10 @@ }; }; +&usb1 { + qcom,ignore-wakeup-src-in-hostmode; +}; + &thermal_zones { cpu-1-6-step { trips { From 6f1552d3b51ea38dbb615dd927d1c10ad50a67aa Mon Sep 17 00:00:00 2001 From: Vishvanath Singh Date: Mon, 8 Feb 2021 17:04:25 +0530 Subject: [PATCH 052/122] Fixing space issue to avoid diff with mainline Change-Id: I0bcda5042d5f21466b04991f54388177db0c3e9a --- qcom/lahaina-hhg.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/lahaina-hhg.dtsi b/qcom/lahaina-hhg.dtsi index 1786428cdee4..701d72476416 100644 --- a/qcom/lahaina-hhg.dtsi +++ b/qcom/lahaina-hhg.dtsi @@ -95,7 +95,7 @@ }; &usb1 { - qcom,ignore-wakeup-src-in-hostmode; + qcom,ignore-wakeup-src-in-hostmode; }; &thermal_zones { From 4b08a1433c4715e9c2dc61af61d40b57b01e5460 Mon Sep 17 00:00:00 2001 From: NITHEESH MUTHURAJ Date: Tue, 19 Jan 2021 21:59:54 -0800 Subject: [PATCH 053/122] ARM: dts: msm: Add Additional speed bins for supported devices Add new speed bins nodes to support new efuse values. Change-Id: Idf5061579c5c3777859bd3a31aa2ee41e1e14faf --- qcom/lahaina-v2-gpu.dtsi | 517 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 517 insertions(+) diff --git a/qcom/lahaina-v2-gpu.dtsi b/qcom/lahaina-v2-gpu.dtsi index 7b23189b324a..23b477a5fa54 100644 --- a/qcom/lahaina-v2-gpu.dtsi +++ b/qcom/lahaina-v2-gpu.dtsi @@ -382,5 +382,522 @@ qcom,acd-level = <0x882f5ffd>; }; }; + + qcom,gpu-pwrlevels-2 { + #address-cells = <1>; + #size-cells = <0>; + qcom,speed-bin = <3>; + qcom,initial-pwrlevel = <10>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882a5ffd>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <840000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882a5ffd>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <778000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82a5ffd>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <738000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82a5ffd>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <676000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <10>; + qcom,bus-min-ddr8 = <10>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882b5ffd>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <608000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82b5ffd>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <540000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0xa82c5ffd>; + }; + + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <491000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82c5ffd>; + }; + + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82d5ffd>; + }; + + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <379000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882e5ffd>; + }; + + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <315000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <2>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <2>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882f5ffd>; + }; + }; + + qcom,gpu-pwrlevels-3 { + #address-cells = <1>; + #size-cells = <0>; + qcom,speed-bin = <5>; + qcom,initial-pwrlevel = <9>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <840000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882a5ffd>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <778000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82a5ffd>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <738000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82a5ffd>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <676000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <10>; + qcom,bus-min-ddr8 = <10>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882b5ffd>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <608000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82b5ffd>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <540000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0xa82c5ffd>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <491000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82c5ffd>; + }; + + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82d5ffd>; + }; + + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <379000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882e5ffd>; + }; + + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <315000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <2>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <2>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882f5ffd>; + }; + }; + + qcom,gpu-pwrlevels-4 { + #address-cells = <1>; + #size-cells = <0>; + qcom,speed-bin = <7>; + qcom,initial-pwrlevel = <9>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <840000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882a5ffd>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <778000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82a5ffd>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <738000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82a5ffd>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <676000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <10>; + qcom,bus-min-ddr8 = <10>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882b5ffd>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <608000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82b5ffd>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <540000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0xa82c5ffd>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <491000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82c5ffd>; + }; + + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82d5ffd>; + }; + + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <379000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882e5ffd>; + }; + + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <315000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <2>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <2>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882f5ffd>; + }; + }; }; }; From 17f3998ed6e95d5b89ac833c5a4845f8b2a1fe7d Mon Sep 17 00:00:00 2001 From: Kunlei Zhang Date: Mon, 8 Feb 2021 17:05:05 +0800 Subject: [PATCH 054/122] ARM: dts: msm: update wsa node for yupik qrd audio Update wsa node for yupik qrd audio. Change-Id: Ia683ea28c86ecf81b4e808ef67f6ee658087dca6 --- qcom/yupik-qrd.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index c3d55c5624f6..8c02fce25000 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -389,6 +389,10 @@ status = "disabled"; }; +&wsa883x_0222 { + qcom,spkr-sd-n-node = <&wsa_spkr_en1>; +}; + &swr_haptics { status = "okay"; swr-slave-supply = <&hap_swr_slave_reg>; From c85bf25cc1c7e4176c6b2fd458e984668858bab0 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Wed, 17 Feb 2021 20:56:04 +0530 Subject: [PATCH 055/122] ARM: dts: msm: Add proxy vote on display regulators on yupik Add proxy vote for L10C and L6B regulators on yupik target. Change-Id: Iea12abbefa2232c2d4e2417dd8768ad425710a2d --- qcom/yupik-regulators.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/yupik-regulators.dtsi b/qcom/yupik-regulators.dtsi index f749bb55eeb7..f2feffa53383 100644 --- a/qcom/yupik-regulators.dtsi +++ b/qcom/yupik-regulators.dtsi @@ -153,6 +153,7 @@ ; qcom,mode-threshold-currents = <0 30000>; + proxy-supply = <&pm7325_l6>; L6B: pm7325_l6: regulator-pm7325-l6 { regulator-name = "pm7325_l6"; @@ -160,6 +161,8 @@ regulator-min-microvolt = <1140000>; regulator-max-microvolt = <1260000>; qcom,init-voltage = <1200000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <8350>; qcom,init-mode = ; }; }; @@ -730,6 +733,7 @@ ; qcom,mode-threshold-currents = <0 30000>; + proxy-supply = <&pm8350c_l10>; L10C: pm8350c_l10: regulator-pm8350c-l10 { regulator-name = "pm8350c_l10"; @@ -737,6 +741,8 @@ regulator-min-microvolt = <720000>; regulator-max-microvolt = <1050000>; qcom,init-voltage = <880000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <37550>; qcom,init-mode = ; }; From 7efa4c5a047f490ed0c8f3398ca0e338b7ee426d Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Mon, 15 Feb 2021 18:23:16 +0530 Subject: [PATCH 056/122] ARM: dts: msm: Enable touch support on lahaina MTP 2.1 This change adds touch support for r66451 dsc fhd plus 60fps command mode panel on lahaina. Change-Id: I7b5e396bc52c02b8e879b1a947b40cea83aa3bbe --- qcom/lahaina-mtp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/lahaina-mtp.dtsi b/qcom/lahaina-mtp.dtsi index 9efb33e86994..237462e72971 100644 --- a/qcom/lahaina-mtp.dtsi +++ b/qcom/lahaina-mtp.dtsi @@ -103,6 +103,7 @@ pinctrl-2 = <&ts_release>; panel = <&dsi_r66451_amoled_cmd + &dsi_r66451_amoled_60hz_cmd &dsi_r66451_amoled_video &dsi_r66451_amoled_144hz_cmd>; focaltech,trusted-touch-mode = "vm_mode"; From 73fd3c0b1a8478ff015806f6c97b94fcb029f5a1 Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Mon, 8 Mar 2021 18:16:14 +0530 Subject: [PATCH 057/122] ARM: dts: msm: Enable two_pass_use_wfi quirk for yupik GPU Enable two_pass_mode_wfi quirk to set TWOPASSUSEWFI in PC_DBG_ECO_CTL for yupik GPU. Change-Id: I7fdef91ffddfe3a3f5578ae93c7323ad90f860ba --- qcom/yupik-gpu.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/yupik-gpu.dtsi b/qcom/yupik-gpu.dtsi index d516d638b7a7..67f2eb0010ed 100644 --- a/qcom/yupik-gpu.dtsi +++ b/qcom/yupik-gpu.dtsi @@ -52,6 +52,7 @@ qcom,min-access-length = <32>; qcom,ubwc-mode = <3>; + qcom,gpu-quirk-two-pass-use-wfi; nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>; nvmem-cell-names = "speed_bin", "gaming_bin"; From 52b4b5d706b40db2f749e34c120d5b946923fc64 Mon Sep 17 00:00:00 2001 From: Minghao Zhang Date: Wed, 17 Mar 2021 15:30:43 +0800 Subject: [PATCH 058/122] ARM: dts: qcom: Update CPU and GPU mitigation rules on Lahaina HHG Update cpu-1-6-step and cpu-1-7-step thermal zone mitigation rules with CPU and gpuss-0-step and gpuss-1-step thermal zone mitigation rules with GPU based on the latest recommendation. Change-Id: I5721575cac197b976867aa78b98ed5694316d6f0 --- qcom/lahaina-hhg.dtsi | 108 +++++++++++++----------------------------- 1 file changed, 32 insertions(+), 76 deletions(-) diff --git a/qcom/lahaina-hhg.dtsi b/qcom/lahaina-hhg.dtsi index 386367957b73..4205dd82791d 100644 --- a/qcom/lahaina-hhg.dtsi +++ b/qcom/lahaina-hhg.dtsi @@ -115,25 +115,19 @@ cpu-1-6-step { trips { fan_cpu16_config0: fan-cpu16-config0 { - temperature = <50000>; - hysteresis = <0>; + temperature = <80000>; + hysteresis = <5000>; type = "passive"; }; fan_cpu16_config1: fan-cpu16-config1 { - temperature = <65000>; - hysteresis = <0>; + temperature = <90000>; + hysteresis = <5000>; type = "passive"; }; fan_cpu16_config2: fan-cpu16-config2 { - temperature = <80000>; - hysteresis = <0>; - type = "passive"; - }; - - fan_cpu16_config3: fan-cpu16-config3 { - temperature = <90000>; + temperature = <95000>; hysteresis = <0>; type = "passive"; }; @@ -142,22 +136,17 @@ cooling-maps { fan_cdev_0 { trip = <&fan_cpu16_config0>; - cooling-device = <&fancontroller 0 1>; + cooling-device = <&fancontroller 1 1>; }; fan_cdev_1 { trip = <&fan_cpu16_config1>; - cooling-device = <&fancontroller 1 2>; + cooling-device = <&fancontroller 2 2>; }; fan_cdev_2 { trip = <&fan_cpu16_config2>; - cooling-device = <&fancontroller 2 3>; - }; - - fan_cdev_3 { - trip = <&fan_cpu16_config3>; - cooling-device = <&fancontroller 3 4>; + cooling-device = <&fancontroller 3 3>; }; }; }; @@ -165,25 +154,19 @@ cpu-1-7-step { trips { fan_cpu17_config0: fan-cpu17-config0 { - temperature = <50000>; - hysteresis = <0>; + temperature = <80000>; + hysteresis = <5000>; type = "passive"; }; fan_cpu17_config1: fan-cpu17-config1 { - temperature = <65000>; - hysteresis = <0>; + temperature = <90000>; + hysteresis = <5000>; type = "passive"; }; fan_cpu17_config2: fan-cpu17-config2 { - temperature = <80000>; - hysteresis = <0>; - type = "passive"; - }; - - fan_cpu17_config3: fan-cpu17-config3 { - temperature = <90000>; + temperature = <95000>; hysteresis = <0>; type = "passive"; }; @@ -192,22 +175,17 @@ cooling-maps { fan_cdev_0 { trip = <&fan_cpu17_config0>; - cooling-device = <&fancontroller 0 1>; + cooling-device = <&fancontroller 1 1>; }; fan_cdev_1 { trip = <&fan_cpu17_config1>; - cooling-device = <&fancontroller 1 2>; + cooling-device = <&fancontroller 2 2>; }; fan_cdev_2 { trip = <&fan_cpu17_config2>; - cooling-device = <&fancontroller 2 3>; - }; - - fan_cdev_3 { - trip = <&fan_cpu17_config3>; - cooling-device = <&fancontroller 3 4>; + cooling-device = <&fancontroller 3 3>; }; }; }; @@ -215,25 +193,19 @@ gpuss-0-step { trips { fan_gpuss0_config0: fan-gpuss0-config0 { - temperature = <50000>; - hysteresis = <0>; + temperature = <85000>; + hysteresis = <5000>; type = "passive"; }; fan_gpuss0_config1: fan-gpuss0-config1 { - temperature = <65000>; - hysteresis = <0>; + temperature = <90000>; + hysteresis = <5000>; type = "passive"; }; fan_gpuss0_config2: fan-gpuss0-config2 { - temperature = <80000>; - hysteresis = <0>; - type = "passive"; - }; - - fan_gpuss0_config3: fan-gpuss0-config3 { - temperature = <90000>; + temperature = <95000>; hysteresis = <0>; type = "passive"; }; @@ -242,22 +214,17 @@ cooling-maps { fan_cdev_0 { trip = <&fan_gpuss0_config0>; - cooling-device = <&fancontroller 0 1>; + cooling-device = <&fancontroller 1 1>; }; fan_cdev_1 { trip = <&fan_gpuss0_config1>; - cooling-device = <&fancontroller 1 2>; + cooling-device = <&fancontroller 2 2>; }; fan_cdev_2 { trip = <&fan_gpuss0_config2>; - cooling-device = <&fancontroller 2 3>; - }; - - fan_cdev_3 { - trip = <&fan_gpuss0_config3>; - cooling-device = <&fancontroller 3 4>; + cooling-device = <&fancontroller 3 3>; }; }; }; @@ -265,25 +232,19 @@ gpuss-1-step { trips { fan_gpuss1_config0: fan-gpuss1-config0 { - temperature = <50000>; - hysteresis = <0>; + temperature = <85000>; + hysteresis = <5000>; type = "passive"; }; fan_gpuss1_config1: fan-gpuss1-config1 { - temperature = <65000>; - hysteresis = <0>; + temperature = <90000>; + hysteresis = <5000>; type = "passive"; }; fan_gpuss1_config2: fan-gpuss1-config2 { - temperature = <80000>; - hysteresis = <0>; - type = "passive"; - }; - - fan_gpuss1_config3: fan-gpuss1-config3 { - temperature = <90000>; + temperature = <95000>; hysteresis = <0>; type = "passive"; }; @@ -292,22 +253,17 @@ cooling-maps { fan_cdev_0 { trip = <&fan_gpuss1_config0>; - cooling-device = <&fancontroller 0 1>; + cooling-device = <&fancontroller 1 1>; }; fan_cdev_1 { trip = <&fan_gpuss1_config1>; - cooling-device = <&fancontroller 1 2>; + cooling-device = <&fancontroller 2 2>; }; fan_cdev_2 { trip = <&fan_gpuss1_config2>; - cooling-device = <&fancontroller 2 3>; - }; - - fan_cdev_3 { - trip = <&fan_gpuss1_config3>; - cooling-device = <&fancontroller 3 4>; + cooling-device = <&fancontroller 3 3>; }; }; }; From dadac09954ad6d66130efec6daf3245d196ca491 Mon Sep 17 00:00:00 2001 From: Yue Ma Date: Fri, 26 Mar 2021 14:37:44 +0530 Subject: [PATCH 059/122] ARM: dts: msm: Add switch control GPIO for WLAN Add SW_CTRL GPIO TLMM 153 in the CNSS node for WLAN device. Change-Id: Ic07c565e85c30796def08d8c3dd3784ae65fafc7 --- bindings/cnss/cnss-wlan.txt | 1 + qcom/lahaina.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/bindings/cnss/cnss-wlan.txt b/bindings/cnss/cnss-wlan.txt index 05e7db9fd7f5..deb8508b9a8e 100644 --- a/bindings/cnss/cnss-wlan.txt +++ b/bindings/cnss/cnss-wlan.txt @@ -94,6 +94,7 @@ Optional properties: enable to resolve PMU power up issues. Provide BT GPIO using this config param. - qcom,xo-clk-gpio: Added for QCA6490 XO CLK selection leakage prevention. + - qcom,sw-ctrl-gpio: Switch control GPIO for device power control - qcom,same-dt-multi-dev: Boolean property to decide whether it supports multiple WLAN devices using the same DT node without sub-nodes. diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 6700bdec8550..10768627ee74 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5386,6 +5386,7 @@ reg-names = "smmu_iova_ipa", "tcs_cmd"; wlan-en-gpio = <&tlmm 64 0>; qcom,bt-en-gpio = <&tlmm 65 0>; + qcom,sw-ctrl-gpio = <&tlmm 153 0>; pinctrl-names = "wlan_en_active", "wlan_en_sleep"; pinctrl-0 = <&cnss_wlan_en_active>; pinctrl-1 = <&cnss_wlan_en_sleep>; From 11f37d78af7d005188982161d9cc159f168a01c0 Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Wed, 31 Mar 2021 14:46:24 +0800 Subject: [PATCH 060/122] ARM: dts: msm: Update PCIe0 PHY settings to v1.00 for p v2.1 Update PCIe0 PHY setting to version 1.00 based on hardware recommendation for p v2.1. Change-Id: Ib0dc5da58ca41520d4f23efdd3f71239aef4a0e0 --- qcom/lahainap-v2.1.dtsi | 79 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/qcom/lahainap-v2.1.dtsi b/qcom/lahainap-v2.1.dtsi index 67728c60f3b9..4b57547fab01 100644 --- a/qcom/lahainap-v2.1.dtsi +++ b/qcom/lahainap-v2.1.dtsi @@ -5,3 +5,82 @@ compatible = "qcom,lahainap"; qcom,msm-id = <439 0x20001>, <502 0x20001>; }; + +&pcie0 { + qcom,pcie-phy-ver = <21101>; + qcom,phy-sequence = <0x0240 0x03 0x0 + 0x0094 0x08 0x0 + 0x0154 0x34 0x0 + 0x016c 0x08 0x0 + 0x0058 0x0f 0x0 + 0x00a4 0x42 0x0 + 0x0110 0x24 0x0 + 0x011c 0x03 0x0 + 0x0118 0xb4 0x0 + 0x010c 0x02 0x0 + 0x01bc 0x11 0x0 + 0x00bc 0x82 0x0 + 0x00d4 0x03 0x0 + 0x00d0 0x55 0x0 + 0x00cc 0x55 0x0 + 0x00b0 0x1a 0x0 + 0x00ac 0x0a 0x0 + 0x00c4 0x68 0x0 + 0x00e0 0x02 0x0 + 0x00dc 0xaa 0x0 + 0x00d8 0xab 0x0 + 0x00b8 0x34 0x0 + 0x00b4 0x14 0x0 + 0x0158 0x01 0x0 + 0x0074 0x06 0x0 + 0x007c 0x16 0x0 + 0x0084 0x36 0x0 + 0x0078 0x06 0x0 + 0x0080 0x16 0x0 + 0x0088 0x36 0x0 + 0x01b0 0x1e 0x0 + 0x01ac 0xca 0x0 + 0x01b8 0x18 0x0 + 0x01b4 0xa2 0x0 + 0x0050 0x07 0x0 + 0x0010 0x01 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0ee4 0x20 0x0 + 0x0e84 0x75 0x0 + 0x0e90 0x3f 0x0 + 0x115c 0x7f 0x0 + 0x1160 0xff 0x0 + 0x1164 0xbf 0x0 + 0x1168 0x3f 0x0 + 0x116c 0xd8 0x0 + 0x1170 0xdc 0x0 + 0x1174 0xdc 0x0 + 0x1178 0x5c 0x0 + 0x117c 0x34 0x0 + 0x1180 0xa6 0x0 + 0x1190 0x34 0x0 + 0x10d8 0x07 0x0 + 0x0e3c 0x1d 0x0 + 0x0e40 0x0c 0x0 + 0x10dc 0x00 0x0 + 0x104c 0x08 0x0 + 0x1050 0x08 0x0 + 0x1044 0xf0 0x0 + 0x11a4 0x38 0x0 + 0x10cc 0xf0 0x0 + 0x0694 0x00 0x0 + 0x0654 0x00 0x0 + 0x06a8 0x0f 0x0 + 0x0048 0x90 0x0 + 0x0620 0xc1 0x0 + 0x0388 0x77 0x0 + 0x0398 0x0b 0x0 + 0x02dc 0x05 0x0 + 0x0200 0x00 0x0 + 0x0244 0x03 0x0>; +}; From 2d3eddf4cb84b385f21e5ac6d7bff1443b01f1b0 Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Wed, 31 Mar 2021 14:50:14 +0800 Subject: [PATCH 061/122] ARM: dts: msm: Enable L1SS sleep for p-v2.1 PCIe0 phy on v2.1 manages the phy PLL properly hence remove the software workaround to keep the phy PLL always on. Change-Id: I435a5776a75b6613d93f47d46ced65e0080b3a94 --- qcom/lahainap-v2.1.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/lahainap-v2.1.dtsi b/qcom/lahainap-v2.1.dtsi index 4b57547fab01..53307dcb647b 100644 --- a/qcom/lahainap-v2.1.dtsi +++ b/qcom/lahainap-v2.1.dtsi @@ -7,6 +7,7 @@ }; &pcie0 { + qcom,l1ss-sleep-disable = <0x0>; qcom,pcie-phy-ver = <21101>; qcom,phy-sequence = <0x0240 0x03 0x0 0x0094 0x08 0x0 From b463a9cf5a52d5c5d0b6965b47f5f13af983b521 Mon Sep 17 00:00:00 2001 From: Kiran Raparthy Date: Tue, 23 Mar 2021 04:01:36 -0700 Subject: [PATCH 062/122] Revert "ARM: dts: msm: Add CX and MX SDPM configuration for YUPIK" This reverts commit 836e490a13eaab21195a5f664ec9070110381b8e. Change-Id: I2faa07a8bcf373c637ae7cad8b0142469a2bafcf Signed-off-by: Kiran Raparthy --- qcom/yupik-thermal.dtsi | 155 ---------------------------------------- 1 file changed, 155 deletions(-) diff --git a/qcom/yupik-thermal.dtsi b/qcom/yupik-thermal.dtsi index 644d307e781d..c161768445eb 100644 --- a/qcom/yupik-thermal.dtsi +++ b/qcom/yupik-thermal.dtsi @@ -61,40 +61,6 @@ "msm_skin_therm"; }; }; - - mx_sdpm@0x00636000 { - compatible = "qcom,sdpm"; - reg = <0x00636000 0x1000>; - clock-names = "cam_cc_ipe", "disp_cc_mdss_mdp"; - clocks = <&camcc CAM_CC_IPE_0_CLK_SRC>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; - cam_cc_ipe-supply = <&cam_cc_ipe_0_gdsc>; - csr-id = <1 4>; - }; - - cx_sdpm@0x00634000 { - compatible = "qcom,sdpm"; - reg = <0x00634000 0x1000>; - clock-names = "cam_cc_ipe", "disp_cc_mdss_mdp"; - clocks = <&camcc CAM_CC_IPE_0_CLK_SRC>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; - cam_cc_ipe-supply = <&cam_cc_ipe_0_gdsc>; - csr-id = <0 2>; - }; - - mx_pe: mx_rdpm_pe@0x00637000 { - compatible = "qcom,policy-engine"; - #thermal-sensor-cells = <0>; - reg = <0x00637000 0x1000>; - interrupts = ; - }; - - cx_pe: cx_rdpm_pe@0x00635000 { - compatible = "qcom,policy-engine"; - #thermal-sensor-cells = <0>; - reg = <0x00635000 0x1000>; - interrupts = ; - }; }; &qmi_tmd { @@ -1501,125 +1467,4 @@ }; }; - mx-pe-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&mx_pe>; - thermal-governor = "step_wise"; - trips { - mx_pe_config1: mx-pe-config1 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - - mx_pe_config2: mx-pe-config2 { - temperature = <2>; - hysteresis = <1>; - type = "passive"; - }; - - mx_pe_config3: mx-pe-config3 { - temperature = <3>; - hysteresis = <1>; - type = "passive"; - }; - }; - - cooling-maps { - mx_pe_cdev_cpu4 { - trip = <&mx_pe_config1>; - cooling-device = <&cpu4_isolate 0 0>; - }; - - mx_pe_cdev_cpu5 { - trip = <&mx_pe_config1>; - cooling-device = <&cpu5_isolate 0 0>; - }; - - mx_pe_cdev_cpu6 { - trip = <&mx_pe_config1>; - cooling-device = <&cpu6_isolate 0 0>; - }; - - mx_pe_cdev_cpu7 { - trip = <&mx_pe_config1>; - cooling-device = <&cpu7_isolate 0 0>; - }; - - mx_pe_cdev_cdsp { - trip = <&mx_pe_config1>; - cooling-device = <&cdsp_sw 0 0>; - }; - - mx_pe_cdev_gpu { - trip = <&mx_pe_config2>; - cooling-device = <&msm_gpu 0 0>; - }; - - mx_pe_cdev_modem { - trip = <&mx_pe_config3>; - cooling-device = <&modem_tj 0 0>; - }; - }; - }; - - cx-pe-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&cx_pe>; - thermal-governor = "step_wise"; - trips { - cx_pe_config1: cx-pe-config1 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - - cx_pe_config2: cx-pe-config2 { - temperature = <2>; - hysteresis = <1>; - type = "passive"; - }; - - cx_pe_config3: cx-pe-config3 { - temperature = <3>; - hysteresis = <1>; - type = "passive"; - }; - - cx_pe_config4: cx-pe-config4 { - temperature = <4>; - hysteresis = <1>; - type = "passive"; - }; - }; - - cooling-maps { - cx_pe_cdev_1 { - trip = <&cx_pe_config1>; - cooling-device = <&cdsp_sw 0 0>; - }; - - cx_pe_cdev_2 { - trip = <&cx_pe_config2>; - cooling-device = <&cdsp_sw 0 0>; - }; - - cx_pe_cdev_3 { - trip = <&cx_pe_config3>; - cooling-device = <&cdsp_sw 0 0>; - }; - - cx_pe_cdev_4 { - trip = <&cx_pe_config4>; - cooling-device = <&modem_tj 0 0>; - }; - - cx_pe_cdev_5 { - trip = <&cx_pe_config4>; - cooling-device = <&msm_gpu 0 0>; - }; - }; - }; }; From ef0546c44d1ce8d59901076c4154a1bb4ef08a5e Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Fri, 2 Apr 2021 15:14:57 +0530 Subject: [PATCH 063/122] ARM: dts: qcom: Enable CPU frequency cooling device for YUPIK Add cooling-cell property to enable CPU frequency cooling devices for YUPIK. Change-Id: I5c91c1cbe11552466c08013968f46d568f6b9d42 --- qcom/yupik.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 748d3dfc222d..2d9075c89e2f 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -77,6 +77,7 @@ dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 0 4>; next-level-cache = <&L2_0>; + #cooling-cells = <2>; L2_0: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -150,6 +151,7 @@ dynamic-power-coefficient = <520>; qcom,freq-domain = <&cpufreq_hw 1 4>; next-level-cache = <&L2_4>; + #cooling-cells = <2>; L2_4: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -201,6 +203,7 @@ dynamic-power-coefficient = <552>; qcom,freq-domain = <&cpufreq_hw 2 4>; next-level-cache = <&L2_7>; + #cooling-cells = <2>; L2_7: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; From 5b2e54a4c8c43a0f6fd4f9ff534fc6c72154c5fe Mon Sep 17 00:00:00 2001 From: Vishvanath Singh Date: Thu, 22 Apr 2021 12:18:07 +0530 Subject: [PATCH 064/122] ARM: dts: msm: Add CX and MX SDPM configuration for YUPIK Add CX SDPM configuration to monitor Camera, Display clocks. Add MX SDPM configuration to monitor Camera, Display clocks. Change-Id: I8c08a41e5d37f8768c661a79967b0e7e3509a489 --- qcom/yupik-thermal.dtsi | 155 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 155 insertions(+) diff --git a/qcom/yupik-thermal.dtsi b/qcom/yupik-thermal.dtsi index c161768445eb..644d307e781d 100644 --- a/qcom/yupik-thermal.dtsi +++ b/qcom/yupik-thermal.dtsi @@ -61,6 +61,40 @@ "msm_skin_therm"; }; }; + + mx_sdpm@0x00636000 { + compatible = "qcom,sdpm"; + reg = <0x00636000 0x1000>; + clock-names = "cam_cc_ipe", "disp_cc_mdss_mdp"; + clocks = <&camcc CAM_CC_IPE_0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + cam_cc_ipe-supply = <&cam_cc_ipe_0_gdsc>; + csr-id = <1 4>; + }; + + cx_sdpm@0x00634000 { + compatible = "qcom,sdpm"; + reg = <0x00634000 0x1000>; + clock-names = "cam_cc_ipe", "disp_cc_mdss_mdp"; + clocks = <&camcc CAM_CC_IPE_0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + cam_cc_ipe-supply = <&cam_cc_ipe_0_gdsc>; + csr-id = <0 2>; + }; + + mx_pe: mx_rdpm_pe@0x00637000 { + compatible = "qcom,policy-engine"; + #thermal-sensor-cells = <0>; + reg = <0x00637000 0x1000>; + interrupts = ; + }; + + cx_pe: cx_rdpm_pe@0x00635000 { + compatible = "qcom,policy-engine"; + #thermal-sensor-cells = <0>; + reg = <0x00635000 0x1000>; + interrupts = ; + }; }; &qmi_tmd { @@ -1467,4 +1501,125 @@ }; }; + mx-pe-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&mx_pe>; + thermal-governor = "step_wise"; + trips { + mx_pe_config1: mx-pe-config1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + + mx_pe_config2: mx-pe-config2 { + temperature = <2>; + hysteresis = <1>; + type = "passive"; + }; + + mx_pe_config3: mx-pe-config3 { + temperature = <3>; + hysteresis = <1>; + type = "passive"; + }; + }; + + cooling-maps { + mx_pe_cdev_cpu4 { + trip = <&mx_pe_config1>; + cooling-device = <&cpu4_isolate 0 0>; + }; + + mx_pe_cdev_cpu5 { + trip = <&mx_pe_config1>; + cooling-device = <&cpu5_isolate 0 0>; + }; + + mx_pe_cdev_cpu6 { + trip = <&mx_pe_config1>; + cooling-device = <&cpu6_isolate 0 0>; + }; + + mx_pe_cdev_cpu7 { + trip = <&mx_pe_config1>; + cooling-device = <&cpu7_isolate 0 0>; + }; + + mx_pe_cdev_cdsp { + trip = <&mx_pe_config1>; + cooling-device = <&cdsp_sw 0 0>; + }; + + mx_pe_cdev_gpu { + trip = <&mx_pe_config2>; + cooling-device = <&msm_gpu 0 0>; + }; + + mx_pe_cdev_modem { + trip = <&mx_pe_config3>; + cooling-device = <&modem_tj 0 0>; + }; + }; + }; + + cx-pe-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&cx_pe>; + thermal-governor = "step_wise"; + trips { + cx_pe_config1: cx-pe-config1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config2: cx-pe-config2 { + temperature = <2>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config3: cx-pe-config3 { + temperature = <3>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config4: cx-pe-config4 { + temperature = <4>; + hysteresis = <1>; + type = "passive"; + }; + }; + + cooling-maps { + cx_pe_cdev_1 { + trip = <&cx_pe_config1>; + cooling-device = <&cdsp_sw 0 0>; + }; + + cx_pe_cdev_2 { + trip = <&cx_pe_config2>; + cooling-device = <&cdsp_sw 0 0>; + }; + + cx_pe_cdev_3 { + trip = <&cx_pe_config3>; + cooling-device = <&cdsp_sw 0 0>; + }; + + cx_pe_cdev_4 { + trip = <&cx_pe_config4>; + cooling-device = <&modem_tj 0 0>; + }; + + cx_pe_cdev_5 { + trip = <&cx_pe_config4>; + cooling-device = <&msm_gpu 0 0>; + }; + }; + }; }; From c5bd520b40acf52c41719da5c839068699839563 Mon Sep 17 00:00:00 2001 From: Hareesh Gundu Date: Thu, 8 Apr 2021 13:07:17 +0530 Subject: [PATCH 065/122] ARM: dts: msm: Add gpu-model property for yupik gpu Add gpu-model property to specify gpu name for yupik. Change-Id: I95787b3cedf98d7b71ba83ae16fd110ea84b5fff --- qcom/yupik-gpu.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/yupik-gpu.dtsi b/qcom/yupik-gpu.dtsi index 67f2eb0010ed..c09538cf0ddc 100644 --- a/qcom/yupik-gpu.dtsi +++ b/qcom/yupik-gpu.dtsi @@ -48,6 +48,7 @@ "gpu_cc_hub_cx_int"; qcom,chipid = <0x06030500>; + qcom,gpu-model = "Adreno642Lv1"; qcom,no-nap; qcom,min-access-length = <32>; From 5125839af05bf60cc1a5fd28dad2075a1c619748 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Mon, 19 Apr 2021 20:52:07 +0530 Subject: [PATCH 066/122] ARM: dts: msm: Add skin, modem and junction thermal config for YUPIK Add queit-therm, modem-lte-sub6-pa, camera and video sensors mitigation config based on latest recommendation for yupik. Change-Id: I7ecbb36e88208c6c30df0c3c0a40a685624d6602 --- qcom/yupik-qrd.dtsi | 70 ++++++++++++++++- qcom/yupik-thermal.dtsi | 162 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 226 insertions(+), 6 deletions(-) diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index cebfeb233046..c9db2290ae63 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -272,6 +272,42 @@ thermal-sensors = <&pmk8350_adc_tm PM7325_ADC7_AMUX_THM1_100K_PU>; trips { + quiet_skin_trip0: quiet-skin-trip0 { + temperature = <43000>; + hysteresis = <4000>; + type = "passive"; + }; + + quiet_batt_trip0: quiet-batt-trip0 { + temperature = <44000>; + hysteresis = <2000>; + type = "passive"; + }; + + quiet_skin_trip1: quiet-skin-trip1 { + temperature = <45000>; + hysteresis = <4000>; + type = "passive"; + }; + + quiet_batt_trip1: quiet-batt-trip1 { + temperature = <46000>; + hysteresis = <2000>; + type = "passive"; + }; + + quiet_batt_trip2: quiet-batt-trip2 { + temperature = <48000>; + hysteresis = <2000>; + type = "passive"; + }; + + quiet_batt_trip3: quiet-batt-trip3 { + temperature = <49000>; + hysteresis = <1000>; + type = "passive"; + }; + quiet_apc_trip: quiet-apc-trip { temperature = <50000>; hysteresis = <0>; @@ -329,9 +365,39 @@ cooling-device = <&cdsp_sw 4 4>; }; - modem-pa-cdev { + skin-cdev0 { + trip = <&quiet_skin_trip0>; + cooling-device = <&modem_skin 1 1>; + }; + + skin-cdev1 { + trip = <&quiet_skin_trip1>; + cooling-device = <&modem_skin 2 2>; + }; + + skin-cdev2 { trip = <&quiet_cx_trip>; - cooling-device = <&modem_pa 3 3>; + cooling-device = <&modem_skin 3 3>; + }; + + batt-cdev0 { + trip = <&quiet_batt_trip0>; + cooling-device = <&battery_charger 4 4>; + }; + + batt-cdev1 { + trip = <&quiet_batt_trip1>; + cooling-device = <&battery_charger 8 8>; + }; + + batt-cdev2 { + trip = <&quiet_batt_trip2>; + cooling-device = <&battery_charger 12 12>; + }; + + batt-cdev3 { + trip = <&quiet_batt_trip3>; + cooling-device = <&battery_charger 16 16>; }; }; }; diff --git a/qcom/yupik-thermal.dtsi b/qcom/yupik-thermal.dtsi index 644d307e781d..579811c898ca 100644 --- a/qcom/yupik-thermal.dtsi +++ b/qcom/yupik-thermal.dtsi @@ -259,6 +259,94 @@ }; }; + modem-sub6-pa1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_PA)>; + trips { + sub6_pa1_trip0: sub6-pa1-trip0 { + temperature = <43000>; + hysteresis = <4000>; + type = "passive"; + }; + + sub6_pa1_trip1: sub6-pa1-trip1 { + temperature = <45000>; + hysteresis = <4000>; + type = "passive"; + }; + + sub6_pa1_trip2: sub6-pa1-trip2 { + temperature = <55000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + pa_fr1_cdev0 { + trip = <&sub6_pa1_trip0>; + cooling-device = <&modem_pa_fr1 1 1>; + }; + + pa_fr1_cdev1 { + trip = <&sub6_pa1_trip1>; + cooling-device = <&modem_pa_fr1 2 2>; + }; + + pa_fr1_cdev2 { + trip = <&sub6_pa1_trip2>; + cooling-device = <&modem_pa_fr1 3 3>; + }; + }; + }; + + modem-lte-pa2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_PA_1)>; + trips { + sub6_pa2_trip0: sub6-pa2-trip0 { + temperature = <42000>; + hysteresis = <4000>; + type = "passive"; + }; + + sub6_pa2_trip1: sub6-pa2-trip1 { + temperature = <44000>; + hysteresis = <4000>; + type = "passive"; + }; + + sub6_pa2_trip2: sub6-pa2-trip2 { + temperature = <55000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + pa_cdev0 { + trip = <&sub6_pa2_trip0>; + cooling-device = <&modem_pa 1 1>; + }; + + pa_cdev1 { + trip = <&sub6_pa2_trip1>; + cooling-device = <&modem_pa 2 2>; + }; + + pa_cdev2 { + trip = <&sub6_pa2_trip2>; + cooling-device = <&modem_pa 3 3>; + }; + }; + }; + aoss-0-usr { polling-delay-passive = <0>; polling-delay = <0>; @@ -1277,7 +1365,7 @@ }; cooling-maps { - cdsp-cdev { + cdsp_cdev { trip = <&nspss0_trip>; cooling-device = <&cdsp_sw 4 4>; }; @@ -1289,7 +1377,7 @@ THERMAL_MAX_LIMIT>; }; - modem-pa-cdev { + modem_pa_cdev { trip = <&nspss0_trip>; cooling-device = <&modem_pa 3 3>; }; @@ -1310,7 +1398,7 @@ }; cooling-maps { - cdsp-cdev { + cdsp_cdev { trip = <&nspss1_trip>; cooling-device = <&cdsp_sw 4 4>; }; @@ -1322,13 +1410,46 @@ THERMAL_MAX_LIMIT>; }; - modem-pa-cdev { + modem_pa_cdev { trip = <&nspss1_trip>; cooling-device = <&modem_pa 3 3>; }; }; }; + video-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 5>; + trips { + video_trip: video-trip { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cdsp_cdev { + trip = <&video_trip>; + cooling-device = <&cdsp_sw 4 4>; + }; + + gpu_cdev { + trip = <&video_trip>; + /* throttle to 315000000Hz */ + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + modem_pa_cdev { + trip = <&video_trip>; + cooling-device = <&modem_pa 3 3>; + }; + }; + }; + mdmss-0-step { polling-delay-passive = <0>; polling-delay = <0>; @@ -1501,6 +1622,39 @@ }; }; + camera-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 11>; + trips { + camera_trip: camera-trip { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cdsp_cdev { + trip = <&camera_trip>; + cooling-device = <&cdsp_sw 4 4>; + }; + + gpu_cdev { + trip = <&camera_trip>; + /* throttle to 315000000Hz */ + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + modem_pa_cdev { + trip = <&camera_trip>; + cooling-device = <&modem_pa 3 3>; + }; + }; + }; + mx-pe-step { polling-delay-passive = <0>; polling-delay = <0>; From 297ce8370a991c17c0eb917576daae7e20be7f26 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Mon, 19 Apr 2021 23:14:13 +0530 Subject: [PATCH 067/122] ARM: dts: msm: Update Ibat threshold and BCL thermal config for YUPIK Update ibat level0 threshold to 5A based on latest recommendation. Remove GPU mitigation rules from BCL thermalzone config as GPU driver itself monitors BCL irq on CB and mitigates its frequency. Change-Id: I73f3fbab2e949cee957c09325f6fb4364bdead60 --- qcom/yupik-thermal-overlay-qrd.dtsi | 98 +++++++++++++++++------------ qcom/yupik-thermal-overlay.dtsi | 76 ++++++++++------------ 2 files changed, 90 insertions(+), 84 deletions(-) diff --git a/qcom/yupik-thermal-overlay-qrd.dtsi b/qcom/yupik-thermal-overlay-qrd.dtsi index 4d302f1cff41..1b35cdcf63e9 100644 --- a/qcom/yupik-thermal-overlay-qrd.dtsi +++ b/qcom/yupik-thermal-overlay-qrd.dtsi @@ -33,6 +33,14 @@ }; }; + pm8350b-ibat-lvl0 { + trips { + ibat-lvl0 { + temperature = <5000>; + }; + }; + }; + pm8350b-bcl-lvl0 { cooling-maps { vbat_cpu4 { @@ -45,50 +53,55 @@ cooling-device = <&cpu5_isolate 1 1>; }; - vbat_gpu0 { + vbat_cpu6 { trip = <&b_bcl_lvl0>; - cooling-device = <&msm_gpu 2 2>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + vbat_cpu7 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu7_isolate 1 1>; }; vbat_cdsp0 { trip = <&b_bcl_lvl0>; cooling-device = <&cdsp_sw 2 2>; }; + + vbat_modem0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_pa 2 2>; + }; + + vbat_modem1 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_tj 1 1>; + }; }; }; pm8350b-bcl-lvl1 { cooling-maps { - vbat_cpu6 { + vbat_gpu { trip = <&b_bcl_lvl1>; - cooling-device = <&cpu6_isolate 1 1>; - }; - - vbat_cpu7 { - trip = <&b_bcl_lvl1>; - cooling-device = <&cpu7_isolate 1 1>; - }; - - vbat_gpu1 { - trip = <&b_bcl_lvl1>; - cooling-device = <&msm_gpu 4 4>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; vbat_cdsp1 { trip = <&b_bcl_lvl1>; cooling-device = <&cdsp_sw 4 4>; }; + + vbat_modem2 { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_tj 3 3>; + }; }; }; pm8350b-bcl-lvl2 { cooling-maps { - vbat_gpu2 { - trip = <&b_bcl_lvl2>; - cooling-device = <&msm_gpu THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - vbat_cdsp2 { trip = <&b_bcl_lvl2>; cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT @@ -110,52 +123,57 @@ cooling-device = <&cpu5_isolate 1 1>; }; - vph_gpu0 { + vph_cpu6 { trip = <&c_bcl_lvl0>; - cooling-device = <&msm_gpu 2 2>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + vph_cpu7 { + trip = <&c_bcl_lvl0>; + cooling-device = <&cpu7_isolate 1 1>; }; vph_cdsp0 { trip = <&c_bcl_lvl0>; cooling-device = <&cdsp_sw 2 2>; }; + + vph_modem0 { + trip = <&c_bcl_lvl0>; + cooling-device = <&modem_pa 2 2>; + }; + + vph_modem1 { + trip = <&c_bcl_lvl0>; + cooling-device = <&modem_tj 1 1>; + }; }; }; pm8350c-bcl-lvl1 { disable-thermal-zone; cooling-maps { - vph_cpu6 { + vph_gpu { trip = <&c_bcl_lvl1>; - cooling-device = <&cpu6_isolate 1 1>; - }; - - vph_cpu7 { - trip = <&c_bcl_lvl1>; - cooling-device = <&cpu7_isolate 1 1>; - }; - - vph_gpu1 { - trip = <&c_bcl_lvl1>; - cooling-device = <&msm_gpu 4 4>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; vph_cdsp1 { trip = <&c_bcl_lvl1>; cooling-device = <&cdsp_sw 4 4>; }; + + vph_modem2 { + trip = <&c_bcl_lvl1>; + cooling-device = <&modem_tj 3 3>; + }; }; }; pm8350c-bcl-lvl2 { disable-thermal-zone; cooling-maps { - vph_gpu2 { - trip = <&c_bcl_lvl2>; - cooling-device = <&msm_gpu THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - vph_cdsp2 { trip = <&c_bcl_lvl2>; cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT diff --git a/qcom/yupik-thermal-overlay.dtsi b/qcom/yupik-thermal-overlay.dtsi index 6e1e1f9389e4..08629122a0e4 100644 --- a/qcom/yupik-thermal-overlay.dtsi +++ b/qcom/yupik-thermal-overlay.dtsi @@ -33,6 +33,14 @@ }; }; + pm7325b-ibat-lvl0 { + trips { + ibat-lvl0 { + temperature = <5000>; + }; + }; + }; + pm7325b-bcl-lvl0 { cooling-maps { vbat_cpu4 { @@ -45,9 +53,14 @@ cooling-device = <&cpu5_isolate 1 1>; }; - vbat_gpu0 { + vbat_cpu6 { trip = <&b_bcl_lvl0>; - cooling-device = <&msm_gpu 2 2>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + vbat_cpu7 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu7_isolate 1 1>; }; vbat_cdsp0 { @@ -69,19 +82,10 @@ pm7325b-bcl-lvl1 { cooling-maps { - vbat_cpu6 { + vbat_gpu { trip = <&b_bcl_lvl1>; - cooling-device = <&cpu6_isolate 1 1>; - }; - - vbat_cpu7 { - trip = <&b_bcl_lvl1>; - cooling-device = <&cpu7_isolate 1 1>; - }; - - vbat_gpu1 { - trip = <&b_bcl_lvl1>; - cooling-device = <&msm_gpu 4 4>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; vbat_cdsp1 { @@ -89,7 +93,7 @@ cooling-device = <&cdsp_sw 4 4>; }; - vbat_modem0 { + vbat_modem2 { trip = <&b_bcl_lvl1>; cooling-device = <&modem_tj 3 3>; }; @@ -98,12 +102,6 @@ pm7325b-bcl-lvl2 { cooling-maps { - vbat_gpu2 { - trip = <&b_bcl_lvl2>; - cooling-device = <&msm_gpu THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - vbat_cdsp2 { trip = <&b_bcl_lvl2>; cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT @@ -125,9 +123,14 @@ cooling-device = <&cpu5_isolate 1 1>; }; - vph_gpu0 { + vph_cpu6 { trip = <&c_bcl_lvl0>; - cooling-device = <&msm_gpu 2 2>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + vph_cpu7 { + trip = <&c_bcl_lvl0>; + cooling-device = <&cpu7_isolate 1 1>; }; vph_cdsp0 { @@ -135,12 +138,12 @@ cooling-device = <&cdsp_sw 2 2>; }; - vbat_modem0 { + vph_modem0 { trip = <&c_bcl_lvl0>; cooling-device = <&modem_pa 2 2>; }; - vbat_modem1 { + vph_modem1 { trip = <&c_bcl_lvl0>; cooling-device = <&modem_tj 1 1>; }; @@ -150,19 +153,10 @@ pm8350c-bcl-lvl1 { disable-thermal-zone; cooling-maps { - vph_cpu6 { + vph_gpu { trip = <&c_bcl_lvl1>; - cooling-device = <&cpu6_isolate 1 1>; - }; - - vph_cpu7 { - trip = <&c_bcl_lvl1>; - cooling-device = <&cpu7_isolate 1 1>; - }; - - vph_gpu1 { - trip = <&c_bcl_lvl1>; - cooling-device = <&msm_gpu 4 4>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; vph_cdsp1 { @@ -170,7 +164,7 @@ cooling-device = <&cdsp_sw 4 4>; }; - vbat_modem0 { + vph_modem2 { trip = <&c_bcl_lvl1>; cooling-device = <&modem_tj 3 3>; }; @@ -180,12 +174,6 @@ pm8350c-bcl-lvl2 { disable-thermal-zone; cooling-maps { - vph_gpu2 { - trip = <&c_bcl_lvl2>; - cooling-device = <&msm_gpu THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - vph_cdsp2 { trip = <&c_bcl_lvl2>; cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT From 3ec7a8f391f926c396ba5d1737b2409550ec3652 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Tue, 20 Apr 2021 17:51:42 +0530 Subject: [PATCH 068/122] ARM: dts: msm: Remove SDPM and policy-engine support for YUPIK Remove SDPM and policy-engine support based on latest recommondation for YUPIK. Change-Id: I7bf2d81913d13f448fac22aebfb46097ba93e2ea --- qcom/yupik-thermal.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/yupik-thermal.dtsi b/qcom/yupik-thermal.dtsi index 579811c898ca..9898b8d44e90 100644 --- a/qcom/yupik-thermal.dtsi +++ b/qcom/yupik-thermal.dtsi @@ -70,6 +70,7 @@ <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; cam_cc_ipe-supply = <&cam_cc_ipe_0_gdsc>; csr-id = <1 4>; + status = "disabled"; }; cx_sdpm@0x00634000 { @@ -80,6 +81,7 @@ <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; cam_cc_ipe-supply = <&cam_cc_ipe_0_gdsc>; csr-id = <0 2>; + status = "disabled"; }; mx_pe: mx_rdpm_pe@0x00637000 { @@ -87,6 +89,7 @@ #thermal-sensor-cells = <0>; reg = <0x00637000 0x1000>; interrupts = ; + status = "disabled"; }; cx_pe: cx_rdpm_pe@0x00635000 { @@ -94,6 +97,7 @@ #thermal-sensor-cells = <0>; reg = <0x00635000 0x1000>; interrupts = ; + status = "disabled"; }; }; @@ -1660,6 +1664,7 @@ polling-delay = <0>; thermal-sensors = <&mx_pe>; thermal-governor = "step_wise"; + status = "disabled"; trips { mx_pe_config1: mx-pe-config1 { temperature = <1>; @@ -1723,6 +1728,7 @@ polling-delay = <0>; thermal-sensors = <&cx_pe>; thermal-governor = "step_wise"; + status = "disabled"; trips { cx_pe_config1: cx-pe-config1 { temperature = <1>; From 248e287647b39b92308a86f69dbc31b58f9a4cac Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Mon, 31 May 2021 12:09:58 +0530 Subject: [PATCH 069/122] ARM: dts: msm: Update board-id for PM7250B Add board-id support for IDP with PM7250B for Yupik platform. Change-Id: I166e6e2b3a3888ab358f7d49920b4d4967161e95 --- qcom/yupik-idp-pm7250b-overlay.dts | 3 +-- qcom/yupik-idp-pm7250b.dts | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/qcom/yupik-idp-pm7250b-overlay.dts b/qcom/yupik-idp-pm7250b-overlay.dts index b2c533d7738a..7bae225d5cf2 100644 --- a/qcom/yupik-idp-pm7250b-overlay.dts +++ b/qcom/yupik-idp-pm7250b-overlay.dts @@ -7,6 +7,5 @@ model = "Qualcomm Technologies, Inc. Yupik IDP + PM7250B"; compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,idp"; qcom,msm-id = <475 0x10000>, <515 0x10000>; - /* Adding dummy Board subtype ID to bypass pmic protocol version check. */ - qcom,board-id = <34 0xFF>; + qcom,board-id = <34 0>; }; diff --git a/qcom/yupik-idp-pm7250b.dts b/qcom/yupik-idp-pm7250b.dts index 45ac21a01659..d487d08acc80 100644 --- a/qcom/yupik-idp-pm7250b.dts +++ b/qcom/yupik-idp-pm7250b.dts @@ -6,6 +6,5 @@ / { model = "Qualcomm Technologies, Inc. Yupik IDP + PM7250B"; compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,idp"; - /* Adding dummy Board subtype ID to bypass pmic protocol version check. */ - qcom,board-id = <34 0xFF>; + qcom,board-id = <34 0>; }; From a8e48aab3f475ae3daf73113daa1de960c3fe210 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Mon, 28 Jun 2021 00:15:43 +0530 Subject: [PATCH 070/122] ARM: dts: msm: Add skin and mmw thermal config for YUPIK Add skin and mmw thermal zone config rules for YUPIK as per recommondation. Change-Id: Iec03b991ab1036afa742e18bed622058aaab6616 --- qcom/yupik-qrd.dtsi | 180 ++++++++++++++++++++++++++++++++++++++------ 1 file changed, 159 insertions(+), 21 deletions(-) diff --git a/qcom/yupik-qrd.dtsi b/qcom/yupik-qrd.dtsi index 55329158acf7..20f36edecfff 100644 --- a/qcom/yupik-qrd.dtsi +++ b/qcom/yupik-qrd.dtsi @@ -273,20 +273,20 @@ (QMI_MODEM_INST_ID+QMI_PA)>; trips { sub6_pa1_trip0: sub6-pa1-trip0 { - temperature = <43000>; + temperature = <46000>; hysteresis = <4000>; type = "passive"; }; sub6_pa1_trip1: sub6-pa1-trip1 { - temperature = <45000>; + temperature = <47000>; hysteresis = <4000>; type = "passive"; }; sub6_pa1_trip2: sub6-pa1-trip2 { - temperature = <55000>; - hysteresis = <5000>; + temperature = <57000>; + hysteresis = <4000>; type = "passive"; }; }; @@ -317,20 +317,20 @@ (QMI_MODEM_INST_ID+QMI_PA_1)>; trips { sub6_pa2_trip0: sub6-pa2-trip0 { - temperature = <42000>; + temperature = <46000>; hysteresis = <4000>; type = "passive"; }; sub6_pa2_trip1: sub6-pa2-trip1 { - temperature = <44000>; + temperature = <47000>; hysteresis = <4000>; type = "passive"; }; sub6_pa2_trip2: sub6-pa2-trip2 { - temperature = <55000>; - hysteresis = <5000>; + temperature = <57000>; + hysteresis = <4000>; type = "passive"; }; }; @@ -360,30 +360,24 @@ thermal-sensors = <&pmk8350_adc_tm PM7325_ADC7_AMUX_THM1_100K_PU>; trips { - quiet_skin_trip0: quiet-skin-trip0 { - temperature = <43000>; - hysteresis = <4000>; - type = "passive"; - }; - quiet_batt_trip0: quiet-batt-trip0 { temperature = <44000>; hysteresis = <2000>; type = "passive"; }; - quiet_skin_trip1: quiet-skin-trip1 { - temperature = <45000>; - hysteresis = <4000>; - type = "passive"; - }; - quiet_batt_trip1: quiet-batt-trip1 { temperature = <46000>; hysteresis = <2000>; type = "passive"; }; + quiet_skin_trip0: quiet-skin-trip0 { + temperature = <47000>; + hysteresis = <4000>; + type = "passive"; + }; + quiet_batt_trip2: quiet-batt-trip2 { temperature = <48000>; hysteresis = <2000>; @@ -396,6 +390,12 @@ type = "passive"; }; + quiet_skin_trip1: quiet-skin-trip1 { + temperature = <49000>; + hysteresis = <4000>; + type = "passive"; + }; + quiet_apc_trip: quiet-apc-trip { temperature = <50000>; hysteresis = <0>; @@ -419,6 +419,12 @@ hysteresis = <5000>; type = "passive"; }; + + quiet_skin_trip2: quiet-skin-trip2 { + temperature = <57000>; + hysteresis = <4000>; + type = "passive"; + }; }; cooling-maps { @@ -464,7 +470,7 @@ }; skin-cdev2 { - trip = <&quiet_cx_trip>; + trip = <&quiet_skin_trip2>; cooling-device = <&modem_skin 3 3>; }; @@ -489,6 +495,138 @@ }; }; }; + + modem-mmw-pa1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW_PA1)>; + trips { + mmw_pa1_trip0: mmw-pa1-trip0 { + temperature = <48000>; + hysteresis = <2000>; + type = "passive"; + }; + + mmw_pa1_trip1: mmw-pa1-trip1 { + temperature = <51000>; + hysteresis = <2000>; + type = "passive"; + }; + + mmw_pa1_trip2: mmw-pa1-trip2 { + temperature = <57000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + mmw_skin1_cdev0 { + trip = <&mmw_pa1_trip0>; + cooling-device = <&modem_mmw_skin1 1 1>; + }; + + mmw_skin1_cdev1 { + trip = <&mmw_pa1_trip1>; + cooling-device = <&modem_mmw_skin1 2 2>; + }; + + mmw_skin1_cdev2 { + trip = <&mmw_pa1_trip2>; + cooling-device = <&modem_mmw_skin1 3 3>; + }; + }; + }; + + modem-mmw-pa2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW_PA2)>; + trips { + mmw_pa2_trip0: mmw-pa2-trip0 { + temperature = <46000>; + hysteresis = <2000>; + type = "passive"; + }; + + mmw_pa2_trip1: mmw-pa2-trip1 { + temperature = <48000>; + hysteresis = <2000>; + type = "passive"; + }; + + mmw_pa2_trip2: mmw-pa2-trip2 { + temperature = <57000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + mmw_skin2_cdev0 { + trip = <&mmw_pa2_trip0>; + cooling-device = <&modem_mmw_skin2 1 1>; + }; + + mmw_skin2_cdev1 { + trip = <&mmw_pa2_trip1>; + cooling-device = <&modem_mmw_skin2 2 2>; + }; + + mmw_skin2_cdev2 { + trip = <&mmw_pa2_trip2>; + cooling-device = <&modem_mmw_skin2 3 3>; + }; + }; + }; + + modem-mmw-pa3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW_PA3)>; + trips { + mmw_pa3_trip0: mmw-pa3-trip0 { + temperature = <46000>; + hysteresis = <2000>; + type = "passive"; + }; + + mmw_pa3_trip1: mmw-pa3-trip1 { + temperature = <48000>; + hysteresis = <2000>; + type = "passive"; + }; + + mmw_pa3_trip2: mmw-pa3-trip2 { + temperature = <57000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + mmw_skin0_cdev0 { + trip = <&mmw_pa3_trip0>; + cooling-device = <&modem_mmw_skin0 1 1>; + }; + + mmw_skin0_cdev1 { + trip = <&mmw_pa3_trip1>; + cooling-device = <&modem_mmw_skin0 2 2>; + }; + + mmw_skin0_cdev2 { + trip = <&mmw_pa3_trip2>; + cooling-device = <&modem_mmw_skin0 3 3>; + }; + }; + }; }; &apps_rsc { From 1846d1df62445be31a26d39f2658b8862f53c132 Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Thu, 22 Jul 2021 15:33:05 +0530 Subject: [PATCH 071/122] ARM: dts: msm: Add support of 608Mhz GPU FMAX for yupik Enable 608Mhz FMAX for yupik GPU as per speed bin requirement. Change-Id: I480d419ece2fa6b10e51f05e262e4f67a51122a8 --- qcom/yupik-gpu.dtsi | 72 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/qcom/yupik-gpu.dtsi b/qcom/yupik-gpu.dtsi index 6f028de05ae4..2161abdca3f9 100644 --- a/qcom/yupik-gpu.dtsi +++ b/qcom/yupik-gpu.dtsi @@ -465,6 +465,78 @@ qcom,acd-level = <0x882F5FFD>; }; }; + + qcom,gpu-pwrlevels-4 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <129>; + qcom,initial-pwrlevel = <3>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <608000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <10>; + qcom,bus-min-ddr7 = <9>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <8>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <10>; + + qcom,acd-level = <0x802B5FFD>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <550000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <9>; + qcom,bus-min-ddr7 = <8>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <6>; + qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0x802B5FFD>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <450000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <6>; + qcom,bus-min-ddr7 = <5>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <6>; + qcom,bus-max-ddr8 = <8>; + + qcom,acd-level = <0x802B5FFD>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <315000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <3>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <3>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882F5FFD>; + }; + }; }; }; From 7d7281735b9f10db2a600ba23977d7bfdcad63fa Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Wed, 19 May 2021 23:27:57 +0530 Subject: [PATCH 072/122] ARM: dts: qcom: Add modem mitigation for bcl violation in lahaina Add modem level 3 mitigation for bcl level 0 violation based on latest recommendation for lahaina. Increase passive delay for bcl thermal zones to delay clearing bcl mitigation. Change-Id: I50e7935c53511e5c47826a4252cfebd0e346c1f8 --- qcom/lahaina-thermal-overlay.dtsi | 50 ++++++++++++++++++------------- qcom/pm8350b.dtsi | 6 ++-- 2 files changed, 33 insertions(+), 23 deletions(-) diff --git a/qcom/lahaina-thermal-overlay.dtsi b/qcom/lahaina-thermal-overlay.dtsi index ce48bd0436ae..441b337bedcb 100644 --- a/qcom/lahaina-thermal-overlay.dtsi +++ b/qcom/lahaina-thermal-overlay.dtsi @@ -36,6 +36,16 @@ pm8350b-bcl-lvl0 { cooling-maps { + vbat_modem_l3 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_tj 3 3>; + }; + + vbat_gpu0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + vbat_cpu4 { trip = <&b_bcl_lvl0>; cooling-device = <&cpu4_isolate 1 1>; @@ -46,11 +56,6 @@ cooling-device = <&cpu5_isolate 1 1>; }; - vbat_gpu0 { - trip = <&b_bcl_lvl0>; - cooling-device = <&msm_gpu 2 2>; - }; - vbat_cdsp0 { trip = <&b_bcl_lvl0>; cooling-device = <&cdsp_sw 2 2>; @@ -60,6 +65,11 @@ pm8350b-bcl-lvl1 { cooling-maps { + vbat_gpu1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + vbat_cpu6 { trip = <&b_bcl_lvl1>; cooling-device = <&cpu6_isolate 1 1>; @@ -70,11 +80,6 @@ cooling-device = <&cpu7_isolate 1 1>; }; - vbat_gpu1 { - trip = <&b_bcl_lvl1>; - cooling-device = <&msm_gpu 4 4>; - }; - vbat_cdsp1 { trip = <&b_bcl_lvl1>; cooling-device = <&cdsp_sw 4 4>; @@ -101,6 +106,16 @@ pm8350c-bcl-lvl0 { disable-thermal-zone; cooling-maps { + vph_modem_l3 { + trip = <&c_bcl_lvl0>; + cooling-device = <&modem_tj 3 3>; + }; + + vph_gpu0 { + trip = <&c_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + vph_cpu4 { trip = <&c_bcl_lvl0>; cooling-device = <&cpu4_isolate 1 1>; @@ -111,11 +126,6 @@ cooling-device = <&cpu5_isolate 1 1>; }; - vph_gpu0 { - trip = <&c_bcl_lvl0>; - cooling-device = <&msm_gpu 2 2>; - }; - vph_cdsp0 { trip = <&c_bcl_lvl0>; cooling-device = <&cdsp_sw 2 2>; @@ -126,6 +136,11 @@ pm8350c-bcl-lvl1 { disable-thermal-zone; cooling-maps { + vph_gpu1 { + trip = <&c_bcl_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + vph_cpu6 { trip = <&c_bcl_lvl1>; cooling-device = <&cpu6_isolate 1 1>; @@ -136,11 +151,6 @@ cooling-device = <&cpu7_isolate 1 1>; }; - vph_gpu1 { - trip = <&c_bcl_lvl1>; - cooling-device = <&msm_gpu 4 4>; - }; - vph_cdsp1 { trip = <&c_bcl_lvl1>; cooling-device = <&cdsp_sw 4 4>; diff --git a/qcom/pm8350b.dtsi b/qcom/pm8350b.dtsi index f92738d71ad5..84578c7d4384 100644 --- a/qcom/pm8350b.dtsi +++ b/qcom/pm8350b.dtsi @@ -279,7 +279,7 @@ }; pm8350b-bcl-lvl0 { - polling-delay-passive = <100>; + polling-delay-passive = <500>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm8350b_bcl 5>; @@ -294,7 +294,7 @@ }; pm8350b-bcl-lvl1 { - polling-delay-passive = <100>; + polling-delay-passive = <500>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm8350b_bcl 6>; @@ -309,7 +309,7 @@ }; pm8350b-bcl-lvl2 { - polling-delay-passive = <100>; + polling-delay-passive = <500>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm8350b_bcl 7>; From ccfddb103c96319320a4554c749e9998e8090c32 Mon Sep 17 00:00:00 2001 From: Priyansh Jain Date: Thu, 24 Jun 2021 09:31:48 +0530 Subject: [PATCH 073/122] ARM: dts: msm: updating modem_tj mitigation for LAHAINA Remove modem_tj mitigation from cx_pe rule for LAHAINA. Change-Id: If889f43b5dbbf61278df717d1c6ec3a08a812cc1 --- qcom/lahaina-thermal.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi index 69d4886a81f6..4fadb7a87f45 100644 --- a/qcom/lahaina-thermal.dtsi +++ b/qcom/lahaina-thermal.dtsi @@ -1471,11 +1471,6 @@ cooling-device = <&cdsp_sw 3 3>; }; - cx_pe_cdev_4 { - trip = <&cx_pe_config4>; - cooling-device = <&modem_tj 1 1>; - }; - cx_pe_cdev_5 { trip = <&cx_pe_config5>; cooling-device = <&cdsp_sw 4 4>; From cc680960c338e48f865cf5f5833bde5077b0f06c Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Sun, 8 Aug 2021 23:32:40 +0530 Subject: [PATCH 074/122] ARM: dts: msm: Ignore SSR failure for wpss Add ignore_ssr_failure flag for wpss on Yupik platform. Change-Id: I4bf032157c3c3586cb3cac4e5dea56c30633471e --- qcom/yupik.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 779cd92d2f55..458ae1fc0cb8 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -4248,6 +4248,7 @@ qcom,smem-id = <626>; qcom,signal-aop; qcom,complete-ramdump; + qcom,ignore-ssr-failure; /* Inputs from wpss */ interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>, From 122a6a86f794e3cd3fbe760446dba54abc12472a Mon Sep 17 00:00:00 2001 From: Ramya SR Date: Wed, 24 Nov 2021 18:49:01 +0530 Subject: [PATCH 075/122] ARM: dts: qcom: Add of version register to figure out ntn3 version This change is to add version register to get the ntn3 switch version. Added two separate reg update sequence , one is reg update this is needed to keep NTN3v1 in gen3, this sequence is not needed in NTN3v2 as it is already taken care in v2 and another one is switch reg update this will update the gen3 preset value to both NTN3v1 and NTN3v2. Also added a optional force i2c settings flag to update the demphasis setting prior pcie linkup in dtsi binding irrespective of ntn3 chip version. Change-Id: Ibb249af5455c76e789931962f2cb9449d8814a42 --- bindings/pci/pci-msm.txt | 13 +++++++++++++ qcom/sdxlemur-mtp-cpe.dtsi | 7 ++++--- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index e80245821de0..fce9facfeada 100644 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -629,6 +629,17 @@ i2c child node Value Type: Array of Definition: List of slave registers to dump by i2c read +- version-reg: + Usage: optional + Value type: + Definition: Register to find ntn3 switch version + +- force-i2c-setting: + Usage: optional + Value type: + Definition: If force-i2c-setting flag is set + then de_emphasis settings are updated + irrespective of the chip version via i2c_writes ======= Example ======= @@ -641,5 +652,7 @@ Example ep-reset-reg = <0x801210>; ep-reset-gpio-mask = <0xf>; dump-regs = <0x801330 0x801350 0x801370>; + version-reg = <0x800000>; + force-i2c-setting; }; }; diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index dde1e97716da..065c77ad0a62 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -91,6 +91,7 @@ gpio-config-reg = <0x801208>; ep-reset-reg = <0x801210>; ep-reset-gpio-mask = <0xc>; + version-reg = <0x800000>; dump-regs = <0x801330 0x801350 0x801370>; reg_update = <0x82c030 0x1 0x828000 0x3 @@ -104,9 +105,9 @@ 0x82c01c 0x10 0x82c030 0xf 0x828000 0xf - 0x82b268 0x2 - 0x82C02C 0x4 - 0x8249DC 0x0>; + 0x82b268 0x2>; + switch_reg_update = <0x82C02C 0x4 + 0x824A0C 0x4>; }; }; From 893afca648372bdeb994b5eee10fee929a3154e5 Mon Sep 17 00:00:00 2001 From: Vignesh Viswanathan Date: Tue, 15 Feb 2022 12:59:20 +0530 Subject: [PATCH 076/122] ARM: dts: qcom: Fix board_id for QCN9000 in SDXLEMUR Fix board_id to pick the correct BDF files for QCN9000 in SDXLEMUR DTS. Change-Id: I3911d3126d30c2aeca39a11be7b887fba73d9a03 --- qcom/sdxlemur-mtp-cpe-pine1x.dtsi | 2 ++ qcom/sdxlemur-mtp-cpe-pine2x.dtsi | 4 +++- qcom/sdxlemur-qcn9000.dtsi | 2 -- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/qcom/sdxlemur-mtp-cpe-pine1x.dtsi b/qcom/sdxlemur-mtp-cpe-pine1x.dtsi index 305877ccd276..3d6851d7cc30 100644 --- a/qcom/sdxlemur-mtp-cpe-pine1x.dtsi +++ b/qcom/sdxlemur-mtp-cpe-pine1x.dtsi @@ -53,6 +53,8 @@ }; &wifi0 { + /* QCN9000 6G */ + board_id = <0xa4>; status = "ok"; }; diff --git a/qcom/sdxlemur-mtp-cpe-pine2x.dtsi b/qcom/sdxlemur-mtp-cpe-pine2x.dtsi index 2fc2b95bc75d..ca313b6e4178 100644 --- a/qcom/sdxlemur-mtp-cpe-pine2x.dtsi +++ b/qcom/sdxlemur-mtp-cpe-pine2x.dtsi @@ -64,11 +64,13 @@ }; &wifi0 { + /* QCN9000 5G with SBS filter */ status = "ok"; - board_id = <0xa0>; + board_id = <0xa3>; }; &wifi1 { + /* QCN9000 2G */ status = "ok"; board_id = <0xa1>; }; diff --git a/qcom/sdxlemur-qcn9000.dtsi b/qcom/sdxlemur-qcn9000.dtsi index d3ec2dcd34c0..af0da8be1fba 100644 --- a/qcom/sdxlemur-qcn9000.dtsi +++ b/qcom/sdxlemur-qcn9000.dtsi @@ -39,7 +39,6 @@ qrtr_node_id = <0x20>; qca,auto-restart; tgt-mem-mode = <0x1>; - board_id = <0xa4>; mhi,max-channels = <30>; mhi,timeout = <10000>; @@ -163,7 +162,6 @@ qrtr_node_id = <0x21>; qca,auto-restart; tgt-mem-mode = <0x1>; - board_id = <0xa4>; mhi,max-channels = <30>; mhi,timeout = <10000>; From d97b95981e3806ab9299b993e10803f569eb0812 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 2 Feb 2022 15:49:30 +0530 Subject: [PATCH 077/122] ARM: dts: msm: Add appropriate dtsi file for SDX+Pine Target Include the correct dtsi file for SDX+Pine target. Change-Id: Ia568891e458cd9d3890af01f9a5522193674dff1 --- qcom/sdxlemur-v2-mtp-cpe-pine1x.dts | 2 +- qcom/sdxlemur-v2-mtp-cpe-pine2x.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur-v2-mtp-cpe-pine1x.dts b/qcom/sdxlemur-v2-mtp-cpe-pine1x.dts index 8b0d1e19d836..f9b9f4cf7f00 100644 --- a/qcom/sdxlemur-v2-mtp-cpe-pine1x.dts +++ b/qcom/sdxlemur-v2-mtp-cpe-pine1x.dts @@ -3,7 +3,7 @@ #include "sdxlemur-v2.dtsi" #include "sdxlemur-mtp-cpe.dtsi" #include "sdxlemur-mtp-cpe-pine1x.dtsi" -#include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-1024mb-cpe.dtsi" #include "sdxlemur-bluetooth.dtsi" / { diff --git a/qcom/sdxlemur-v2-mtp-cpe-pine2x.dts b/qcom/sdxlemur-v2-mtp-cpe-pine2x.dts index 77b04077a9ff..21bbb7d4f4be 100644 --- a/qcom/sdxlemur-v2-mtp-cpe-pine2x.dts +++ b/qcom/sdxlemur-v2-mtp-cpe-pine2x.dts @@ -3,7 +3,7 @@ #include "sdxlemur-v2.dtsi" #include "sdxlemur-mtp-cpe.dtsi" #include "sdxlemur-mtp-cpe-pine2x.dtsi" -#include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-1024mb-cpe.dtsi" #include "sdxlemur-bluetooth.dtsi" / { From 95a9d5b65b23f667f7d7b2655390f2368615ad52 Mon Sep 17 00:00:00 2001 From: Ashish Bhimanpalliwar Date: Mon, 21 Feb 2022 12:05:02 +0530 Subject: [PATCH 078/122] ARM: dts: qcom: Add apq variant device tree support to Blair Add APQ variant device trees support for Blair. Change-Id: I10f716f061970b66570fbff6071632c8787954fb --- bindings/arm/msm/msm.txt | 7 ++++ qcom/Makefile | 25 +++++++++++++-- qcom/blairp-atp-overlay.dts | 44 +++++++++++++++++++++++++ qcom/blairp-atp.dts | 10 ++++++ qcom/blairp-atp.dtsi | 1 + qcom/blairp-cdp-overlay.dts | 16 ++++++++++ qcom/blairp-cdp.dts | 10 ++++++ qcom/blairp-cdp.dtsi | 1 + qcom/blairp-mtp-nopmi-overlay.dts | 14 ++++++++ qcom/blairp-mtp-nopmi.dts | 13 ++++++++ qcom/blairp-mtp-nopmi.dtsi | 2 ++ qcom/blairp-mtp-overlay.dts | 18 +++++++++++ qcom/blairp-mtp-usbc-overlay.dts | 53 +++++++++++++++++++++++++++++++ qcom/blairp-mtp-usbc.dts | 15 +++++++++ qcom/blairp-mtp-usbc.dtsi | 1 + qcom/blairp-mtp.dts | 17 ++++++++++ qcom/blairp-mtp.dtsi | 1 + qcom/blairp-qrd-nopmi-overlay.dts | 14 ++++++++ qcom/blairp-qrd-nopmi.dts | 13 ++++++++ qcom/blairp-qrd-nopmi.dtsi | 2 ++ qcom/blairp-qrd-overlay.dts | 18 +++++++++++ qcom/blairp-qrd.dts | 17 ++++++++++ qcom/blairp-qrd.dtsi | 1 + qcom/blairp.dts | 9 ++++++ qcom/blairp.dtsi | 9 ++++++ 25 files changed, 329 insertions(+), 2 deletions(-) create mode 100644 qcom/blairp-atp-overlay.dts create mode 100644 qcom/blairp-atp.dts create mode 100644 qcom/blairp-atp.dtsi create mode 100644 qcom/blairp-cdp-overlay.dts create mode 100644 qcom/blairp-cdp.dts create mode 100644 qcom/blairp-cdp.dtsi create mode 100644 qcom/blairp-mtp-nopmi-overlay.dts create mode 100644 qcom/blairp-mtp-nopmi.dts create mode 100644 qcom/blairp-mtp-nopmi.dtsi create mode 100644 qcom/blairp-mtp-overlay.dts create mode 100644 qcom/blairp-mtp-usbc-overlay.dts create mode 100644 qcom/blairp-mtp-usbc.dts create mode 100644 qcom/blairp-mtp-usbc.dtsi create mode 100644 qcom/blairp-mtp.dts create mode 100644 qcom/blairp-mtp.dtsi create mode 100644 qcom/blairp-qrd-nopmi-overlay.dts create mode 100644 qcom/blairp-qrd-nopmi.dts create mode 100644 qcom/blairp-qrd-nopmi.dtsi create mode 100644 qcom/blairp-qrd-overlay.dts create mode 100644 qcom/blairp-qrd.dts create mode 100644 qcom/blairp-qrd.dtsi create mode 100644 qcom/blairp.dts create mode 100644 qcom/blairp.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 013f38e3fe76..0cca021ae5f2 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -104,6 +104,9 @@ SoCs: - BLAIR compatible = "qcom,blair" +- BLAIRP + compatible = "qcom,blairp" + - MONACO compatible = "qcom,monaco" @@ -300,6 +303,10 @@ compatible = "qcom,blair-mtp" compatible = "qcom,blair-cdp" compatible = "qcom,blair-atp" compatible = "qcom,blair-qrd" +compatible = "qcom,blairp-mtp" +compatible = "qcom,blairp-cdp" +compatible = "qcom,blairp-atp" +compatible = "qcom,blairp-qrd" compatible = "qcom,scuba-idp" compatible = "qcom,monaco-rumi" compatible = "qcom,monaco" diff --git a/qcom/Makefile b/qcom/Makefile index cfe040cf7742..694208016e3c 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -150,7 +150,14 @@ dtbo-$(CONFIG_ARCH_BLAIR) += blair-rumi-overlay.dtbo \ blair-qrd-overlay.dtbo \ blair-mtp-usbc-overlay.dtbo \ blair-mtp-nopmi-overlay.dtbo \ - blair-qrd-nopmi-overlay.dtbo + blair-qrd-nopmi-overlay.dtbo \ + blairp-mtp-overlay.dtbo \ + blairp-cdp-overlay.dtbo \ + blairp-atp-overlay.dtbo \ + blairp-qrd-overlay.dtbo \ + blairp-mtp-usbc-overlay.dtbo \ + blairp-mtp-nopmi-overlay.dtbo \ + blairp-qrd-nopmi-overlay.dtbo blair-rumi-overlay.dtbo-base := blair.dtb blair-mtp-overlay.dtbo-base := blair.dtb @@ -160,6 +167,13 @@ blair-qrd-overlay.dtbo-base := blair.dtb blair-mtp-usbc-overlay.dtbo-base := blair.dtb blair-mtp-nopmi-overlay.dtbo-base := blair.dtb blair-qrd-nopmi-overlay.dtbo-base := blair.dtb +blairp-mtp-overlay.dtbo-base := blairp.dtb +blairp-cdp-overlay.dtbo-base := blairp.dtb +blairp-atp-overlay.dtbo-base := blairp.dtb +blairp-qrd-overlay.dtbo-base := blairp.dtb +blairp-mtp-usbc-overlay.dtbo-base := blairp.dtb +blairp-mtp-nopmi-overlay.dtbo-base := blairp.dtb +blairp-qrd-nopmi-overlay.dtbo-base := blairp.dtb else dtb-$(CONFIG_ARCH_BLAIR) += blair-rumi.dtb \ blair-mtp.dtb \ @@ -168,7 +182,14 @@ dtb-$(CONFIG_ARCH_BLAIR) += blair-rumi.dtb \ blair-qrd.dtb \ blair-mtp-usbc.dtb \ blair-mtp-nopmi.dtb \ - blair-qrd-nopmi.dtb + blair-qrd-nopmi.dtb \ + blairp-mtp.dtb \ + blairp-cdp.dtb \ + blairp-atp.dtb \ + blairp-qrd.dtb \ + blairp-mtp-usbc.dtb \ + blairp-mtp-nopmi.dtb \ + blairp-qrd-nopmi.dtb endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) diff --git a/qcom/blairp-atp-overlay.dts b/qcom/blairp-atp-overlay.dts new file mode 100644 index 000000000000..bb7b8787bdd3 --- /dev/null +++ b/qcom/blairp-atp-overlay.dts @@ -0,0 +1,44 @@ +/dts-v1/; +/plugin/; + +#include "blairp-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blairp ATP"; + compatible = "qcom,blairp-atp", "qcom,blairp", "qcom,atp"; + qcom,msm-id = <565 0x10000>; + qcom,board-id = <33 0>; +}; + +&wsa881x_i2c_e { + status = "disabled"; +}; + +&wsa881x_i2c_44 { + status = "disabled"; +}; + +&wcd937x_tx_slave { + status = "disabled"; +}; + +&wcd937x_rx_slave { + status = "disabled"; +}; + +&wcd937x_codec { + status = "disabled"; +}; + +&holi_snd { + qcom,wcd-disabled = <1>; + qcom,audio-routing = + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "VA SWR_INPUT", "VA_SWR_CLK", + "VA_AIF1 CAP", "VA_SWR_CLK", + "VA_AIF2 CAP", "VA_SWR_CLK", + "VA_AIF3 CAP", "VA_SWR_CLK"; +}; diff --git a/qcom/blairp-atp.dts b/qcom/blairp-atp.dts new file mode 100644 index 000000000000..f428a1ce4008 --- /dev/null +++ b/qcom/blairp-atp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "blairp.dtsi" +#include "blairp-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blairp ATP"; + compatible = "qcom,blairp-atp", "qcom,blairp", "qcom,atp"; + qcom,board-id = <33 0>; +}; diff --git a/qcom/blairp-atp.dtsi b/qcom/blairp-atp.dtsi new file mode 100644 index 000000000000..0655e61bdc13 --- /dev/null +++ b/qcom/blairp-atp.dtsi @@ -0,0 +1 @@ +#include "blair-atp.dtsi" diff --git a/qcom/blairp-cdp-overlay.dts b/qcom/blairp-cdp-overlay.dts new file mode 100644 index 000000000000..02704e07a2a9 --- /dev/null +++ b/qcom/blairp-cdp-overlay.dts @@ -0,0 +1,16 @@ +/dts-v1/; +/plugin/; + +#include "blairp-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blairp CDP"; + compatible = "qcom,blairp-cdp", "qcom,blairp", "qcom,cdp"; + qcom,msm-id = <565 0x10000>; + qcom,board-id = <1 0>; +}; + +&wsa881x_analog_reset_gpio { + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-1 = <&spkr_1_sd_n_sleep>; +}; diff --git a/qcom/blairp-cdp.dts b/qcom/blairp-cdp.dts new file mode 100644 index 000000000000..0b6e0547abf3 --- /dev/null +++ b/qcom/blairp-cdp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "blairp.dtsi" +#include "blairp-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blairp CDP"; + compatible = "qcom,blairp-cdp", "qcom,blairp", "qcom,cdp"; + qcom,board-id = <1 0>; +}; diff --git a/qcom/blairp-cdp.dtsi b/qcom/blairp-cdp.dtsi new file mode 100644 index 000000000000..048e3c5d9dd1 --- /dev/null +++ b/qcom/blairp-cdp.dtsi @@ -0,0 +1 @@ +#include "blair-cdp.dtsi" diff --git a/qcom/blairp-mtp-nopmi-overlay.dts b/qcom/blairp-mtp-nopmi-overlay.dts new file mode 100644 index 000000000000..58003066810b --- /dev/null +++ b/qcom/blairp-mtp-nopmi-overlay.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +#include "blairp-mtp-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blairp MTP NOPMI"; + compatible = "qcom,blairp-mtp", "qcom,blairp", "qcom,mtp"; + qcom,msm-id = <565 0x10000>; + qcom,board-id = <8 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; + diff --git a/qcom/blairp-mtp-nopmi.dts b/qcom/blairp-mtp-nopmi.dts new file mode 100644 index 000000000000..4f1cee09132a --- /dev/null +++ b/qcom/blairp-mtp-nopmi.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "blairp.dtsi" +#include "blairp-mtp-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blairp MTP NOPMI"; + compatible = "qcom,blairp-mtp", "qcom,blairp", "qcom,mtp"; + qcom,board-id = <8 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; + diff --git a/qcom/blairp-mtp-nopmi.dtsi b/qcom/blairp-mtp-nopmi.dtsi new file mode 100644 index 000000000000..684585a2fa27 --- /dev/null +++ b/qcom/blairp-mtp-nopmi.dtsi @@ -0,0 +1,2 @@ +#include "blair-mtp-nopmi.dtsi" + diff --git a/qcom/blairp-mtp-overlay.dts b/qcom/blairp-mtp-overlay.dts new file mode 100644 index 000000000000..37651c24ece1 --- /dev/null +++ b/qcom/blairp-mtp-overlay.dts @@ -0,0 +1,18 @@ +/dts-v1/; +/plugin/; + +#include "blairp-mtp.dtsi" +#include "holi-mtp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blairp MTP"; + compatible = "qcom,blairp-mtp", "qcom,blairp", "qcom,mtp"; + qcom,msm-id = <565 0x10000>; + qcom,board-id = <8 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x2E 0x0>; +}; + +&pm7250b_charger { + dpdm-supply = <&usb2_phy0>; +}; diff --git a/qcom/blairp-mtp-usbc-overlay.dts b/qcom/blairp-mtp-usbc-overlay.dts new file mode 100644 index 000000000000..8df452b841c0 --- /dev/null +++ b/qcom/blairp-mtp-usbc-overlay.dts @@ -0,0 +1,53 @@ +/dts-v1/; +/plugin/; + +#include "blairp-mtp-usbc.dtsi" +#include "holi-mtp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blairp MTP USBC audio"; + compatible = "qcom,blairp-mtp", "qcom,blairp", "qcom,mtp"; + qcom,msm-id = <565 0x10000>; + qcom,board-id = <8 1>; +}; + +&swr0 { + qcom,is_wcd937x = <0>; +}; + +&wcd937x_tx_slave { + status = "disabled"; +}; + +&wcd937x_rx_slave { + status = "disabled"; +}; + +&wcd937x_codec { + status = "disabled"; +}; + +&pm7250b_charger { + dpdm-supply = <&usb2_phy0>; +}; + +&wcd938x_tx_slave { + status = "ok"; +}; + +&wcd938x_rx_slave { + status = "ok"; +}; + +&wcd938x_codec { + status = "ok"; +}; + +&holi_snd { + asoc-codec = <&stub_codec>, <&bolero>, + <&wcd938x_codec>, <&wsa881x_i2c_e>, + <&wsa881x_i2c_f>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec", + "wcd938x_codec", "wsa-codec0", + "wsa-codec1"; +}; diff --git a/qcom/blairp-mtp-usbc.dts b/qcom/blairp-mtp-usbc.dts new file mode 100644 index 000000000000..4590d8e52055 --- /dev/null +++ b/qcom/blairp-mtp-usbc.dts @@ -0,0 +1,15 @@ +/dts-v1/; + +#include "blairp.dtsi" +#include "blairp-mtp-usbc.dtsi" +#include "holi-mtp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. BLAIRP MTP USBC audio"; + compatible = "qcom,blairp-mtp", "qcom,blairp", "qcom,mtp"; + qcom,board-id = <8 1>; +}; + +&pm7250b_charger { + dpdm-supply = <&usb2_phy0>; +}; diff --git a/qcom/blairp-mtp-usbc.dtsi b/qcom/blairp-mtp-usbc.dtsi new file mode 100644 index 000000000000..b90e9b1c0b19 --- /dev/null +++ b/qcom/blairp-mtp-usbc.dtsi @@ -0,0 +1 @@ +#include "blair-mtp-usbc.dtsi" diff --git a/qcom/blairp-mtp.dts b/qcom/blairp-mtp.dts new file mode 100644 index 000000000000..305dbd64a19e --- /dev/null +++ b/qcom/blairp-mtp.dts @@ -0,0 +1,17 @@ +/dts-v1/; + +#include "blairp.dtsi" +#include "blairp-mtp.dtsi" +#include "holi-mtp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blairp MTP"; + compatible = "qcom,blairp-mtp", "qcom,blairp", "qcom,mtp"; + qcom,board-id = <8 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x2E 0x0>; +}; + +&pm7250b_charger { + dpdm-supply = <&usb2_phy0>; +}; diff --git a/qcom/blairp-mtp.dtsi b/qcom/blairp-mtp.dtsi new file mode 100644 index 000000000000..b8622d186cf9 --- /dev/null +++ b/qcom/blairp-mtp.dtsi @@ -0,0 +1 @@ +#include "blair-mtp.dtsi" diff --git a/qcom/blairp-qrd-nopmi-overlay.dts b/qcom/blairp-qrd-nopmi-overlay.dts new file mode 100644 index 000000000000..d3a8ca2f0c0b --- /dev/null +++ b/qcom/blairp-qrd-nopmi-overlay.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +#include "blairp-qrd-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blairp QRD NOPMI"; + compatible = "qcom,blairp-qrd", "qcom,blairp", "qcom,qrd"; + qcom,msm-id = <565 0x10000>; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; + diff --git a/qcom/blairp-qrd-nopmi.dts b/qcom/blairp-qrd-nopmi.dts new file mode 100644 index 000000000000..64cac8f5ccf5 --- /dev/null +++ b/qcom/blairp-qrd-nopmi.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "blairp.dtsi" +#include "blairp-qrd-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blairp QRD NOPMI"; + compatible = "qcom,blairp-qrd", "qcom,blairp", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; + diff --git a/qcom/blairp-qrd-nopmi.dtsi b/qcom/blairp-qrd-nopmi.dtsi new file mode 100644 index 000000000000..c1ab5e75c7fb --- /dev/null +++ b/qcom/blairp-qrd-nopmi.dtsi @@ -0,0 +1,2 @@ +#include "blair-qrd-nopmi.dtsi" + diff --git a/qcom/blairp-qrd-overlay.dts b/qcom/blairp-qrd-overlay.dts new file mode 100644 index 000000000000..40c9baef8462 --- /dev/null +++ b/qcom/blairp-qrd-overlay.dts @@ -0,0 +1,18 @@ +/dts-v1/; +/plugin/; + +#include "blairp-qrd.dtsi" +#include "holi-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blairp QRD"; + compatible = "qcom,blairp-qrd", "qcom,blairp", "qcom,qrd"; + qcom,msm-id = <565 0x10000>; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x2E 0x0>; +}; + +&pm7250b_charger { + dpdm-supply = <&usb2_phy0>; +}; diff --git a/qcom/blairp-qrd.dts b/qcom/blairp-qrd.dts new file mode 100644 index 000000000000..7f4730b19a02 --- /dev/null +++ b/qcom/blairp-qrd.dts @@ -0,0 +1,17 @@ +/dts-v1/; + +#include "blairp.dtsi" +#include "blairp-qrd.dtsi" +#include "holi-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blairp QRD"; + compatible = "qcom,blairp-qrd", "qcom,blairp", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id-size = <4>; + qcom,pmic-id = <0x2D 0x0 0x2E 0x0>; +}; + +&pm7250b_charger { + dpdm-supply = <&usb2_phy0>; +}; diff --git a/qcom/blairp-qrd.dtsi b/qcom/blairp-qrd.dtsi new file mode 100644 index 000000000000..b35b4131b743 --- /dev/null +++ b/qcom/blairp-qrd.dtsi @@ -0,0 +1 @@ +#include "blair-qrd.dtsi" diff --git a/qcom/blairp.dts b/qcom/blairp.dts new file mode 100644 index 000000000000..0377d012c7c4 --- /dev/null +++ b/qcom/blairp.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "blairp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blairp SoC"; + compatible = "qcom,blairp"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/blairp.dtsi b/qcom/blairp.dtsi new file mode 100644 index 000000000000..ebdbccee7d06 --- /dev/null +++ b/qcom/blairp.dtsi @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "blair.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blairp SoC"; + compatible = "qcom,blairp"; + qcom,msm-id = <565 0x10000>; +}; From 21e8c52dfc4a241fdec017c5d19012dbf0d3c349 Mon Sep 17 00:00:00 2001 From: Jagadeesh Ponduru Date: Fri, 25 Feb 2022 18:21:54 +0530 Subject: [PATCH 079/122] ARM: dts: msm: disable IPA entry for blair APQ targets Change to disable IPA through dtsi file for blairp target. Change-Id: I0a081cfeb3ecd1522415e4031bae2d55d5d2ec38 --- qcom/blairp.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/qcom/blairp.dtsi b/qcom/blairp.dtsi index ebdbccee7d06..c446a1e4d67d 100644 --- a/qcom/blairp.dtsi +++ b/qcom/blairp.dtsi @@ -7,3 +7,22 @@ compatible = "qcom,blairp"; qcom,msm-id = <565 0x10000>; }; + +&soc { + qcom,msm_gsi { + status = "disabled"; + }; + + qcom,rmnet-ipa { + status = "disabled"; + }; + + qcom,ipa_fws { + status = "disabled"; + }; + + ipa_hw: qcom,ipa@0x5800000 { + status = "disabled"; + }; + +}; From 169992e806c3b6588edbc8bbc09ac5175b65d053 Mon Sep 17 00:00:00 2001 From: Ramya SR Date: Mon, 21 Feb 2022 12:52:58 +0530 Subject: [PATCH 080/122] ARM: dts: qcom: Settings for change calculation of FoM for preset This change is add settings for change calculation of FoM for preset Change-Id: I64a7be0473ad9fd8f100252df40e986e18a5c756 --- qcom/sdxlemur-mtp-cpe.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index 065c77ad0a62..6e9f0048d3e1 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -106,8 +106,13 @@ 0x82c030 0xf 0x828000 0xf 0x82b268 0x2>; - switch_reg_update = <0x82C02C 0x4 - 0x824A0C 0x4>; + /*FOM for preset caluclation*/ + switch_reg_update = <0x82c02c 0x00000007 + 0x824a10 0x00000001 + 0x82c030 0x00000008 + 0x828000 0x00000001 + 0x82b074 0x00000020 + 0x82b2bc 0x00000001>; }; }; From fac15fc1dcff56ccf4fb8e9d59b708e7edbd76b5 Mon Sep 17 00:00:00 2001 From: Priyansh Jain Date: Mon, 7 Mar 2022 18:02:56 +0530 Subject: [PATCH 081/122] ARM: dts: qcom: Change modem Tj thresholds for sdxlemur Change modem Tj threshold based on latest recommendation. Change-Id: I30cd3d95f626fca94a195011ec87484c74168550 --- qcom/sdxlemur-thermal.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/qcom/sdxlemur-thermal.dtsi b/qcom/sdxlemur-thermal.dtsi index 5ca372177e6d..150c060358e8 100644 --- a/qcom/sdxlemur-thermal.dtsi +++ b/qcom/sdxlemur-thermal.dtsi @@ -67,14 +67,14 @@ thermal-sensors = <&tsens0 3>; trips { mdmss0_config0: mdmss0-config0 { - temperature = <111000>; + temperature = <101000>; hysteresis = <3000>; type = "passive"; }; mdmss0_config1: mdmss0-config1 { - temperature = <115000>; - hysteresis = <2000>; + temperature = <105000>; + hysteresis = <3000>; type = "passive"; }; }; @@ -87,14 +87,14 @@ thermal-sensors = <&tsens0 4>; trips { mdmss1_config0: mdmss1-config0 { - temperature = <111000>; + temperature = <101000>; hysteresis = <3000>; type = "passive"; }; mdmss1_config1: mdmss1-config1 { - temperature = <115000>; - hysteresis = <2000>; + temperature = <105000>; + hysteresis = <3000>; type = "passive"; }; }; @@ -134,14 +134,14 @@ thermal-sensors = <&tsens0 5>; trips { mdmss2_config0: mdmss2-config0 { - temperature = <111000>; + temperature = <101000>; hysteresis = <3000>; type = "passive"; }; mdmss2_config1: mdmss2-config1 { - temperature = <115000>; - hysteresis = <2000>; + temperature = <105000>; + hysteresis = <3000>; type = "passive"; }; }; @@ -154,14 +154,14 @@ thermal-sensors = <&tsens0 6>; trips { mdmss3_config0: mdmss3-config0 { - temperature = <111000>; + temperature = <101000>; hysteresis = <3000>; type = "passive"; }; mdmss3_config1: mdmss3-config1 { - temperature = <115000>; - hysteresis = <2000>; + temperature = <105000>; + hysteresis = <3000>; type = "passive"; }; }; From 855fc16ae022757efad71fc932c2334b1934e2b5 Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Wed, 9 Mar 2022 15:25:53 +0530 Subject: [PATCH 082/122] ARM: dts: msm: Updating right AB/IB vote as per new frequency plan Updating right AB/IB vote as per new frequency plan Change-Id: I78ce2cafa07b022bfb4b302fdd68dd48f824a01b --- qcom/sdxlemur.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 3ffb3e2dd6f1..515b1ac6512d 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1229,19 +1229,19 @@ /* SVS2 */ qcom,svs2 = - <600000 0 600000 1900000 0 76800>; + <18000 0 600000 1900000 0 76800>; /* SVS */ qcom,svs = - <1200000 0 1200000 2800000 0 150000>; + <400000 0 1200000 2800000 0 150000>; /* NOMINAL */ qcom,nominal = - <2400000 0 2400000 5500000 0 400000>; + <670000 0 2400000 5500000 0 400000>; /* TURBO */ qcom,turbo = - <3600000 0 3600000 5500000 0 400000>; + <1380000 0 3600000 5500000 0 400000>; qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; From 074319e2dced255aa6a2ba0bbae3239f1a209a1f Mon Sep 17 00:00:00 2001 From: Sandeep Singh Date: Wed, 2 Mar 2022 12:03:22 +0530 Subject: [PATCH 083/122] ARM: dts: msm: Disable ipa from wlan side for blair apq IPA needs to be disabled for blair apq as IPA hw is not present for apq targets. Change-Id: I4dadc80fb655504d018085ee25786bf2990df613 --- bindings/cnss/cnss-wlan.txt | 2 ++ qcom/blairp.dtsi | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/bindings/cnss/cnss-wlan.txt b/bindings/cnss/cnss-wlan.txt index 7be180ac82b5..1c3cf34581f6 100644 --- a/bindings/cnss/cnss-wlan.txt +++ b/bindings/cnss/cnss-wlan.txt @@ -54,6 +54,8 @@ Optional properties: load in uA and Regulator settle delay in us - qcom,smmu-s1-enable: Boolean property to decide whether to enable SMMU S1 stage or not + - wlan-ipa-disabled: Boolean property to decide whether IPA is disabled + or not - qcom,wlan-smmu-iova-address: I/O virtual address range as format to be used for allocations associated between WLAN/PCIe and SMMU diff --git a/qcom/blairp.dtsi b/qcom/blairp.dtsi index c446a1e4d67d..192f3b55e620 100644 --- a/qcom/blairp.dtsi +++ b/qcom/blairp.dtsi @@ -25,4 +25,8 @@ status = "disabled"; }; + icnss: qcom,icnss@C800000 { + wlan-ipa-disabled; + }; + }; From 3e4324be6577249a3901deff68421b7461b5313f Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Thu, 20 Jan 2022 17:50:46 +0800 Subject: [PATCH 084/122] ARM: dts: msm: switch qdss usb to sw path Switch qdss usb to sw path on sdxlemur. Change-Id: Ie27ae273b535801729499fac008df002c472c7e6 --- qcom/sdxlemur-coresight.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxlemur-coresight.dtsi b/qcom/sdxlemur-coresight.dtsi index 60efffb4855e..f4ff5cd3e7fd 100644 --- a/qcom/sdxlemur-coresight.dtsi +++ b/qcom/sdxlemur-coresight.dtsi @@ -147,6 +147,7 @@ arm,buffer-size = <0x400000>; arm,scatter-gather; + qcom,sw-usb; qcom,qdss-ipa-support; ipa-conn-data-base-pa = <0x1468B000>; From f2e816bcb5cc68c5e1ab67af462645d357b9b08f Mon Sep 17 00:00:00 2001 From: Ramya SR Date: Mon, 4 Apr 2022 21:47:51 +0530 Subject: [PATCH 085/122] ARM: dts: qcom: Add EP reset post link-up flag for pine This change is to add a flag to reset the pine EP post link-up. Change-Id: I01ef2fd3790b270180166924dcfbfe36aeaee099 --- qcom/sdxlemur-mtp-cpe-pine1x.dtsi | 1 + qcom/sdxlemur-mtp-cpe-pine2x.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe-pine1x.dtsi b/qcom/sdxlemur-mtp-cpe-pine1x.dtsi index 3d6851d7cc30..38eee1a933e8 100644 --- a/qcom/sdxlemur-mtp-cpe-pine1x.dtsi +++ b/qcom/sdxlemur-mtp-cpe-pine1x.dtsi @@ -37,6 +37,7 @@ }; &pcie_i2c_ctrl { + ep_reset_postlinkup; reg_update = <0x82c030 0x1 0x828000 0x3 0x82bd00 0x8 diff --git a/qcom/sdxlemur-mtp-cpe-pine2x.dtsi b/qcom/sdxlemur-mtp-cpe-pine2x.dtsi index ca313b6e4178..ac102dfe643b 100644 --- a/qcom/sdxlemur-mtp-cpe-pine2x.dtsi +++ b/qcom/sdxlemur-mtp-cpe-pine2x.dtsi @@ -17,6 +17,7 @@ }; &pcie_i2c_ctrl { + ep_reset_postlinkup; reg_update = <0x82c030 0x1 0x828000 0x3 0x82bd00 0x8 From 20541ffa35ea2014730e39ee96bb6f561d799374 Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Fri, 29 Apr 2022 15:08:33 +0530 Subject: [PATCH 086/122] ARM: dts: msm: Update the LLC node AB value without modem Previously shared AB values by clocks team depended on modem vote, Updating right AB value for LLC node without depending on modem vote. Change-Id: Iab92f6e646b41edd8bdcebe11638471b1fddf5d2 --- qcom/sdxlemur.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 515b1ac6512d..bdde1284b724 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1229,19 +1229,19 @@ /* SVS2 */ qcom,svs2 = - <18000 0 600000 1900000 0 76800>; + <50000 0 600000 1900000 0 76800>; /* SVS */ qcom,svs = - <400000 0 1200000 2800000 0 150000>; + <490000 0 1200000 2800000 0 150000>; /* NOMINAL */ qcom,nominal = - <670000 0 2400000 5500000 0 400000>; + <800000 0 2400000 5500000 0 400000>; /* TURBO */ qcom,turbo = - <1380000 0 3600000 5500000 0 400000>; + <1600000 0 3600000 5500000 0 400000>; qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; From f201ff7cb5be1282e6effc7dcf98a3f7e16200db Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Thu, 26 May 2022 12:45:34 +0530 Subject: [PATCH 087/122] ARM: dts: msm: Updating right DDR AB/IB voting values With current AB/IB values not meeting expected tput in concurrent scenario. Adding changes to use right AB/IB votes for DDR to meet tput requirements. Change-Id: I21f02c5ae5e793d54e5669cfe375fb5b391721b2 --- qcom/sdxlemur.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index bdde1284b724..82def0a0d2e1 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1229,19 +1229,19 @@ /* SVS2 */ qcom,svs2 = - <50000 0 600000 1900000 0 76800>; + <780000 0 1300000 1800000 0 76800>; /* SVS */ qcom,svs = - <490000 0 1200000 2800000 0 150000>; + <1290000 0 2160000 3000000 0 150000>; /* NOMINAL */ qcom,nominal = - <800000 0 2400000 5500000 0 400000>; + <2820000 0 4300000 6000000 0 400000>; /* TURBO */ qcom,turbo = - <1600000 0 3600000 5500000 0 400000>; + <3480000 0 6900000 9600000 0 400000>; qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; From 049fe5107af74c66bb8773a1b40d772a18e85432 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Fri, 27 May 2022 12:43:16 +0530 Subject: [PATCH 088/122] ARM: dts: msm: Add additional v2 variant for sdxlemur board Add additional v2 variant for sdxlemur board. Change-Id: I570245d691c9db6b2842f9c173b65869e6c8447c --- qcom/Makefile | 3 ++- qcom/sdxlemur-v2-mtp-cpe-pine2x-5+6.dts | 13 +++++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) create mode 100644 qcom/sdxlemur-v2-mtp-cpe-pine2x-5+6.dts diff --git a/qcom/Makefile b/qcom/Makefile index 694208016e3c..d6920dea3bc6 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -475,7 +475,8 @@ dtb-$(CONFIG_ARCH_SDXLEMUR) += sdxlemur-rumi.dtb \ sdxlemur-v2-mtp-mbb-m2-ep.dtb \ sdxlemur-v2-rcm-rc-pine1x.dtb \ sdxlemur-v2-rcm-rc-pine2x.dtb \ - sdxlemur-v2-m2-ep-fwa.dtb + sdxlemur-v2-m2-ep-fwa.dtb \ + sdxlemur-v2-mtp-cpe-pine2x-5+6.dtb diff --git a/qcom/sdxlemur-v2-mtp-cpe-pine2x-5+6.dts b/qcom/sdxlemur-v2-mtp-cpe-pine2x-5+6.dts new file mode 100644 index 000000000000..8a1cfd0d5b0c --- /dev/null +++ b/qcom/sdxlemur-v2-mtp-cpe-pine2x-5+6.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "sdxlemur-v2.dtsi" +#include "sdxlemur-mtp-cpe.dtsi" +#include "sdxlemur-mtp-cpe-pine2x.dtsi" +#include "sdxlemur-1024mb-cpe.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE 2x Pine V2 5+6 Configuration"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x12010008 0x312>; +}; From 4bd1d87012c4394e3bae048cd0b21d6b64507240 Mon Sep 17 00:00:00 2001 From: Piyush Dhyani Date: Fri, 3 Jun 2022 19:25:32 +0530 Subject: [PATCH 089/122] ARM: dts: msm: Add dtsi entry for dual pine Add dtsi entry for dual pine config for IPA. Change-Id: I73354a6be1622584c19881be4e74b440d2ae57f6 --- qcom/sdxlemur-mtp-cpe-pine2x.dts | 5 +++++ qcom/sdxlemur-v2-mtp-cpe-pine2x.dts | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe-pine2x.dts b/qcom/sdxlemur-mtp-cpe-pine2x.dts index 705c9b4cb1dd..bac797bbdba5 100644 --- a/qcom/sdxlemur-mtp-cpe-pine2x.dts +++ b/qcom/sdxlemur-mtp-cpe-pine2x.dts @@ -12,3 +12,8 @@ "qcom,sdxlemur", "qcom,mtp"; qcom,board-id = <0xA010008 0x30A>; }; + +&ipa_hw { + qcom,use-dual-pine-config; +}; + diff --git a/qcom/sdxlemur-v2-mtp-cpe-pine2x.dts b/qcom/sdxlemur-v2-mtp-cpe-pine2x.dts index 21bbb7d4f4be..fab16854eaad 100644 --- a/qcom/sdxlemur-v2-mtp-cpe-pine2x.dts +++ b/qcom/sdxlemur-v2-mtp-cpe-pine2x.dts @@ -12,3 +12,8 @@ "qcom,sdxlemur", "qcom,mtp"; qcom,board-id = <0xA010008 0x30A>; }; + +&ipa_hw { + qcom,use-dual-pine-config; +}; + From 28e9e379a7f16929af308628db34b31f2b95d69e Mon Sep 17 00:00:00 2001 From: Anil Veshala Veshala Date: Wed, 30 Mar 2022 05:36:08 -0700 Subject: [PATCH 090/122] ARM: dts: msm: add rtl based flag Added dt entry for rtl based SE's. Change-Id: I065c567082b9b7b28879c4da396d3949c354f3c2 --- qcom/holi-qupv3.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/holi-qupv3.dtsi b/qcom/holi-qupv3.dtsi index 3376a25d47cc..cbc8be21fa8a 100644 --- a/qcom/holi-qupv3.dtsi +++ b/qcom/holi-qupv3.dtsi @@ -158,6 +158,7 @@ <&gpi_dma0 1 2 3 64 0>; dma-names = "tx", "rx"; qcom,wrapper-core = <&qupv3_0>; + qcom,rtl_se; status = "disabled"; }; @@ -241,6 +242,7 @@ <&gpi_dma1 1 0 3 64 0>; dma-names = "tx", "rx"; qcom,wrapper-core = <&qupv3_1>; + qcom,rtl_se; status = "disabled"; }; @@ -283,6 +285,7 @@ <&gpi_dma1 1 1 3 64 0>; dma-names = "tx", "rx"; qcom,wrapper-core = <&qupv3_1>; + qcom,rtl_se; status = "disabled"; }; @@ -303,6 +306,7 @@ <&gpi_dma1 1 2 3 64 0>; dma-names = "tx", "rx"; qcom,wrapper-core = <&qupv3_1>; + qcom,rtl_se; status = "disabled"; }; From 89be46d5a210a27582e101496a07378c059d255d Mon Sep 17 00:00:00 2001 From: Dishendra Deshmukh Date: Fri, 22 Apr 2022 12:45:46 +0530 Subject: [PATCH 091/122] ARM: dts: msm: Add support for Katmai targets Add support for Katmai platform on all supported variant of Yupik and Yupikp. Change-Id: Ia82db0a6602573b9c6b1b512848e9aeeacded14a --- qcom/Makefile | 38 ++++++++++++++++--------- qcom/katmai-hsp-pm7250b.dts | 10 +++++++ qcom/katmai-hsp.dts | 10 +++++++ qcom/katmai-idp-pm7250b.dts | 10 +++++++ qcom/katmai-idp.dts | 10 +++++++ qcom/katmai-idps-amoled.dts | 10 +++++++ qcom/katmai-qrd.dts | 10 +++++++ qcom/katmai.dts | 9 ++++++ qcom/katmai.dtsi | 7 +++++ qcom/katmaip-hsp-pm7250b.dts | 10 +++++++ qcom/katmaip-hsp.dts | 10 +++++++ qcom/katmaip-idp-pm7250b.dts | 10 +++++++ qcom/katmaip-idp.dts | 10 +++++++ qcom/katmaip-idps-amoled.dts | 10 +++++++ qcom/katmaip-qrd.dts | 10 +++++++ qcom/katmaip.dts | 9 ++++++ qcom/katmaip.dtsi | 17 +++++++++++ qcom/yupik-iot-hsp-overlay.dts | 2 +- qcom/yupik-iot-hsp-pm7250b-overlay.dts | 2 +- qcom/yupik-iot-idp-overlay.dts | 2 +- qcom/yupik-iot-idp-pm7250b-overlay.dts | 2 +- qcom/yupik-iot-idps-amoled-overlay.dts | 2 +- qcom/yupik-iot-qrd-overlay.dts | 2 +- qcom/yupikp-iot-hsp-overlay.dts | 2 +- qcom/yupikp-iot-hsp-pm7250b-overlay.dts | 2 +- qcom/yupikp-iot-idp-overlay.dts | 2 +- qcom/yupikp-iot-idp-pm7250b-overlay.dts | 2 +- qcom/yupikp-iot-idps-amoled-overlay.dts | 2 +- qcom/yupikp-iot-qrd-overlay.dts | 2 +- 29 files changed, 199 insertions(+), 25 deletions(-) create mode 100644 qcom/katmai-hsp-pm7250b.dts create mode 100644 qcom/katmai-hsp.dts create mode 100644 qcom/katmai-idp-pm7250b.dts create mode 100644 qcom/katmai-idp.dts create mode 100644 qcom/katmai-idps-amoled.dts create mode 100644 qcom/katmai-qrd.dts create mode 100644 qcom/katmai.dts create mode 100644 qcom/katmai.dtsi create mode 100644 qcom/katmaip-hsp-pm7250b.dts create mode 100644 qcom/katmaip-hsp.dts create mode 100644 qcom/katmaip-idp-pm7250b.dts create mode 100644 qcom/katmaip-idp.dts create mode 100644 qcom/katmaip-idps-amoled.dts create mode 100644 qcom/katmaip-qrd.dts create mode 100644 qcom/katmaip.dts create mode 100644 qcom/katmaip.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 694208016e3c..4771e3f0a50b 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -259,18 +259,18 @@ yupikp-atp-overlay.dtbo-base := yupikp.dtb yupikp-qrd-overlay.dtbo-base := yupikp.dtb yupikp-idps-amoled-overlay.dtbo-base := yupikp.dtb yupikp-idp-hsp-overlay.dtbo-base := yupikp-hsp.dtb -yupik-iot-idp-overlay.dtbo-base := yupik-iot.dtb -yupik-iot-idp-pm7250b-overlay.dtbo-base := yupik-iot.dtb -yupik-iot-qrd-overlay.dtbo-base := yupik-iot.dtb -yupik-iot-hsp-overlay.dtbo-base := yupik-iot.dtb -yupik-iot-hsp-pm7250b-overlay.dtbo-base := yupik-iot.dtb -yupik-iot-idps-amoled-overlay.dtbo-base := yupik-iot.dtb -yupikp-iot-idp-overlay.dtbo-base := yupikp-iot.dtb -yupikp-iot-idp-pm7250b-overlay.dtbo-base := yupikp-iot.dtb -yupikp-iot-qrd-overlay.dtbo-base := yupikp-iot.dtb -yupikp-iot-hsp-overlay.dtbo-base := yupikp-iot.dtb -yupikp-iot-hsp-pm7250b-overlay.dtbo-base := yupikp-iot.dtb -yupikp-iot-idps-amoled-overlay.dtbo-base := yupikp-iot.dtb +yupik-iot-idp-overlay.dtbo-base := yupik-iot.dtb katmai.dtb +yupik-iot-idp-pm7250b-overlay.dtbo-base := yupik-iot.dtb katmai.dtb +yupik-iot-qrd-overlay.dtbo-base := yupik-iot.dtb katmai.dtb +yupik-iot-hsp-overlay.dtbo-base := yupik-iot.dtb katmai.dtb +yupik-iot-hsp-pm7250b-overlay.dtbo-base := yupik-iot.dtb katmai.dtb +yupik-iot-idps-amoled-overlay.dtbo-base := yupik-iot.dtb katmai.dtb +yupikp-iot-idp-overlay.dtbo-base := yupikp-iot.dtb katmaip.dtb +yupikp-iot-idp-pm7250b-overlay.dtbo-base := yupikp-iot.dtb katmaip.dtb +yupikp-iot-qrd-overlay.dtbo-base := yupikp-iot.dtb katmaip.dtb +yupikp-iot-hsp-overlay.dtbo-base := yupikp-iot.dtb katmaip.dtb +yupikp-iot-hsp-pm7250b-overlay.dtbo-base := yupikp-iot.dtb katmaip.dtb +yupikp-iot-idps-amoled-overlay.dtbo-base := yupikp-iot.dtb katmaip.dtb else dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb \ yupik-idp.dtb \ @@ -295,7 +295,19 @@ dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb \ yupikp-iot-hsp.dtb \ yupik-iot-hsp-pm7250b.dtb \ yupikp-iot-hsp-pm7250b.dtb \ - yupikp-iot-idps-amoled.dtb + yupikp-iot-idps-amoled.dtb \ + katmai-idp.dtb \ + katmai-idp-pm7250b.dtb \ + katmai-qrd.dtb \ + katmai-hsp.dtb \ + katmai-idps-amoled.dtb \ + katmaip-idp.dtb \ + katmaip-idp-pm7250b.dtb \ + katmaip-qrd.dtb \ + katmaip-hsp.dtb \ + katmai-hsp-pm7250b.dtb \ + katmaip-hsp-pm7250b.dtb \ + katmaip-idps-amoled.dtb endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) diff --git a/qcom/katmai-hsp-pm7250b.dts b/qcom/katmai-hsp-pm7250b.dts new file mode 100644 index 000000000000..248750ebe660 --- /dev/null +++ b/qcom/katmai-hsp-pm7250b.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "katmai.dtsi" +#include "yupik-iot-hsp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Katmai HSP + PM7250B"; + compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; + qcom,board-id = <34 1>; +}; diff --git a/qcom/katmai-hsp.dts b/qcom/katmai-hsp.dts new file mode 100644 index 000000000000..9aaf17c0d01c --- /dev/null +++ b/qcom/katmai-hsp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "katmai.dtsi" +#include "yupik-iot-hsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Katmai HSP"; + compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; + qcom,board-id = <34 1>; +}; diff --git a/qcom/katmai-idp-pm7250b.dts b/qcom/katmai-idp-pm7250b.dts new file mode 100644 index 000000000000..c8d237d79fe8 --- /dev/null +++ b/qcom/katmai-idp-pm7250b.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "katmai.dtsi" +#include "yupik-iot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Katmai IDP + PM7250B"; + compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/katmai-idp.dts b/qcom/katmai-idp.dts new file mode 100644 index 000000000000..9d9b2fb29bb8 --- /dev/null +++ b/qcom/katmai-idp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "katmai.dtsi" +#include "yupik-iot-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KATMAI IDP"; + compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/katmai-idps-amoled.dts b/qcom/katmai-idps-amoled.dts new file mode 100644 index 000000000000..7acdcc48cf59 --- /dev/null +++ b/qcom/katmai-idps-amoled.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "katmai.dtsi" +#include "yupik-iot-idps-amoled.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KATMAI IDPS + AMOLED"; + compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/katmai-qrd.dts b/qcom/katmai-qrd.dts new file mode 100644 index 000000000000..5ea9050346fc --- /dev/null +++ b/qcom/katmai-qrd.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "katmai.dtsi" +#include "yupik-iot-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KATMAI QRD"; + compatible = "qcom,yupik-iot-qrd", "qcom,yupik-iot", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/katmai.dts b/qcom/katmai.dts new file mode 100644 index 000000000000..0769778f40a6 --- /dev/null +++ b/qcom/katmai.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "katmai.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KATMAI SoC"; + compatible = "qcom,yupik-iot"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/katmai.dtsi b/qcom/katmai.dtsi new file mode 100644 index 000000000000..4b1667a64079 --- /dev/null +++ b/qcom/katmai.dtsi @@ -0,0 +1,7 @@ +#include "yupik-iot.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KATMAI SoC"; + compatible = "qcom,yupik-iot"; + qcom,msm-id = <576 0x10000>; +}; diff --git a/qcom/katmaip-hsp-pm7250b.dts b/qcom/katmaip-hsp-pm7250b.dts new file mode 100644 index 000000000000..2eccc09194f2 --- /dev/null +++ b/qcom/katmaip-hsp-pm7250b.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "katmaip.dtsi" +#include "yupikp-iot-hsp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KatmaiP HSP + PM7250B"; + compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; + qcom,board-id = <34 1>; +}; diff --git a/qcom/katmaip-hsp.dts b/qcom/katmaip-hsp.dts new file mode 100644 index 000000000000..8e0ad391069d --- /dev/null +++ b/qcom/katmaip-hsp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "katmaip.dtsi" +#include "yupikp-iot-hsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KatmaiP HSP"; + compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; + qcom,board-id = <34 1>; +}; diff --git a/qcom/katmaip-idp-pm7250b.dts b/qcom/katmaip-idp-pm7250b.dts new file mode 100644 index 000000000000..74314dfdb779 --- /dev/null +++ b/qcom/katmaip-idp-pm7250b.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "katmaip.dtsi" +#include "yupikp-iot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KatmaiP IDP + PM7250B"; + compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/katmaip-idp.dts b/qcom/katmaip-idp.dts new file mode 100644 index 000000000000..e1697a341ed5 --- /dev/null +++ b/qcom/katmaip-idp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "katmaip.dtsi" +#include "yupikp-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KATMAIP IDP"; + compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/katmaip-idps-amoled.dts b/qcom/katmaip-idps-amoled.dts new file mode 100644 index 000000000000..60289858a9b8 --- /dev/null +++ b/qcom/katmaip-idps-amoled.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "katmaip.dtsi" +#include "yupikp-iot-idps-amoled.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KATMAIP IDPS + AMOLED"; + compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/katmaip-qrd.dts b/qcom/katmaip-qrd.dts new file mode 100644 index 000000000000..41048d9a7aa7 --- /dev/null +++ b/qcom/katmaip-qrd.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "katmaip.dtsi" +#include "yupikp-iot-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KATMAIP QRD"; + compatible = "qcom,yupikp-iot-qrd", "qcom,yupikp-iot", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/katmaip.dts b/qcom/katmaip.dts new file mode 100644 index 000000000000..73cd145a60ef --- /dev/null +++ b/qcom/katmaip.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "katmaip.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KATMAIP SoC"; + compatible = "qcom,yupikp-iot"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/katmaip.dtsi b/qcom/katmaip.dtsi new file mode 100644 index 000000000000..bcc2e8e9af54 --- /dev/null +++ b/qcom/katmaip.dtsi @@ -0,0 +1,17 @@ +#include "katmai.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KATMAIP SoC"; + compatible = "qcom,yupikp-iot"; + qcom,msm-id = <575 0x10000>; +}; + +&soc { + qcom,rmnet-ipa { + status = "disabled"; + }; +}; + +&ipa_hw { + status = "disabled"; +}; diff --git a/qcom/yupik-iot-hsp-overlay.dts b/qcom/yupik-iot-hsp-overlay.dts index ff3f722b20fc..305a1283c29e 100644 --- a/qcom/yupik-iot-hsp-overlay.dts +++ b/qcom/yupik-iot-hsp-overlay.dts @@ -7,6 +7,6 @@ / { model = "Qualcomm Technologies, Inc. Yupik IoT HSP"; compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; - qcom,msm-id = <497 0x10000>; + qcom,msm-id = <497 0x10000>, <575 0x10000>, <576 0x10000>; qcom,board-id = <34 1>; }; diff --git a/qcom/yupik-iot-hsp-pm7250b-overlay.dts b/qcom/yupik-iot-hsp-pm7250b-overlay.dts index 13601736b210..ae0e75afd39e 100644 --- a/qcom/yupik-iot-hsp-pm7250b-overlay.dts +++ b/qcom/yupik-iot-hsp-pm7250b-overlay.dts @@ -6,6 +6,6 @@ / { model = "Qualcomm Technologies, Inc. Yupik IOT HSP + PM7250B"; compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; - qcom,msm-id = <497 0x10000>; + qcom,msm-id = <497 0x10000>, <575 0x10000>, <576 0x10000>; qcom,board-id = <34 1>; }; diff --git a/qcom/yupik-iot-idp-overlay.dts b/qcom/yupik-iot-idp-overlay.dts index fcf60a41d2d6..6cfb766ca72f 100644 --- a/qcom/yupik-iot-idp-overlay.dts +++ b/qcom/yupik-iot-idp-overlay.dts @@ -7,6 +7,6 @@ / { model = "Qualcomm Technologies, Inc. YUPIK-IOT IDP"; compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; - qcom,msm-id = <497 0x10000>; + qcom,msm-id = <497 0x10000>, <575 0x10000>, <576 0x10000>; qcom,board-id = <34 0>; }; diff --git a/qcom/yupik-iot-idp-pm7250b-overlay.dts b/qcom/yupik-iot-idp-pm7250b-overlay.dts index 30427232e379..82336601fcdd 100644 --- a/qcom/yupik-iot-idp-pm7250b-overlay.dts +++ b/qcom/yupik-iot-idp-pm7250b-overlay.dts @@ -6,6 +6,6 @@ / { model = "Qualcomm Technologies, Inc. Yupik IOT IDP + PM7250B"; compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; - qcom,msm-id = <497 0x10000>; + qcom,msm-id = <497 0x10000>, <575 0x10000>, <576 0x10000>; qcom,board-id = <34 0>; }; diff --git a/qcom/yupik-iot-idps-amoled-overlay.dts b/qcom/yupik-iot-idps-amoled-overlay.dts index 0f64f04e5599..19d275473291 100644 --- a/qcom/yupik-iot-idps-amoled-overlay.dts +++ b/qcom/yupik-iot-idps-amoled-overlay.dts @@ -6,6 +6,6 @@ / { model = "Qualcomm Technologies, Inc. YUPIK-IOT IDPS + AMOLED"; compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; - qcom,msm-id = <497 0x10000>; + qcom,msm-id = <497 0x10000>, <575 0x10000>, <576 0x10000>; qcom,board-id = <34 2>; }; diff --git a/qcom/yupik-iot-qrd-overlay.dts b/qcom/yupik-iot-qrd-overlay.dts index 640be53957ac..84ef097bd8ff 100644 --- a/qcom/yupik-iot-qrd-overlay.dts +++ b/qcom/yupik-iot-qrd-overlay.dts @@ -6,6 +6,6 @@ / { model = "Qualcomm Technologies, Inc. YUPIK-IOT QRD"; compatible = "qcom,yupik-iot-qrd", "qcom,yupik-iot", "qcom,qrd"; - qcom,msm-id = <497 0x10000>; + qcom,msm-id = <497 0x10000>, <575 0x10000>, <576 0x10000>; qcom,board-id = <0x1000B 0>; }; diff --git a/qcom/yupikp-iot-hsp-overlay.dts b/qcom/yupikp-iot-hsp-overlay.dts index 5bce4a9f4d0f..a5ead642363b 100644 --- a/qcom/yupikp-iot-hsp-overlay.dts +++ b/qcom/yupikp-iot-hsp-overlay.dts @@ -7,6 +7,6 @@ / { model = "Qualcomm Technologies, Inc. YupikP IoT HSP"; compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; - qcom,msm-id = <498 0x10000>; + qcom,msm-id = <498 0x10000>, <575 0x10000>, <576 0x10000>; qcom,board-id = <34 1>; }; diff --git a/qcom/yupikp-iot-hsp-pm7250b-overlay.dts b/qcom/yupikp-iot-hsp-pm7250b-overlay.dts index 657d8bcd6537..93d88a639d8c 100644 --- a/qcom/yupikp-iot-hsp-pm7250b-overlay.dts +++ b/qcom/yupikp-iot-hsp-pm7250b-overlay.dts @@ -6,6 +6,6 @@ / { model = "Qualcomm Technologies, Inc. YupikP IOT HSP + PM7250B"; compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; - qcom,msm-id = <498 0x10000>; + qcom,msm-id = <498 0x10000>, <575 0x10000>, <576 0x10000>; qcom,board-id = <34 1>; }; diff --git a/qcom/yupikp-iot-idp-overlay.dts b/qcom/yupikp-iot-idp-overlay.dts index b90731fe0dfb..2afdd382b929 100644 --- a/qcom/yupikp-iot-idp-overlay.dts +++ b/qcom/yupikp-iot-idp-overlay.dts @@ -7,6 +7,6 @@ / { model = "Qualcomm Technologies, Inc. YUPIKP-IOT IDP"; compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; - qcom,msm-id = <498 0x10000>; + qcom,msm-id = <498 0x10000>, <575 0x10000>, <576 0x10000>; qcom,board-id = <34 0>; }; diff --git a/qcom/yupikp-iot-idp-pm7250b-overlay.dts b/qcom/yupikp-iot-idp-pm7250b-overlay.dts index 9b6f4f250fef..1f8aaad1ccbc 100644 --- a/qcom/yupikp-iot-idp-pm7250b-overlay.dts +++ b/qcom/yupikp-iot-idp-pm7250b-overlay.dts @@ -6,6 +6,6 @@ / { model = "Qualcomm Technologies, Inc. YupikP IOT IDP + PM7250B"; compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; - qcom,msm-id = <498 0x10000>; + qcom,msm-id = <498 0x10000>, <575 0x10000>,<576 0x10000>; qcom,board-id = <34 0>; }; diff --git a/qcom/yupikp-iot-idps-amoled-overlay.dts b/qcom/yupikp-iot-idps-amoled-overlay.dts index dfe1eae9874b..e4c15845a32a 100644 --- a/qcom/yupikp-iot-idps-amoled-overlay.dts +++ b/qcom/yupikp-iot-idps-amoled-overlay.dts @@ -6,6 +6,6 @@ / { model = "Qualcomm Technologies, Inc. YUPIKP-IOT IDPS + AMOLED"; compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; - qcom,msm-id = <498 0x10000>; + qcom,msm-id = <498 0x10000>, <575 0x10000>, <576 0x10000>; qcom,board-id = <34 2>; }; diff --git a/qcom/yupikp-iot-qrd-overlay.dts b/qcom/yupikp-iot-qrd-overlay.dts index 1df03e9216a3..06bf8795d084 100644 --- a/qcom/yupikp-iot-qrd-overlay.dts +++ b/qcom/yupikp-iot-qrd-overlay.dts @@ -6,6 +6,6 @@ / { model = "Qualcomm Technologies, Inc. YUPIKP-IOT QRD"; compatible = "qcom,yupikp-iot-qrd", "qcom,yupikp-iot", "qcom,qrd"; - qcom,msm-id = <498 0x10000>; + qcom,msm-id = <498 0x10000>, <575 0x10000>, <576 0x10000>; qcom,board-id = <0x1000B 0>; }; From 5a18eaad5867c935d3724eb74d4e84aa4d781a6f Mon Sep 17 00:00:00 2001 From: Dishendra Deshmukh Date: Thu, 28 Apr 2022 16:48:18 +0530 Subject: [PATCH 092/122] ARM: dts: msm: Add cpu related changes for Katmai targets Added DT changes for for Katmai targets 2xgold A78 (2.1GHz) +4x Silver A55 (1.8GHz). Change-Id: I133d7cf095132fd0ad6e831bb063a483fe33ef6d --- qcom/katmai-cpu.dtsi | 335 +++++++++++++++++++++++++++++++++++++++++++ qcom/katmai.dtsi | 1 + 2 files changed, 336 insertions(+) create mode 100644 qcom/katmai-cpu.dtsi diff --git a/qcom/katmai-cpu.dtsi b/qcom/katmai-cpu.dtsi new file mode 100644 index 000000000000..32e9e8289b22 --- /dev/null +++ b/qcom/katmai-cpu.dtsi @@ -0,0 +1,335 @@ +/ { + /delete-node/ cpus; +// /delete-node/ energy-costs; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + qcom,freq-domain = <&cpufreq_hw 0 4>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-level = <3>; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + qcom,freq-domain = <&cpufreq_hw 0 4>; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + qcom,freq-domain = <&cpufreq_hw 0 4>; + next-level-cache = <&L2_2>; + L2_2: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + qcom,freq-domain = <&cpufreq_hw 0 4>; + next-level-cache = <&L2_3>; + L2_3: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x400>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <520>; + qcom,freq-domain = <&cpufreq_hw 1 4>; + next-level-cache = <&L2_4>; + #cooling-cells = <2>; + L2_4: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x500>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <520>; + qcom,freq-domain = <&cpufreq_hw 1 4>; + next-level-cache = <&L2_5>; + L2_5: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + }; + }; + }; +}; + +&soc { + /delete-node/ jtagmm@7640000; + /delete-node/ jtagmm@7740000; + qcom,cpu0-cpugrp { + /delete-property/ qcom,cpulist; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,cpu4-cpu-llcc-latmon { + /delete-property/ qcom,cpulist; + qcom,cpulist = <&CPU4 &CPU5>; + qcom,core-dev-table = + < 691200 MHZ_TO_MBPS( 300, 16) >, + < 940800 MHZ_TO_MBPS( 466, 16) >, + < 1228800 MHZ_TO_MBPS( 600, 16) >, + < 1651200 MHZ_TO_MBPS( 806, 16) >; + }; + + qcom,cpu4-llcc-ddr-latmon { + /delete-property/ qcom,cpulist; + qcom,cpulist = <&CPU4 &CPU5>; + ddr4-map { + qcom,core-dev-table = + < 691200 MHZ_TO_MBPS( 451, 4) >, + < 940800 MHZ_TO_MBPS( 547, 4) >, + < 1228800 MHZ_TO_MBPS(1017, 4) >, + < 1651200 MHZ_TO_MBPS(1555, 4) >; + }; + + ddr5-map { + qcom,core-dev-table = + < 691200 MHZ_TO_MBPS( 451, 4) >, + < 940800 MHZ_TO_MBPS( 547, 4) >, + < 1228800 MHZ_TO_MBPS( 768, 4) >, + < 1651200 MHZ_TO_MBPS(1555, 4) >, + < 1900800 MHZ_TO_MBPS(1708, 4) >; + }; + }; + + qcom,cpu4-computemon { + /delete-property/ qcom,cpulist; + qcom,cpulist = <&CPU4 &CPU5>; + ddr4-map { + qcom,core-dev-table = + < 691200 MHZ_TO_MBPS( 451, 4) >, + < 1228800 MHZ_TO_MBPS( 547, 4) >, + < 1516800 MHZ_TO_MBPS( 768, 4) >, + < 1651200 MHZ_TO_MBPS(1017, 4) >, + < 1900800 MHZ_TO_MBPS(1555, 4) >; + }; + + ddr5-map { + qcom,core-dev-table = + < 691200 MHZ_TO_MBPS( 451, 4) >, + < 1228800 MHZ_TO_MBPS( 547, 4) >, + < 1516800 MHZ_TO_MBPS( 768, 4) >, + < 1651200 MHZ_TO_MBPS(1555, 4) >, + < 1900800 MHZ_TO_MBPS(1708, 4) >; + }; + }; + + qcom,cpu4-llcc-computemon { + /delete-property/ qcom,cpulist; + qcom,cpulist = <&CPU4 &CPU5>; + qcom,core-dev-table = + < 1900800 MHZ_TO_MBPS( 150, 16) >; + }; + + qcom,cpu4-qoslatmon { + /delete-property/ qcom,cpulist; + qcom,cpulist = <&CPU4 &CPU5>; + }; + + + /delete-node/ qcom,cpu7-qoslatmon; + /delete-node/ qcom,cpu7-l3-computemon; + /delete-node/ qcom,cpu7-computemon; + }; + + qcom,cpu4_grp { + /delete-property/ qcom,cpulist; + qcom,cpulist = <&CPU4 &CPU5>; + + qcom,cpu4-rimps-l3-latmon { + /delete-property/ qcom,cpulist; + qcom,cpulist = <&CPU4 &CPU5>; + qcom,core-dev-table = + < 940800 556800000 >, + < 1228800 768000000 >, + < 1651200 1190400000 >, + < 1900800 1401600000 >; + }; + }; + + /delete-node/ qcom,cpu7-cpu-ddr-latfloor; + /delete-node/ qcom,cpu7-cpu-l3-latfloor; + /delete-node/ qcom,cpu7-cpu-ddr-qoslatfloor; + /delete-node/ qcom,cpu7_grp; + /delete-node/ etm@7640000; + /delete-node/ etm@7740000; + /delete-node/ cti@7620000; + /delete-node/ cti@7720000; + + qcom,lpm-levels { + qcom,pm-cluster@0 { + qcom,pm-cpu@1 { + /delete-property/ qcom,cpu; + qcom,cpu = <&CPU4 &CPU5>; + }; + }; + }; +}; + +&cpufreq_hw { + qcom,cpu-isolation { + cpu6_isolate: cpu6-isolate { + /delete-property/ qcom,cpu; + }; + + + cpu7_isolate: cpu7-isolate { + /delete-property/ qcom,cpu; + }; + }; + + qcom,cpu-hotplug { + cpu6_hotplug: cpu6-hotplug { + /delete-property/ qcom,cpu; + }; + + + cpu7_hotplug: cpu7-hotplug { + /delete-property/ qcom,cpu; + }; + }; + + + qcom,cpu-voltage-cdev { + apc1_cluster: qcom,apc1-cluster { + /delete-property/ qcom,cpus; + qcom,cpus = <&CPU4>; + }; + }; +}; + +&funnel_apss { + in-ports { + /delete-node/ port@6; + /delete-node/ port@7; + }; +}; + +&thermal_zones { + cpu-1-4-step { + cooling-maps { + /delete-node/ cpu14_cdev; + /delete-node/ cpu14_cdev2; + }; + }; + + cpu-1-5-step { + cooling-maps { + /delete-node/ cpu15_cdev; + /delete-node/ cpu15_cdev2; + }; + }; + + cpu-1-6-step { + cooling-maps { + /delete-node/ cpu16_cdev; + /delete-node/ cpu16_cdev2; + }; + }; + + cpu-1-7-step { + cooling-maps { + /delete-node/ cpu17_cdev; + /delete-node/ cpu17_cdev2; + }; + }; + + mx-pe-step { + cooling-maps { + /delete-node/ mx_pe_cdev_cpu6; + /delete-node/ mx_pe_cdev_cpu7; + }; + }; +}; diff --git a/qcom/katmai.dtsi b/qcom/katmai.dtsi index 4b1667a64079..c96f538be9ff 100644 --- a/qcom/katmai.dtsi +++ b/qcom/katmai.dtsi @@ -1,4 +1,5 @@ #include "yupik-iot.dtsi" +#include "katmai-cpu.dtsi" / { model = "Qualcomm Technologies, Inc. KATMAI SoC"; From bb1ddaba680b17533e801c2df9e17d16f22295a5 Mon Sep 17 00:00:00 2001 From: Amit Kushwaha Date: Tue, 24 May 2022 10:40:58 +0530 Subject: [PATCH 093/122] ARM: dts: msm: Add GPU pwrlevels for Katmai target Add GPU power level support for Katmai platform. Change-Id: I3a98336a7c7492ea61b37b0bfd348eeb4f45a361 --- qcom/katmai.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/qcom/katmai.dtsi b/qcom/katmai.dtsi index 4b1667a64079..0bd04864b9fd 100644 --- a/qcom/katmai.dtsi +++ b/qcom/katmai.dtsi @@ -5,3 +5,35 @@ compatible = "qcom,yupik-iot"; qcom,msm-id = <576 0x10000>; }; + +&msm_gpu { + /delete-property/qcom,gpu-speed-bin; + /delete-property/qcom,initial-pwrlevel; + /delete-node/qcom,gpu-pwrlevels; + /delete-node/qcom,gpu-pwrlevel-bins; + + /* GPU power levels */ + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + qcom,initial-pwrlevel = <0>; + compatible = "qcom,gpu-pwrlevels"; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <315000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <3>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <3>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882F5FFD>; + }; + }; +}; From 9ef2d90ebf389b10276fc384b2e85d30d0161961 Mon Sep 17 00:00:00 2001 From: Hariharan Ramanathan Date: Mon, 20 Jun 2022 12:25:18 +0530 Subject: [PATCH 094/122] ARM: dts: qcom: Add changes for 2x pine with 5G and 6G radio Add changes for 2x pine with 5G and 6G radios to pick correct bdf files. Change-Id: I0c74186ab50e9570163319ebb6d88b6f4795a654 --- qcom/sdxlemur-v2-mtp-cpe-pine2x-5+6.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qcom/sdxlemur-v2-mtp-cpe-pine2x-5+6.dts b/qcom/sdxlemur-v2-mtp-cpe-pine2x-5+6.dts index 8a1cfd0d5b0c..6e942c0d1337 100644 --- a/qcom/sdxlemur-v2-mtp-cpe-pine2x-5+6.dts +++ b/qcom/sdxlemur-v2-mtp-cpe-pine2x-5+6.dts @@ -11,3 +11,15 @@ "qcom,sdxlemur", "qcom,mtp"; qcom,board-id = <0x12010008 0x312>; }; + +&wifi0 { + /* QCN9000 6G with SBS filter */ + status = "ok"; + board_id = <0xa4>; +}; + +&wifi1 { + /* QCN9000 5G */ + status = "ok"; + board_id = <0xa3>; +}; From f0aaeb702c81b230166bbba7663164f065428912 Mon Sep 17 00:00:00 2001 From: Dishednra Deshmukh Date: Wed, 15 Jun 2022 15:51:11 +0530 Subject: [PATCH 095/122] ARM: dts: msm: Disable PCIe1 nodes for katmai fp1 variant Disable PCIe1 nodes from dtsi file for katmai fp1 variant. Change-Id: Idb75c9af16d5bc3f59ddcde7dd2e2a7ee2fddaf7 --- qcom/Makefile | 18 +++++++++++++----- qcom/katmai-hsp-overlay.dts | 12 ++++++++++++ qcom/katmai-hsp-pm7250b-overlay.dts | 11 +++++++++++ qcom/katmai-hsp-pm7250b.dtsi | 10 ++++++++++ qcom/katmai-hsp.dtsi | 9 +++++++++ qcom/katmaip-hsp-overlay.dts | 12 ++++++++++++ qcom/katmaip-hsp-pm7250b-overlay.dts | 11 +++++++++++ qcom/katmaip-hsp-pm7250b.dtsi | 9 +++++++++ qcom/katmaip-hsp.dtsi | 9 +++++++++ 9 files changed, 96 insertions(+), 5 deletions(-) create mode 100644 qcom/katmai-hsp-overlay.dts create mode 100644 qcom/katmai-hsp-pm7250b-overlay.dts create mode 100644 qcom/katmai-hsp-pm7250b.dtsi create mode 100644 qcom/katmai-hsp.dtsi create mode 100644 qcom/katmaip-hsp-overlay.dts create mode 100644 qcom/katmaip-hsp-pm7250b-overlay.dts create mode 100644 qcom/katmaip-hsp-pm7250b.dtsi create mode 100644 qcom/katmaip-hsp.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 873f8c29cdb9..ed4144c17d14 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -237,13 +237,17 @@ dtbo-$(CONFIG_ARCH_YUPIK) += \ yupik-iot-idp-pm7250b-overlay.dtbo \ yupik-iot-qrd-overlay.dtbo \ yupik-iot-hsp-overlay.dtbo \ + katmai-hsp-overlay.dtbo \ yupik-iot-hsp-pm7250b-overlay.dtbo \ + katmai-hsp-pm7250b-overlay.dtbo \ yupik-iot-idps-amoled-overlay.dtbo \ yupikp-iot-idp-overlay.dtbo \ yupikp-iot-idp-pm7250b-overlay.dtbo \ yupikp-iot-qrd-overlay.dtbo \ yupikp-iot-hsp-overlay.dtbo \ + katmaip-hsp-overlay.dtbo \ yupikp-iot-hsp-pm7250b-overlay.dtbo \ + katmaip-hsp-pm7250b-overlay.dtbo \ yupikp-iot-idps-amoled-overlay.dtbo @@ -262,14 +266,18 @@ yupikp-idp-hsp-overlay.dtbo-base := yupikp-hsp.dtb yupik-iot-idp-overlay.dtbo-base := yupik-iot.dtb katmai.dtb yupik-iot-idp-pm7250b-overlay.dtbo-base := yupik-iot.dtb katmai.dtb yupik-iot-qrd-overlay.dtbo-base := yupik-iot.dtb katmai.dtb -yupik-iot-hsp-overlay.dtbo-base := yupik-iot.dtb katmai.dtb -yupik-iot-hsp-pm7250b-overlay.dtbo-base := yupik-iot.dtb katmai.dtb -yupik-iot-idps-amoled-overlay.dtbo-base := yupik-iot.dtb katmai.dtb +yupik-iot-hsp-overlay.dtbo-base := yupik-iot.dtb +katmai-hsp-overlay.dtbo-base := katmai.dtb +yupik-iot-hsp-pm7250b-overlay.dtbo-base := yupik-iot.dtb +katmai-hsp-pm7250b-overlay.dtbo-base := katmai.dtb +yupik-iot-idps-amoled-overlay.dtbo-base := katmai.dtb yupikp-iot-idp-overlay.dtbo-base := yupikp-iot.dtb katmaip.dtb yupikp-iot-idp-pm7250b-overlay.dtbo-base := yupikp-iot.dtb katmaip.dtb yupikp-iot-qrd-overlay.dtbo-base := yupikp-iot.dtb katmaip.dtb -yupikp-iot-hsp-overlay.dtbo-base := yupikp-iot.dtb katmaip.dtb -yupikp-iot-hsp-pm7250b-overlay.dtbo-base := yupikp-iot.dtb katmaip.dtb +yupikp-iot-hsp-overlay.dtbo-base := yupikp-iot.dtb +katmaip-hsp-overlay.dtbo-base := katmaip.dtb +yupikp-iot-hsp-pm7250b-overlay.dtbo-base := yupikp-iot.dtb +katmaip-hsp-pm7250b-overlay.dtbo-base := katmaip.dtb yupikp-iot-idps-amoled-overlay.dtbo-base := yupikp-iot.dtb katmaip.dtb else dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb \ diff --git a/qcom/katmai-hsp-overlay.dts b/qcom/katmai-hsp-overlay.dts new file mode 100644 index 000000000000..806c0f45d4dd --- /dev/null +++ b/qcom/katmai-hsp-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include +#include "katmai-hsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik IoT HSP"; + compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; + qcom,msm-id = <497 0x10000>, <575 0x10000>, <576 0x10000>; + qcom,board-id = <34 1>; +}; diff --git a/qcom/katmai-hsp-pm7250b-overlay.dts b/qcom/katmai-hsp-pm7250b-overlay.dts new file mode 100644 index 000000000000..fa1178cf9bc2 --- /dev/null +++ b/qcom/katmai-hsp-pm7250b-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "katmai-hsp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik IOT HSP + PM7250B"; + compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; + qcom,msm-id = <497 0x10000>, <575 0x10000>, <576 0x10000>; + qcom,board-id = <34 1>; +}; diff --git a/qcom/katmai-hsp-pm7250b.dtsi b/qcom/katmai-hsp-pm7250b.dtsi new file mode 100644 index 000000000000..82aceb806a2c --- /dev/null +++ b/qcom/katmai-hsp-pm7250b.dtsi @@ -0,0 +1,10 @@ +#include "yupik-iot-hsp-pm7250b.dtsi" + +&pcie1 { + status = "disabled"; +}; + +&pcie1_msi { + status = "disabled"; +}; + diff --git a/qcom/katmai-hsp.dtsi b/qcom/katmai-hsp.dtsi new file mode 100644 index 000000000000..2ae682e6e881 --- /dev/null +++ b/qcom/katmai-hsp.dtsi @@ -0,0 +1,9 @@ +#include "yupik-iot-hsp.dtsi" + +&pcie1 { + status = "disabled"; +}; + +&pcie1_msi { + status = "disabled"; +}; diff --git a/qcom/katmaip-hsp-overlay.dts b/qcom/katmaip-hsp-overlay.dts new file mode 100644 index 000000000000..bb8b4be0978e --- /dev/null +++ b/qcom/katmaip-hsp-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include +#include "katmaip-hsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YupikP IoT HSP"; + compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; + qcom,msm-id = <498 0x10000>, <575 0x10000>, <576 0x10000>; + qcom,board-id = <34 1>; +}; diff --git a/qcom/katmaip-hsp-pm7250b-overlay.dts b/qcom/katmaip-hsp-pm7250b-overlay.dts new file mode 100644 index 000000000000..69f48f511d31 --- /dev/null +++ b/qcom/katmaip-hsp-pm7250b-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "katmaip-hsp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. YupikP IOT HSP + PM7250B"; + compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; + qcom,msm-id = <498 0x10000>, <575 0x10000>, <576 0x10000>; + qcom,board-id = <34 1>; +}; diff --git a/qcom/katmaip-hsp-pm7250b.dtsi b/qcom/katmaip-hsp-pm7250b.dtsi new file mode 100644 index 000000000000..789376a38c6b --- /dev/null +++ b/qcom/katmaip-hsp-pm7250b.dtsi @@ -0,0 +1,9 @@ +#include "yupikp-iot-hsp-pm7250b.dtsi" + +&pcie1 { + status = "disabled"; +}; + +&pcie1_msi { + status = "disabled"; +}; diff --git a/qcom/katmaip-hsp.dtsi b/qcom/katmaip-hsp.dtsi new file mode 100644 index 000000000000..77283c6341e6 --- /dev/null +++ b/qcom/katmaip-hsp.dtsi @@ -0,0 +1,9 @@ +#include "yupikp-iot-hsp.dtsi" + +&pcie1 { + status = "disabled"; +}; + +&pcie1_msi { + status = "disabled"; +}; From 09b505464c1e38f1eb572852182074e02b0a7293 Mon Sep 17 00:00:00 2001 From: Priyansh Jain Date: Tue, 7 Jun 2022 16:10:48 +0530 Subject: [PATCH 096/122] dt-bindings: thermal: Add support for new SDR pa thermistors Add support for the new RF related thermistor support. The support includes for the qmi sensors sdr0_pa, sdr1_pa. Change-Id: I711ceca8f10ed04c073d3adb04b1025879a189f1 --- bindings/thermal/qti-qmi-sensor.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/bindings/thermal/qti-qmi-sensor.txt b/bindings/thermal/qti-qmi-sensor.txt index 1c42a19e8cc7..b5bb09558bc7 100644 --- a/bindings/thermal/qti-qmi-sensor.txt +++ b/bindings/thermal/qti-qmi-sensor.txt @@ -92,6 +92,17 @@ Subsystem properties: 59. mmw2 60. mmw3 61. mmw_ific0 + 62. rf_cal + 63. qfe_wtr_pa4 + 64. qfe_wtr_pa5 + 65. qfe_wtr_pa6 + 66. qfe_wtr_pa4_fr1 + 67. qfe_wtr_pa5_fr1 + 68. qfe_wtr_pa6_fr1 + 69. qfe_ret_pa1 + 70. qfe_ret_pa1_fr1 + 71. sdr0_pa + 72. sdr1_pa Example: From 8af04253d08154fb4caf40dcf9073d77b5277c34 Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Tue, 21 Jun 2022 16:02:04 +0530 Subject: [PATCH 097/122] ARM: dts: msm: Add support of FMAX 700mhz for blair GPU Enable 700 Mhz FMAX for blair GPU as per speed bin requirement. Change-Id: I86e333d751e94976a166c47d5d4d2701b7a5366f --- qcom/blair.dtsi | 67 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index b16c64f920a6..b9ccd3baf56c 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -3684,6 +3684,73 @@ qcom,bus-max-ddr7 = <4>; }; }; + + qcom,gpu-pwrlevels-3 { + #address-cells = <1>; + #size-cells = <0>; + qcom,speed-bin = <148>; + qcom,ca-target-pwrlevel = <3>; + qcom,initial-pwrlevel = <4>; + + + /* NOM_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <700000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <9>; + qcom,bus-min-ddr7 = <5>; + qcom,bus-max-ddr7 = <9>; + + }; + + /* NOM */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <650000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <6>; + qcom,bus-min-ddr7 = <5>; + qcom,bus-max-ddr7 = <8>; + + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <490000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <5>; + qcom,bus-min-ddr7 = <4>; + qcom,bus-max-ddr7 = <7>; + + }; + + /* SVS */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <390000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <4>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7= <5>; + }; + + /* LOW SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <266000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <2>; + qcom,bus-min-ddr7 = <1>; + qcom,bus-max-ddr7 = <4>; + }; + }; }; }; From 6eca9a4e95696276e231efbf64a4738c217b14ab Mon Sep 17 00:00:00 2001 From: Priyansh Jain Date: Tue, 7 Jun 2022 16:21:25 +0530 Subject: [PATCH 098/122] ARM: dts: msm: Add additional thermal zones for sdr pa sensors Add addtional thermal zones for sdr pa sensor to make compatibility on both modem versions. Change-Id: Ieaf14620cfca9894e76c2c8a9c28749c97ef25db --- qcom/sdxlemur-thermal-modem.dtsi | 44 +++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/qcom/sdxlemur-thermal-modem.dtsi b/qcom/sdxlemur-thermal-modem.dtsi index e54074abffd8..e04948b34a69 100644 --- a/qcom/sdxlemur-thermal-modem.dtsi +++ b/qcom/sdxlemur-thermal-modem.dtsi @@ -140,7 +140,9 @@ "mmw1", "mmw2", "mmw3", - "mmw_ific0"; + "mmw_ific0", + "sdr0_pa", + "sdr1_pa"; }; }; }; @@ -619,4 +621,44 @@ }; }; }; + + modem-sdr0-pa { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR0_PA)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-sdr1-pa { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR1_PA)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; }; From 71079c97b59c6c04b3d35843a0b2c392365722fb Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Wed, 18 May 2022 11:00:51 +0530 Subject: [PATCH 099/122] ARM: dts: qcom: Add new soc-id for Blair Add new soc-id to support Blair variant. Change-Id: I015768e06598d8e78e4280c25acc2a01a78059cc --- qcom/blair-atp-overlay.dts | 2 +- qcom/blair-cdp-overlay.dts | 2 +- qcom/blair-mtp-nopmi-overlay.dts | 2 +- qcom/blair-mtp-overlay.dts | 2 +- qcom/blair-mtp-usbc-overlay.dts | 2 +- qcom/blair-qrd-nopmi-overlay.dts | 2 +- qcom/blair-qrd-overlay.dts | 2 +- qcom/blair-rumi-overlay.dts | 2 +- qcom/blair.dtsi | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/qcom/blair-atp-overlay.dts b/qcom/blair-atp-overlay.dts index c002a611a76b..7ea8dfd91329 100644 --- a/qcom/blair-atp-overlay.dts +++ b/qcom/blair-atp-overlay.dts @@ -6,7 +6,7 @@ / { model = "Qualcomm Technologies, Inc. Blair ATP"; compatible = "qcom,blair-atp", "qcom,blair", "qcom,atp"; - qcom,msm-id = <507 0x10000>; + qcom,msm-id = <507 0x10000>, <578 0x10000>; qcom,board-id = <33 0>; }; diff --git a/qcom/blair-cdp-overlay.dts b/qcom/blair-cdp-overlay.dts index c46e6e97fc86..1961fb0914d0 100644 --- a/qcom/blair-cdp-overlay.dts +++ b/qcom/blair-cdp-overlay.dts @@ -6,7 +6,7 @@ / { model = "Qualcomm Technologies, Inc. Blair CDP"; compatible = "qcom,blair-cdp", "qcom,blair", "qcom,cdp"; - qcom,msm-id = <507 0x10000>; + qcom,msm-id = <507 0x10000>, <578 0x10000>; qcom,board-id = <1 0>; }; diff --git a/qcom/blair-mtp-nopmi-overlay.dts b/qcom/blair-mtp-nopmi-overlay.dts index a879373f8d08..a132050d0e25 100644 --- a/qcom/blair-mtp-nopmi-overlay.dts +++ b/qcom/blair-mtp-nopmi-overlay.dts @@ -6,7 +6,7 @@ / { model = "Qualcomm Technologies, Inc. Blair MTP NOPMI"; compatible = "qcom,blair-mtp", "qcom,blair", "qcom,mtp"; - qcom,msm-id = <507 0x10000>; + qcom,msm-id = <507 0x10000>, <578 0x10000>; qcom,board-id = <8 0>; qcom,pmic-id-size = <4>; qcom,pmic-id = <0x2D 0x0 0x0 0x0>; diff --git a/qcom/blair-mtp-overlay.dts b/qcom/blair-mtp-overlay.dts index 624cb3f025ec..4dbe0d8a6869 100644 --- a/qcom/blair-mtp-overlay.dts +++ b/qcom/blair-mtp-overlay.dts @@ -7,7 +7,7 @@ / { model = "Qualcomm Technologies, Inc. Blair MTP"; compatible = "qcom,blair-mtp", "qcom,blair", "qcom,mtp"; - qcom,msm-id = <507 0x10000>; + qcom,msm-id = <507 0x10000>, <578 0x10000>; qcom,board-id = <8 0>; qcom,pmic-id-size = <4>; qcom,pmic-id = <0x2D 0x0 0x2E 0x0>; diff --git a/qcom/blair-mtp-usbc-overlay.dts b/qcom/blair-mtp-usbc-overlay.dts index d6477987dbeb..69e6b42dad93 100644 --- a/qcom/blair-mtp-usbc-overlay.dts +++ b/qcom/blair-mtp-usbc-overlay.dts @@ -7,7 +7,7 @@ / { model = "Qualcomm Technologies, Inc. Blair MTP USBC audio"; compatible = "qcom,blair-mtp", "qcom,blair", "qcom,mtp"; - qcom,msm-id = <507 0x10000>; + qcom,msm-id = <507 0x10000>, <578 0x10000>; qcom,board-id = <8 1>; }; diff --git a/qcom/blair-qrd-nopmi-overlay.dts b/qcom/blair-qrd-nopmi-overlay.dts index 242b301e2408..3b837e5a2916 100644 --- a/qcom/blair-qrd-nopmi-overlay.dts +++ b/qcom/blair-qrd-nopmi-overlay.dts @@ -6,7 +6,7 @@ / { model = "Qualcomm Technologies, Inc. Blair QRD NOPMI"; compatible = "qcom,blair-qrd", "qcom,blair", "qcom,qrd"; - qcom,msm-id = <507 0x10000>; + qcom,msm-id = <507 0x10000>, <578 0x10000>; qcom,board-id = <0x1000B 0>; qcom,pmic-id-size = <4>; qcom,pmic-id = <0x2D 0x0 0x0 0x0>; diff --git a/qcom/blair-qrd-overlay.dts b/qcom/blair-qrd-overlay.dts index 57c75c1c53cd..f8a57fbf3309 100644 --- a/qcom/blair-qrd-overlay.dts +++ b/qcom/blair-qrd-overlay.dts @@ -7,7 +7,7 @@ / { model = "Qualcomm Technologies, Inc. Blair QRD"; compatible = "qcom,blair-qrd", "qcom,blair", "qcom,qrd"; - qcom,msm-id = <507 0x10000>; + qcom,msm-id = <507 0x10000>, <578 0x10000>; qcom,board-id = <0x1000B 0>; qcom,pmic-id-size = <4>; qcom,pmic-id = <0x2D 0x0 0x2E 0x0>; diff --git a/qcom/blair-rumi-overlay.dts b/qcom/blair-rumi-overlay.dts index 36113587bdfb..b1720bf4a833 100644 --- a/qcom/blair-rumi-overlay.dts +++ b/qcom/blair-rumi-overlay.dts @@ -6,6 +6,6 @@ / { model = "Qualcomm Technologies, Inc. Blair RUMI"; compatible = "qcom,blair-rumi", "qcom,blair", "qcom,rumi"; - qcom,msm-id = <507 0x10000>; + qcom,msm-id = <507 0x10000>, <578 0x10000>; qcom,board-id = <15 0>; }; diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index b9ccd3baf56c..8956d7e3b0b6 100644 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -17,7 +17,7 @@ / { model = "Qualcomm Technologies, Inc. Blair "; compatible = "qcom,blair"; - qcom,msm-id = <507 0x10000>; + qcom,msm-id = <507 0x10000>, <578 0x10000>; interrupt-parent = <&intc>; #address-cells = <2>; From af1e4757a113cf5a3d04c0733ce6c29cdf998931 Mon Sep 17 00:00:00 2001 From: Om Parkash Date: Fri, 6 May 2022 18:18:10 +0530 Subject: [PATCH 100/122] ARM: dts: msm: Disable csid2 & vfe2 nodes Disable csid2 & vfe2 nodes. Change-Id: Ibd39ab2ced0e4f62a24ac8c154ab213d90185d80 --- qcom/katmai.dtsi | 8 ++++++++ qcom/katmaip.dtsi | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/qcom/katmai.dtsi b/qcom/katmai.dtsi index 55d4bad04ee7..4c20a8c70358 100644 --- a/qcom/katmai.dtsi +++ b/qcom/katmai.dtsi @@ -38,3 +38,11 @@ }; }; }; + +&cam_csid2 { + status = "disabled"; +}; + +&cam_vfe2 { + status = "disabled"; +}; diff --git a/qcom/katmaip.dtsi b/qcom/katmaip.dtsi index bcc2e8e9af54..ebc82acfc62e 100644 --- a/qcom/katmaip.dtsi +++ b/qcom/katmaip.dtsi @@ -6,6 +6,14 @@ qcom,msm-id = <575 0x10000>; }; +&cam_csid2 { + status = "disabled"; +}; + +&cam_vfe2 { + status = "disabled"; +}; + &soc { qcom,rmnet-ipa { status = "disabled"; From c3aeb936a3af0611571622063de4e6dab167fb04 Mon Sep 17 00:00:00 2001 From: Sai Srujana Oruganti Date: Thu, 14 Jul 2022 11:46:33 +0530 Subject: [PATCH 101/122] ARM: dts: msm: set default panel for yupik iot qrd Set r66451_amoled_120Hz cmd cphy panel as default panel for yupik iot qrd platform. Change-Id: I5053f89b8fe4ef6e06b4d164c3a152914b68d3da --- qcom/yupik-iot-qrd.dtsi | 4 ++++ qcom/yupikp-iot-qrd.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/qcom/yupik-iot-qrd.dtsi b/qcom/yupik-iot-qrd.dtsi index 3eaf08aed50a..07e07fa9fa42 100644 --- a/qcom/yupik-iot-qrd.dtsi +++ b/qcom/yupik-iot-qrd.dtsi @@ -36,3 +36,7 @@ &gcc_usb30_sec_gdsc { status = "ok"; }; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_r66451_amoled_120hz_cmd_cphy>; +}; diff --git a/qcom/yupikp-iot-qrd.dtsi b/qcom/yupikp-iot-qrd.dtsi index 9119462f89dc..75aeb4ca4aab 100644 --- a/qcom/yupikp-iot-qrd.dtsi +++ b/qcom/yupikp-iot-qrd.dtsi @@ -1 +1,5 @@ #include "yupikp-qrd.dtsi" + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_r66451_amoled_120hz_cmd_cphy>; +}; From 1d7ad7c2fc95b4dc405b64b8fb066294254cfffd Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Wed, 20 Jul 2022 14:19:13 +0530 Subject: [PATCH 102/122] ARM: dts: msm: Add support for 700Mhz GPU FMAX for yupik Enable 700Mhz FMAX for yupik GPU as per speed bin requirement. Change-Id: I671c7498b7a39e4b3def68ff5c9b5f01e45964f8 --- qcom/yupik-gpu.dtsi | 88 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/qcom/yupik-gpu.dtsi b/qcom/yupik-gpu.dtsi index c8a93bd66ed6..da9b0fdd4f37 100644 --- a/qcom/yupik-gpu.dtsi +++ b/qcom/yupik-gpu.dtsi @@ -559,6 +559,94 @@ qcom,acd-level = <0x882F5FFD>; }; }; + + qcom,gpu-pwrlevels-5 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <148>; + qcom,initial-pwrlevel = <4>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <700000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <10>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <9>; + qcom,bus-min-ddr8 = <8>; + qcom,bus-max-ddr8 = <10>; + + qcom,acd-level = <0x802B5FFD>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <608000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <10>; + qcom,bus-min-ddr7 = <9>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <8>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <10>; + + qcom,acd-level = <0x802B5FFD>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <550000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <9>; + qcom,bus-min-ddr7 = <8>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <6>; + qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0x802B5FFD>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <450000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <6>; + qcom,bus-min-ddr7 = <5>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <6>; + qcom,bus-max-ddr8 = <8>; + + qcom,acd-level = <0x802B5FFD>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <315000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <3>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <3>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882F5FFD>; + }; + }; }; }; From 4a6ae6e0d86102a10ee2f10081e6fcbb05cd797a Mon Sep 17 00:00:00 2001 From: Jyothi Kumar Seerapu Date: Mon, 25 Jul 2022 16:03:51 +0530 Subject: [PATCH 103/122] ARM: dts: qcom: Add support to disable PCIe halt Wr and Rd This will add the provision to control the PCIe halt Wr and Rd. By setting this DT flag, PCIe halt Wr and Rd can be disabled. In Olympic CPE targets observed degradation in throughput due to PCIe latencies with PCIe halt write/read feature. Hence, disabling the PCIe halt feature in Olympic CPE targets. Change-Id: Iee945984e24f2a99d9e0b1e2a0323255decc28ef --- bindings/pci/pci-msm.txt | 6 ++++++ qcom/sdxlemur-pcie.dtsi | 1 + 2 files changed, 7 insertions(+) diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index fce9facfeada..30addf402558 100644 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -407,12 +407,18 @@ interconnects: Usage: optional Value type: Definition: Skip enumeration for the list of 32-bit BDFs. + - qcom,config-recovery: Usage: optional Value type : Definition: Enable to notify the client driver for recovery when config space is not accessible +- qcom, pcie-halt-feature-dis: + Usage: optional + Value type : + Definition: Disable PCIe Write and Read halt feature + ============== Root port node ============== diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index 05b1db8be5e1..437bac326385 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -115,6 +115,7 @@ qcom,slv-addr-space-size = <0x40000000>; qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; + qcom,pcie-halt-feature-dis; qcom,pcie-phy-ver = <1108>; qcom,phy-status-offset = <0x1214>; From ba95a9124d485b4838ed52cd294120c9ebb96445 Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Tue, 26 Jul 2022 19:24:14 +0530 Subject: [PATCH 104/122] ARM: dts: msm: Reduce IPA AB DDR vote value for LOW SVS corner In modem concurrency scenario when modem and apps voting for DDR aggregated AB vote was jumping to next corner. To avoid this issue reducing apps AB vote from apps side. Change-Id: I1317fb8e6f8802e08e44e868d6d6c9a7c6cac1d8 --- qcom/sdxlemur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 82def0a0d2e1..27cede7e5cc0 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1229,7 +1229,7 @@ /* SVS2 */ qcom,svs2 = - <780000 0 1300000 1800000 0 76800>; + <50000 0 600000 1900000 0 76800>; /* SVS */ qcom,svs = From 3b2b075db14c997b28db76c42cf6567da053c2ff Mon Sep 17 00:00:00 2001 From: Priyansh Jain Date: Tue, 26 Jul 2022 14:46:25 +0530 Subject: [PATCH 105/122] dt-bindings: thermal: Update CPU voltage cooling device bindings Update bindings for the updated properties of CPU voltage cooling device. Change-Id: I5af1f1c203a7374f493cc98409cb3ac48feb5d55 --- bindings/thermal/qti-voltage-cooling.txt | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/bindings/thermal/qti-voltage-cooling.txt b/bindings/thermal/qti-voltage-cooling.txt index ad5b3436aba0..84b62e0a484c 100644 --- a/bindings/thermal/qti-voltage-cooling.txt +++ b/bindings/thermal/qti-voltage-cooling.txt @@ -15,11 +15,24 @@ Required Parameters: driver. voltage cooling device node properties: - -qcom,cpus: + - apc1_cluster: thermal-cluster-a-b + Usage: required + Definition : CPU voltage cooling device node name. where 'a' is the + 1st core of 1st cluster and 'b' is 1st core of 2nd cluster. + + -qcom,cluster0: Usage: required Value type: An array of CPU phandle - Definition: Specify array of 2 CPU phandles, which needs to be - used for building a voltage based mitigation table. + Definition: Specify array of CPU phandles available in 1st cluster, + which needs to be used for building a voltage based mitigation + table. + + -qcom,cluster1: + Usage: required + Value type: An array of CPU phandle + Definition: Specify array of CPU phandles available in 2nd cluster, + which needs to be used for building a voltage based mitigation + table. -#cooling-cells: Usage: required @@ -35,8 +48,9 @@ Optional Parameters: Example: qcom,cpu-voltage-cdev { compatible = "qcom,cc-cooling-devices"; - apc1_cluster: qcom,apc1-cluster { - qcom,cpus = <&CPU4 &CPU7>; + apc1_cluster: thermal-cluster-4-7 { + qcom,cluster0 = <&CPU4 &CPU5 &CPU6>; + qcom,cluster1 = <&CPU7>; #cooling-cells = <2>; }; }; From e69f4f590fe59f2f8b5886b7cab3e507b9ed1fb4 Mon Sep 17 00:00:00 2001 From: Priyansh Jain Date: Tue, 26 Jul 2022 15:28:59 +0530 Subject: [PATCH 106/122] ARM: dts: qcom: Update cpu voltage cooling device node Add cpu voltage cooling device devicetree node. Change-Id: I7d83cd625f4b80136f2cec656e22188e6283f8fe --- qcom/katmai-cpu.dtsi | 34 ++++++++++++++++++++++++++++++---- qcom/lahaina-thermal.dtsi | 5 +++-- qcom/shima-thermal.dtsi | 5 +++-- qcom/yupik-thermal.dtsi | 5 +++-- 4 files changed, 39 insertions(+), 10 deletions(-) diff --git a/qcom/katmai-cpu.dtsi b/qcom/katmai-cpu.dtsi index 32e9e8289b22..86771b11ca9f 100644 --- a/qcom/katmai-cpu.dtsi +++ b/qcom/katmai-cpu.dtsi @@ -281,13 +281,13 @@ }; }; - qcom,cpu-voltage-cdev { - apc1_cluster: qcom,apc1-cluster { - /delete-property/ qcom,cpus; - qcom,cpus = <&CPU4>; + apc1_cluster: thermal-cluster-4-7 { + /delete-property/ qcom,cluster0; + /delete-property/ qcom,cluster1; }; }; + }; &funnel_apss { @@ -298,9 +298,34 @@ }; &thermal_zones { + cpu-1-0-step { + cooling-maps { + /delete-node/ cpu10_cdev1; + }; + }; + + cpu-1-1-step { + cooling-maps { + /delete-node/ cpu11_cdev1; + }; + }; + + cpu-1-2-step { + cooling-maps { + /delete-node/ cpu12_cdev1; + }; + }; + + cpu-1-3-step { + cooling-maps { + /delete-node/ cpu13_cdev1; + }; + }; + cpu-1-4-step { cooling-maps { /delete-node/ cpu14_cdev; + /delete-node/ cpu14_cdev1; /delete-node/ cpu14_cdev2; }; }; @@ -308,6 +333,7 @@ cpu-1-5-step { cooling-maps { /delete-node/ cpu15_cdev; + /delete-node/ cpu15_cdev1; /delete-node/ cpu15_cdev2; }; }; diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi index 4fadb7a87f45..62c72c32cfa0 100644 --- a/qcom/lahaina-thermal.dtsi +++ b/qcom/lahaina-thermal.dtsi @@ -171,8 +171,9 @@ qcom,cpu-voltage-cdev { compatible = "qcom,cc-cooling-devices"; - apc1_cluster: qcom,apc1-cluster { - qcom,cpus = <&CPU4 &CPU7>; + apc1_cluster: thermal-cluster-4-7 { + qcom,cluster0 = <&CPU4 &CPU5 &CPU6>; + qcom,cluster1 = <&CPU7>; #cooling-cells = <2>; }; }; diff --git a/qcom/shima-thermal.dtsi b/qcom/shima-thermal.dtsi index a5b819e44a9c..bf631203e352 100644 --- a/qcom/shima-thermal.dtsi +++ b/qcom/shima-thermal.dtsi @@ -199,8 +199,9 @@ qcom,cpu-voltage-cdev { compatible = "qcom,cc-cooling-devices"; - apc1_cluster: qcom,apc1-cluster { - qcom,cpus = <&CPU4 &CPU7>; + apc1_cluster: thermal-cluster-4-7 { + qcom,cluster0 = <&CPU4 &CPU5 &CPU6>; + qcom,cluster1 = <&CPU7>; #cooling-cells = <2>; }; }; diff --git a/qcom/yupik-thermal.dtsi b/qcom/yupik-thermal.dtsi index a9d549cfe7b1..db04e7b9de33 100644 --- a/qcom/yupik-thermal.dtsi +++ b/qcom/yupik-thermal.dtsi @@ -231,8 +231,9 @@ qcom,cpu-voltage-cdev { compatible = "qcom,cc-cooling-devices"; - apc1_cluster: qcom,apc1-cluster { - qcom,cpus = <&CPU4 &CPU7>; + apc1_cluster: thermal-cluster-4-7 { + qcom,cluster0 = <&CPU4 &CPU5 &CPU6>; + qcom,cluster1 = <&CPU7>; #cooling-cells = <2>; }; }; From 9aa1445b87cbe781165b3275b344bd95c8adea83 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Tue, 26 Jul 2022 19:09:17 +0530 Subject: [PATCH 107/122] ARM: dts: qcom: add calibrated batt_therm channel for yupik Add calibrated batt_therm channel for yupik to read battery temperature accurately. Change-Id: Ide4529ae1ee5cfaf922ca1e50127f6c0d67c95d2 --- qcom/yupik-idp.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/yupik-idp.dtsi b/qcom/yupik-idp.dtsi index 97bfc3cba1f2..ddc59eb8c3af 100644 --- a/qcom/yupik-idp.dtsi +++ b/qcom/yupik-idp.dtsi @@ -144,6 +144,14 @@ qcom,pre-scaling = <1 1>; }; + pm7325b_batt_therm { + reg = ; + label = "pm7325b_batt_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + pm7325b_chg_temp { reg = ; label = "pm7325b_chg_temp"; From 939c4b947458d80566547f861865dc8b76ad7b87 Mon Sep 17 00:00:00 2001 From: Dishendra Deshmukh Date: Thu, 28 Jul 2022 17:04:08 +0530 Subject: [PATCH 108/122] ARM: dts: msm: Add cpu related changes for Katmai FP2 targets Added DT changes for for Katmai targets 4xgold A78 (2.1GHz) +4x Silver A55 (1.8GHz). Change-Id: I47ec2d3fd2528d44998bb485ae4046de998acf6d --- qcom/Makefile | 32 +++++---- qcom/katmai-cpu-fp2.dtsi | 89 ++++++++++++++++++++++++ qcom/katmai-fp2-hsp-overlay.dts | 22 ++++++ qcom/katmai-fp2-hsp-pm7250b-overlay.dts | 21 ++++++ qcom/katmai-fp2.dts | 9 +++ qcom/katmai-fp2.dtsi | 41 +++++++++++ qcom/katmai-hsp-overlay.dts | 3 +- qcom/katmai-hsp-pm7250b-overlay.dts | 3 +- qcom/katmai.dtsi | 1 + qcom/katmaip-fp2-hsp-overlay.dts | 22 ++++++ qcom/katmaip-fp2-hsp-pm7250b-overlay.dts | 21 ++++++ qcom/katmaip-fp2.dts | 9 +++ qcom/katmaip-fp2.dtsi | 18 +++++ qcom/katmaip-hsp-overlay.dts | 3 +- qcom/katmaip-hsp-pm7250b-overlay.dts | 3 +- qcom/katmaip.dtsi | 1 + 16 files changed, 282 insertions(+), 16 deletions(-) create mode 100644 qcom/katmai-cpu-fp2.dtsi create mode 100644 qcom/katmai-fp2-hsp-overlay.dts create mode 100644 qcom/katmai-fp2-hsp-pm7250b-overlay.dts create mode 100644 qcom/katmai-fp2.dts create mode 100644 qcom/katmai-fp2.dtsi create mode 100644 qcom/katmaip-fp2-hsp-overlay.dts create mode 100644 qcom/katmaip-fp2-hsp-pm7250b-overlay.dts create mode 100644 qcom/katmaip-fp2.dts create mode 100644 qcom/katmaip-fp2.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index ed4144c17d14..972c845c97a4 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -237,17 +237,21 @@ dtbo-$(CONFIG_ARCH_YUPIK) += \ yupik-iot-idp-pm7250b-overlay.dtbo \ yupik-iot-qrd-overlay.dtbo \ yupik-iot-hsp-overlay.dtbo \ - katmai-hsp-overlay.dtbo \ yupik-iot-hsp-pm7250b-overlay.dtbo \ + katmai-hsp-overlay.dtbo \ katmai-hsp-pm7250b-overlay.dtbo \ + katmai-fp2-hsp-overlay.dtbo \ + katmai-fp2-hsp-pm7250b-overlay.dtbo \ yupik-iot-idps-amoled-overlay.dtbo \ yupikp-iot-idp-overlay.dtbo \ yupikp-iot-idp-pm7250b-overlay.dtbo \ yupikp-iot-qrd-overlay.dtbo \ yupikp-iot-hsp-overlay.dtbo \ - katmaip-hsp-overlay.dtbo \ yupikp-iot-hsp-pm7250b-overlay.dtbo \ + katmaip-hsp-overlay.dtbo \ katmaip-hsp-pm7250b-overlay.dtbo \ + katmaip-fp2-hsp-overlay.dtbo \ + katmaip-fp2-hsp-pm7250b-overlay.dtbo \ yupikp-iot-idps-amoled-overlay.dtbo @@ -263,22 +267,26 @@ yupikp-atp-overlay.dtbo-base := yupikp.dtb yupikp-qrd-overlay.dtbo-base := yupikp.dtb yupikp-idps-amoled-overlay.dtbo-base := yupikp.dtb yupikp-idp-hsp-overlay.dtbo-base := yupikp-hsp.dtb -yupik-iot-idp-overlay.dtbo-base := yupik-iot.dtb katmai.dtb -yupik-iot-idp-pm7250b-overlay.dtbo-base := yupik-iot.dtb katmai.dtb -yupik-iot-qrd-overlay.dtbo-base := yupik-iot.dtb katmai.dtb +yupik-iot-idp-overlay.dtbo-base := yupik-iot.dtb katmai.dtb katmai-fp2.dtb +yupik-iot-idp-pm7250b-overlay.dtbo-base := yupik-iot.dtb katmai.dtb katmai-fp2.dtb +yupik-iot-qrd-overlay.dtbo-base := yupik-iot.dtb katmai.dtb katmai-fp2.dtb yupik-iot-hsp-overlay.dtbo-base := yupik-iot.dtb -katmai-hsp-overlay.dtbo-base := katmai.dtb yupik-iot-hsp-pm7250b-overlay.dtbo-base := yupik-iot.dtb +katmai-hsp-overlay.dtbo-base := katmai.dtb katmai-hsp-pm7250b-overlay.dtbo-base := katmai.dtb -yupik-iot-idps-amoled-overlay.dtbo-base := katmai.dtb -yupikp-iot-idp-overlay.dtbo-base := yupikp-iot.dtb katmaip.dtb -yupikp-iot-idp-pm7250b-overlay.dtbo-base := yupikp-iot.dtb katmaip.dtb -yupikp-iot-qrd-overlay.dtbo-base := yupikp-iot.dtb katmaip.dtb +katmai-fp2-hsp-overlay.dtbo-base := katmai-fp2.dtb +katmai-fp2-hsp-pm7250b-overlay.dtbo-base := katmai-fp2.dtb +yupik-iot-idps-amoled-overlay.dtbo-base := yupik-iot.dtb katmai.dtb katmai-fp2.dtb +yupikp-iot-idp-overlay.dtbo-base := yupikp-iot.dtb katmaip.dtb katmaip-fp2.dtb +yupikp-iot-idp-pm7250b-overlay.dtbo-base := yupikp-iot.dtb katmaip.dtb katmaip-fp2.dtb +yupikp-iot-qrd-overlay.dtbo-base := yupikp-iot.dtb katmaip.dtb katmaip-fp2.dtb yupikp-iot-hsp-overlay.dtbo-base := yupikp-iot.dtb -katmaip-hsp-overlay.dtbo-base := katmaip.dtb yupikp-iot-hsp-pm7250b-overlay.dtbo-base := yupikp-iot.dtb +katmaip-hsp-overlay.dtbo-base := katmaip.dtb katmaip-hsp-pm7250b-overlay.dtbo-base := katmaip.dtb -yupikp-iot-idps-amoled-overlay.dtbo-base := yupikp-iot.dtb katmaip.dtb +katmaip-fp2-hsp-overlay.dtbo-base := katmaip-fp2.dtb +katmaip-fp2-hsp-pm7250b-overlay.dtbo-base := katmaip-fp2.dtb +yupikp-iot-idps-amoled-overlay.dtbo-base := yupikp-iot.dtb katmaip.dtb katmaip-fp2.dtb else dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb \ yupik-idp.dtb \ diff --git a/qcom/katmai-cpu-fp2.dtsi b/qcom/katmai-cpu-fp2.dtsi new file mode 100644 index 000000000000..f7af471759e9 --- /dev/null +++ b/qcom/katmai-cpu-fp2.dtsi @@ -0,0 +1,89 @@ +&cpu4_cpu_llcc_latmon { + qcom,core-dev-table = + < 691200 MHZ_TO_MBPS( 300, 16) >, + < 940800 MHZ_TO_MBPS( 466, 16) >, + < 1228800 MHZ_TO_MBPS( 600, 16) >, + < 1651200 MHZ_TO_MBPS( 806, 16) >; +}; + +&cpu4_llcc_ddr_latmon { + ddr4-map { + qcom,core-dev-table = + < 691200 MHZ_TO_MBPS( 451, 4) >, + < 940800 MHZ_TO_MBPS( 547, 4) >, + < 1228800 MHZ_TO_MBPS(1017, 4) >, + < 1651200 MHZ_TO_MBPS(1555, 4) >; + }; + + ddr5-map { + qcom,core-dev-table = + < 691200 MHZ_TO_MBPS( 451, 4) >, + < 940800 MHZ_TO_MBPS( 547, 4) >, + < 1228800 MHZ_TO_MBPS( 768, 4) >, + < 1651200 MHZ_TO_MBPS(1555, 4) >, + < 1900800 MHZ_TO_MBPS(1708, 4) >; + }; +}; + +&cpu4_computemon { + ddr4-map { + qcom,core-dev-table = + < 691200 MHZ_TO_MBPS( 451, 4) >, + < 1228800 MHZ_TO_MBPS( 547, 4) >, + < 1516800 MHZ_TO_MBPS( 768, 4) >, + < 1651200 MHZ_TO_MBPS(1017, 4) >, + < 1900800 MHZ_TO_MBPS(1555, 4) >; + }; + + ddr5-map { + qcom,core-dev-table = + < 691200 MHZ_TO_MBPS( 451, 4) >, + < 1228800 MHZ_TO_MBPS( 547, 4) >, + < 1516800 MHZ_TO_MBPS( 768, 4) >, + < 1651200 MHZ_TO_MBPS(1555, 4) >, + < 1900800 MHZ_TO_MBPS(1708, 4) >; + }; +}; + +&cpu4_llcc_computemon { + qcom,core-dev-table = + < 1900800 MHZ_TO_MBPS( 150, 16) >; +}; + +&cpu7_computemon { + ddr4-map { + qcom,core-dev-table = + < 2380800 MHZ_TO_MBPS( 451, 4) >; + }; + + ddr5-map { + qcom,core-dev-table = + < 2380800 MHZ_TO_MBPS( 451, 4) >; + }; +}; + +&cpu7_l3_computemon { + qcom,core-dev-table = + < 2035200 300000000 >; +}; + +&cpu7_qoslatmon { + qcom,core-dev-table = + < 2035200 1 >; + +}; + +&cpu4_rimps_l3_latmon { + qcom,core-dev-table = + < 940800 556800000 >, + < 1228800 768000000 >, + < 1651200 1190400000 >, + < 1900800 1401600000 >; +}; + +&cpu7_rimps_l3_latmon { + qcom,core-dev-table = + < 1056000 556800000 >, + < 1324800 768000000 >, + < 1766400 1190400000 >; +}; diff --git a/qcom/katmai-fp2-hsp-overlay.dts b/qcom/katmai-fp2-hsp-overlay.dts new file mode 100644 index 000000000000..23e5434a5674 --- /dev/null +++ b/qcom/katmai-fp2-hsp-overlay.dts @@ -0,0 +1,22 @@ +/dts-v1/; +/plugin/; + +#include +#include "katmai-hsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Katmai FP2 IoT HSP"; + compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; + qcom,msm-id = <497 0x10000>, <575 0x10000>, <576 0x10000>; + qcom,board-id = <34 1>; + qcom,softsku-id = <2>; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie1_msi { + status = "okay"; +}; + diff --git a/qcom/katmai-fp2-hsp-pm7250b-overlay.dts b/qcom/katmai-fp2-hsp-pm7250b-overlay.dts new file mode 100644 index 000000000000..3daf3088780a --- /dev/null +++ b/qcom/katmai-fp2-hsp-pm7250b-overlay.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +#include "katmai-hsp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Katmai FP2 IOT HSP + PM7250B"; + compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; + qcom,msm-id = <497 0x10000>, <575 0x10000>, <576 0x10000>; + qcom,board-id = <34 1>; + qcom,softsku-id = <2>; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie1_msi { + status = "okay"; +}; + diff --git a/qcom/katmai-fp2.dts b/qcom/katmai-fp2.dts new file mode 100644 index 000000000000..10a68aa48e59 --- /dev/null +++ b/qcom/katmai-fp2.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "katmai-fp2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KATMAI-FP2 SoC"; + compatible = "qcom,yupik-iot"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/katmai-fp2.dtsi b/qcom/katmai-fp2.dtsi new file mode 100644 index 000000000000..74ac5fcd2324 --- /dev/null +++ b/qcom/katmai-fp2.dtsi @@ -0,0 +1,41 @@ +#include "yupik-iot.dtsi" +#include "katmai-cpu-fp2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KATMAI-FP2 SoC"; + compatible = "qcom,yupik-iot"; + qcom,msm-id = <576 0x10000>; + qcom,softsku-id = <2>; +}; + +&msm_gpu { + /delete-property/qcom,gpu-speed-bin; + /delete-property/qcom,initial-pwrlevel; + /delete-node/qcom,gpu-pwrlevels; + /delete-node/qcom,gpu-pwrlevel-bins; + + /* GPU power levels */ + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + qcom,initial-pwrlevel = <0>; + compatible = "qcom,gpu-pwrlevels"; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <315000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <3>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <3>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882F5FFD>; + }; + }; +}; diff --git a/qcom/katmai-hsp-overlay.dts b/qcom/katmai-hsp-overlay.dts index 806c0f45d4dd..02720f56b1c6 100644 --- a/qcom/katmai-hsp-overlay.dts +++ b/qcom/katmai-hsp-overlay.dts @@ -5,8 +5,9 @@ #include "katmai-hsp.dtsi" / { - model = "Qualcomm Technologies, Inc. Yupik IoT HSP"; + model = "Qualcomm Technologies, Inc. Katmai IoT HSP"; compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; qcom,msm-id = <497 0x10000>, <575 0x10000>, <576 0x10000>; qcom,board-id = <34 1>; + qcom,softsku-id = <1>; }; diff --git a/qcom/katmai-hsp-pm7250b-overlay.dts b/qcom/katmai-hsp-pm7250b-overlay.dts index fa1178cf9bc2..67050db9a43d 100644 --- a/qcom/katmai-hsp-pm7250b-overlay.dts +++ b/qcom/katmai-hsp-pm7250b-overlay.dts @@ -4,8 +4,9 @@ #include "katmai-hsp-pm7250b.dtsi" / { - model = "Qualcomm Technologies, Inc. Yupik IOT HSP + PM7250B"; + model = "Qualcomm Technologies, Inc. Katmai IOT HSP + PM7250B"; compatible = "qcom,yupik-iot-idp", "qcom,yupik-iot", "qcom,idp"; qcom,msm-id = <497 0x10000>, <575 0x10000>, <576 0x10000>; qcom,board-id = <34 1>; + qcom,softsku-id = <1>; }; diff --git a/qcom/katmai.dtsi b/qcom/katmai.dtsi index 4c20a8c70358..ec23e8231b72 100644 --- a/qcom/katmai.dtsi +++ b/qcom/katmai.dtsi @@ -5,6 +5,7 @@ model = "Qualcomm Technologies, Inc. KATMAI SoC"; compatible = "qcom,yupik-iot"; qcom,msm-id = <576 0x10000>; + qcom,softsku-id = <1>; }; &msm_gpu { diff --git a/qcom/katmaip-fp2-hsp-overlay.dts b/qcom/katmaip-fp2-hsp-overlay.dts new file mode 100644 index 000000000000..f6c78069c114 --- /dev/null +++ b/qcom/katmaip-fp2-hsp-overlay.dts @@ -0,0 +1,22 @@ +/dts-v1/; +/plugin/; + +#include +#include "katmaip-hsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KatmaiP FP2 IoT HSP"; + compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; + qcom,msm-id = <498 0x10000>, <575 0x10000>, <576 0x10000>; + qcom,board-id = <34 1>; + qcom,softsku-id = <2>; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie1_msi { + status = "okay"; +}; + diff --git a/qcom/katmaip-fp2-hsp-pm7250b-overlay.dts b/qcom/katmaip-fp2-hsp-pm7250b-overlay.dts new file mode 100644 index 000000000000..e802e8da8e6e --- /dev/null +++ b/qcom/katmaip-fp2-hsp-pm7250b-overlay.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; + +#include "katmaip-hsp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KatmaiP FP2 IOT HSP + PM7250B"; + compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; + qcom,msm-id = <498 0x10000>, <575 0x10000>, <576 0x10000>; + qcom,board-id = <34 1>; + qcom,softsku-id = <2>; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie1_msi { + status = "okay"; +}; + diff --git a/qcom/katmaip-fp2.dts b/qcom/katmaip-fp2.dts new file mode 100644 index 000000000000..6fe9dd37f37c --- /dev/null +++ b/qcom/katmaip-fp2.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "katmaip-fp2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KATMAIP-FP2 SoC"; + compatible = "qcom,yupikp-iot"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/katmaip-fp2.dtsi b/qcom/katmaip-fp2.dtsi new file mode 100644 index 000000000000..9296d0e29903 --- /dev/null +++ b/qcom/katmaip-fp2.dtsi @@ -0,0 +1,18 @@ +#include "katmai-fp2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KATMAIP-FP2 SoC"; + compatible = "qcom,yupikp-iot"; + qcom,msm-id = <575 0x10000>; + qcom,softsku-id = <2>; +}; + +&soc { + qcom,rmnet-ipa { + status = "disabled"; + }; +}; + +&ipa_hw { + status = "disabled"; +}; diff --git a/qcom/katmaip-hsp-overlay.dts b/qcom/katmaip-hsp-overlay.dts index bb8b4be0978e..bf4f8af03708 100644 --- a/qcom/katmaip-hsp-overlay.dts +++ b/qcom/katmaip-hsp-overlay.dts @@ -5,8 +5,9 @@ #include "katmaip-hsp.dtsi" / { - model = "Qualcomm Technologies, Inc. YupikP IoT HSP"; + model = "Qualcomm Technologies, Inc. KatmaiP IoT HSP"; compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; qcom,msm-id = <498 0x10000>, <575 0x10000>, <576 0x10000>; qcom,board-id = <34 1>; + qcom,softsku-id = <1>; }; diff --git a/qcom/katmaip-hsp-pm7250b-overlay.dts b/qcom/katmaip-hsp-pm7250b-overlay.dts index 69f48f511d31..1a4fa6d07817 100644 --- a/qcom/katmaip-hsp-pm7250b-overlay.dts +++ b/qcom/katmaip-hsp-pm7250b-overlay.dts @@ -4,8 +4,9 @@ #include "katmaip-hsp-pm7250b.dtsi" / { - model = "Qualcomm Technologies, Inc. YupikP IOT HSP + PM7250B"; + model = "Qualcomm Technologies, Inc. KatmaiP IOT HSP + PM7250B"; compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp"; qcom,msm-id = <498 0x10000>, <575 0x10000>, <576 0x10000>; qcom,board-id = <34 1>; + qcom,softsku-id = <1>; }; diff --git a/qcom/katmaip.dtsi b/qcom/katmaip.dtsi index ebc82acfc62e..d9e2b81adefc 100644 --- a/qcom/katmaip.dtsi +++ b/qcom/katmaip.dtsi @@ -4,6 +4,7 @@ model = "Qualcomm Technologies, Inc. KATMAIP SoC"; compatible = "qcom,yupikp-iot"; qcom,msm-id = <575 0x10000>; + qcom,softsku-id = <1>; }; &cam_csid2 { From 52616a2238bd6511d28a64b8c042f25824768bde Mon Sep 17 00:00:00 2001 From: Deven Solanki Date: Wed, 10 Aug 2022 18:43:48 +0530 Subject: [PATCH 109/122] ARM: dts: msm: add display config support for katmai Add support for DSI display configuration for katmai platform. Change-Id: I75b55b4734d55015bc718c4e913d315fd7fa0e65 --- qcom/katmai.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qcom/katmai.dtsi b/qcom/katmai.dtsi index 4c20a8c70358..73eeb08a7daa 100644 --- a/qcom/katmai.dtsi +++ b/qcom/katmai.dtsi @@ -46,3 +46,14 @@ &cam_vfe2 { status = "disabled"; }; + +&mdss_dsi0 { + /delete-property/reg; + /delete-property/reg-names; + + reg = <0xae94000 0x400>, + <0xaf08000 0x4>, + <0x0ae36000 0x300>, + <0xc00c6000 0x01000>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base", "disp_conf"; +}; From c495307cc5fccfe0bd441996d4d9187db4c04f80 Mon Sep 17 00:00:00 2001 From: Om Parkash Date: Thu, 18 Aug 2022 14:21:06 +0530 Subject: [PATCH 110/122] ARM: dts: msm: Disable csid2 & vfe2 nodes Disable csid2 & vfe2 nodes. Change-Id: I837ddec77ee2c40c7b4ab9b13d971a82043207ec --- qcom/katmai-fp2.dtsi | 8 ++++++++ qcom/katmaip-fp2.dtsi | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/qcom/katmai-fp2.dtsi b/qcom/katmai-fp2.dtsi index 74ac5fcd2324..453fbb9b19ea 100644 --- a/qcom/katmai-fp2.dtsi +++ b/qcom/katmai-fp2.dtsi @@ -39,3 +39,11 @@ }; }; }; + +&cam_csid2 { + status = "disabled"; +}; + +&cam_vfe2 { + status = "disabled"; +}; diff --git a/qcom/katmaip-fp2.dtsi b/qcom/katmaip-fp2.dtsi index 9296d0e29903..0d0c02ff0f9e 100644 --- a/qcom/katmaip-fp2.dtsi +++ b/qcom/katmaip-fp2.dtsi @@ -16,3 +16,11 @@ &ipa_hw { status = "disabled"; }; + +&cam_csid2 { + status = "disabled"; +}; + +&cam_vfe2 { + status = "disabled"; +}; From f724d9203d125155d5a4b5fdadabde92c79c89e2 Mon Sep 17 00:00:00 2001 From: Sai Pavan Akhil Remella Date: Fri, 2 Sep 2022 15:07:47 +0530 Subject: [PATCH 111/122] ARM: dts: msm: cnss: Update DDR/SNOC voting values Update values for DDR/SNOC voting for ultra high and super high modes. Currently there is index mismatch in selecting the mode from qcx6490-cnss.dtsi file. This commit adds values to the missing modes. Change-Id: I16b6d6c1fe9a2531431c11ef586c023c05d9ac72 CRs-Fixed: 3282161 --- qcom/qcx6490-cnss.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/qcom/qcx6490-cnss.dtsi b/qcom/qcx6490-cnss.dtsi index 5c50c7e7fb45..817bca47eede 100644 --- a/qcom/qcx6490-cnss.dtsi +++ b/qcom/qcx6490-cnss.dtsi @@ -32,7 +32,7 @@ interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr"; qcom,icc-path-count = <2>; - qcom,bus-bw-cfg-count = <7>; + qcom,bus-bw-cfg-count = <9>; qcom,bus-bw-cfg = /** ICC Path 1 **/ <0 0>, /* no vote */ @@ -46,6 +46,10 @@ <100000 790000>, /* very high: > 1080 Mbps snoc/anoc: 403 Mhz ddr: 451.2 MHz */ <175000 1600000>, + /* Ultra high */ + <0 0>, + /* Super High */ + <0 0>, /* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz * ddr: 547.2 MHz */ @@ -58,6 +62,8 @@ <30000 1804800>, <100000 1804800>, <175000 6220800>, + <0 0>, + <0 0>, <7500 2188800>; mhi,max-channels = <30>; From 70602d12d95b418c0195024f50f415239fa20f94 Mon Sep 17 00:00:00 2001 From: Jyothi Kumar Seerapu Date: Mon, 19 Sep 2022 13:48:56 +0530 Subject: [PATCH 112/122] ARM: dts: qcom: Enable PCIe halt feature on sdxlemur In sdxlemur, with PCIe halt feature disable, IPA has raised some SMMU errors due to out of order of transactions. So, enabled the PCIe halt feature to default, which is PCIe write halt enable with 1MB and enable PCIe read halt. Change-Id: I660b6bc16db3af05bdedc67ea28c92ee769166db --- qcom/sdxlemur-pcie.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index 437bac326385..05b1db8be5e1 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -115,7 +115,6 @@ qcom,slv-addr-space-size = <0x40000000>; qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; - qcom,pcie-halt-feature-dis; qcom,pcie-phy-ver = <1108>; qcom,phy-status-offset = <0x1214>; From eb11fccd7327197035afe41884c02734244fe3f5 Mon Sep 17 00:00:00 2001 From: Deepak Kumar Date: Thu, 4 Aug 2022 12:21:02 +0530 Subject: [PATCH 113/122] ARM: dts: msm: Add 738MHz GPU speed bins support for SM8325 Enable 738MHz GPU FMAX speed bin as per latest requirement. Change-Id: I0ac67e370831b9e6d91d2e62d885c42d43ef0cfd --- qcom/lahaina-v2-gpu.dtsi | 135 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 135 insertions(+) diff --git a/qcom/lahaina-v2-gpu.dtsi b/qcom/lahaina-v2-gpu.dtsi index 23b477a5fa54..b16c675a6abc 100644 --- a/qcom/lahaina-v2-gpu.dtsi +++ b/qcom/lahaina-v2-gpu.dtsi @@ -899,5 +899,140 @@ qcom,acd-level = <0x882f5ffd>; }; }; + + qcom,gpu-pwrlevels-5 { + #address-cells = <1>; + #size-cells = <0>; + qcom,speed-bin = <4>; + qcom,initial-pwrlevel = <7>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <738000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82a5ffd>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <676000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <10>; + qcom,bus-min-ddr8 = <10>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882b5ffd>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <608000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82b5ffd>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <540000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0xa82c5ffd>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <491000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82c5ffd>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82d5ffd>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <379000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882e5ffd>; + }; + + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <315000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <2>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <2>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882f5ffd>; + }; + }; }; }; From cb9b3a6b50ad6cbee566eea5a47fa7e07ebb7a8b Mon Sep 17 00:00:00 2001 From: Deven Solanki Date: Mon, 26 Sep 2022 18:33:09 +0530 Subject: [PATCH 114/122] ARM: dts: msm: add display config support for katmai FP2 Add support for DSI display configuration for katmai FP2 target. Change-Id: Ibf9873000b4a3fc251f1b8bb7488ffb402223d28 --- qcom/katmai-fp2.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qcom/katmai-fp2.dtsi b/qcom/katmai-fp2.dtsi index 453fbb9b19ea..180a619f8f01 100644 --- a/qcom/katmai-fp2.dtsi +++ b/qcom/katmai-fp2.dtsi @@ -47,3 +47,14 @@ &cam_vfe2 { status = "disabled"; }; + +&mdss_dsi0 { + /delete-property/reg; + /delete-property/reg-names; + + reg = <0xae94000 0x400>, + <0xaf08000 0x4>, + <0x0ae36000 0x300>, + <0xc00c6000 0x01000>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base", "disp_conf"; +}; From f5dab9168284cc4190d08de6a1b94a75f0c3e454 Mon Sep 17 00:00:00 2001 From: Lakshit Tyagi Date: Wed, 14 Sep 2022 10:34:42 +0530 Subject: [PATCH 115/122] ARM: dts: msm: Increase R8125 ring size Increase r8125 TX ring size to 4K. Change-Id: I0bbcc5c14bb9df6a4cb383753c0f429966a692fb --- qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi index 6bd0120779cc..c2d9043b1248 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi @@ -40,7 +40,7 @@ ioss_r8125_eth0_tx: r8125_tx@eth0 { qcom,dir-tx; - qcom,ring-size = <1024>; + qcom,ring-size = <4096>; qcom,buff-size = <2048>; qcom,mod-count-min = <32>; From 6b19d22b6d1e8e9b373f3e8fdd27e0aab872a84e Mon Sep 17 00:00:00 2001 From: Jyothi Kumar Seerapu Date: Wed, 28 Sep 2022 09:24:44 +0530 Subject: [PATCH 116/122] ARM: dts: qcom: Set PCIe Wr halt window size to 1GB for sdxlemur This will set the PCIe Wr halt window size to 1GB and disables BDF halt for sdxlemur for PINE attach. In sdxlemur for PINE attaches observed throughput degradation because of PCIe latencies, this is due to PCIe write halt window of 1MB and BDF halt feature enable. So, disabled BDF halt feature and increased PCIe Wr halt window size to 1GB for sdxlemur. Change-Id: I604fcc646a64cddb9502f31c7c357ddc476f741f --- bindings/pci/pci-msm.txt | 6 ++++++ qcom/sdxlemur-mtp-cpe-pine1x.dtsi | 2 ++ qcom/sdxlemur-mtp-cpe-pine2x.dtsi | 3 +++ qcom/sdxlemur-pcie.dtsi | 1 - 4 files changed, 11 insertions(+), 1 deletion(-) diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index 30addf402558..09fdfa102583 100644 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -419,6 +419,12 @@ interconnects: Value type : Definition: Disable PCIe Write and Read halt feature +- qcom, qcom,bdf-halt-dis: + Usage: optional + Value type : + Definition: Disables the BDF halt feature which halt inbound + write transactions when BDF change is detected. + ============== Root port node ============== diff --git a/qcom/sdxlemur-mtp-cpe-pine1x.dtsi b/qcom/sdxlemur-mtp-cpe-pine1x.dtsi index 38eee1a933e8..baff76c38128 100644 --- a/qcom/sdxlemur-mtp-cpe-pine1x.dtsi +++ b/qcom/sdxlemur-mtp-cpe-pine1x.dtsi @@ -22,6 +22,8 @@ qcom,no-l1-supported; qcom,no-l1ss-supported; qcom,no-aux-clk-sync; + qcom,bdf-halt-dis; + qcom,wr-halt-size = <0x1e>; }; &pcie0_bus2_dev1_fn0 { diff --git a/qcom/sdxlemur-mtp-cpe-pine2x.dtsi b/qcom/sdxlemur-mtp-cpe-pine2x.dtsi index ac102dfe643b..54fe439cabf0 100644 --- a/qcom/sdxlemur-mtp-cpe-pine2x.dtsi +++ b/qcom/sdxlemur-mtp-cpe-pine2x.dtsi @@ -38,6 +38,9 @@ qcom,no-l1-supported; qcom,no-l1ss-supported; qcom,no-aux-clk-sync; + qcom,bdf-halt-dis; + qcom,wr-halt-size = <0x1e>; + }; &pcie0_bus2_dev1_fn0 { diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index 437bac326385..05b1db8be5e1 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -115,7 +115,6 @@ qcom,slv-addr-space-size = <0x40000000>; qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; - qcom,pcie-halt-feature-dis; qcom,pcie-phy-ver = <1108>; qcom,phy-status-offset = <0x1214>; From 3835d326e9b2149f8f5ddccb6b843382284a75eb Mon Sep 17 00:00:00 2001 From: HuaWen CHEN Date: Mon, 10 Oct 2022 11:08:32 +0800 Subject: [PATCH 117/122] ARM: dts: msm: change WLAN IOVA address To ensure 1GB separation between iommu-ddr and iommu-ipa. Change-Id: I6363f5de66d3d1e2173a5285a173402b5b8a147e --- qcom/sdxlemur-cnss.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur-cnss.dtsi b/qcom/sdxlemur-cnss.dtsi index 469c03a51321..49483d12f328 100644 --- a/qcom/sdxlemur-cnss.dtsi +++ b/qcom/sdxlemur-cnss.dtsi @@ -16,7 +16,7 @@ &soc { wlan: qcom,cnss-qca6490@b0000000 { compatible = "qcom,cnss-qca6490"; - reg = <0xb0000000 0x10000>, + reg = <0xc0000000 0x10000>, <0xb2e5510 0x690>; reg-names = "smmu_iova_ipa", "tcs_cmd"; wlan-en-gpio = <&tlmm 91 0>; @@ -197,7 +197,7 @@ #size-cells = <1>; cnss_pci_iommu_group: cnss_pci_iommu_group { - qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-dma-addr-pool = <0xa0000000 0x20000000>; qcom,iommu-dma = "fastmap"; qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE", "non-fatal"; From cf582767fed1a6102ae6a07c24e95f86c46e5630 Mon Sep 17 00:00:00 2001 From: Shirshendu Prakash Naveen Date: Thu, 8 Sep 2022 13:44:03 +0530 Subject: [PATCH 118/122] ARM: dts: msm: Add cpu related changes for Katmai targets Update CPU related changes for Katmai Fp1 targets 4xgold A78 (2.1GHz) +4x Silver A55 (1.8GHz). Change it to make 2 cluster approach. Change-Id: Ib7e44768bf94186a2f6ee156bed8a78c438aec88 --- qcom/katmai-cpu.dtsi | 361 ------------------------------------------- qcom/katmai.dtsi | 2 +- 2 files changed, 1 insertion(+), 362 deletions(-) delete mode 100644 qcom/katmai-cpu.dtsi diff --git a/qcom/katmai-cpu.dtsi b/qcom/katmai-cpu.dtsi deleted file mode 100644 index 86771b11ca9f..000000000000 --- a/qcom/katmai-cpu.dtsi +++ /dev/null @@ -1,361 +0,0 @@ -/ { - /delete-node/ cpus; -// /delete-node/ energy-costs; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo"; - reg = <0x0 0x0>; - enable-method = "psci"; - cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <100>; - qcom,freq-domain = <&cpufreq_hw 0 4>; - next-level-cache = <&L2_0>; - #cooling-cells = <2>; - L2_0: l2-cache { - compatible = "arm,arch-cache"; - cache-level = <2>; - next-level-cache = <&L3_0>; - - L3_0: l3-cache { - compatible = "arm,arch-cache"; - cache-level = <3>; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo"; - reg = <0x0 0x100>; - enable-method = "psci"; - cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <100>; - qcom,freq-domain = <&cpufreq_hw 0 4>; - next-level-cache = <&L2_1>; - L2_1: l2-cache { - compatible = "arm,arch-cache"; - cache-level = <2>; - next-level-cache = <&L3_0>; - }; - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo"; - reg = <0x0 0x200>; - enable-method = "psci"; - cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <100>; - qcom,freq-domain = <&cpufreq_hw 0 4>; - next-level-cache = <&L2_2>; - L2_2: l2-cache { - compatible = "arm,arch-cache"; - cache-level = <2>; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo"; - reg = <0x0 0x300>; - enable-method = "psci"; - cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <100>; - qcom,freq-domain = <&cpufreq_hw 0 4>; - next-level-cache = <&L2_3>; - L2_3: l2-cache { - compatible = "arm,arch-cache"; - cache-level = <2>; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo"; - reg = <0x0 0x400>; - enable-method = "psci"; - cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; - capacity-dmips-mhz = <1946>; - dynamic-power-coefficient = <520>; - qcom,freq-domain = <&cpufreq_hw 1 4>; - next-level-cache = <&L2_4>; - #cooling-cells = <2>; - L2_4: l2-cache { - compatible = "arm,arch-cache"; - cache-level = <2>; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo"; - reg = <0x0 0x500>; - enable-method = "psci"; - cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; - capacity-dmips-mhz = <1946>; - dynamic-power-coefficient = <520>; - qcom,freq-domain = <&cpufreq_hw 1 4>; - next-level-cache = <&L2_5>; - L2_5: l2-cache { - compatible = "arm,arch-cache"; - cache-level = <2>; - next-level-cache = <&L3_0>; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - }; - - cluster1 { - core0 { - cpu = <&CPU4>; - }; - - core1 { - cpu = <&CPU5>; - }; - }; - }; - }; -}; - -&soc { - /delete-node/ jtagmm@7640000; - /delete-node/ jtagmm@7740000; - qcom,cpu0-cpugrp { - /delete-property/ qcom,cpulist; - qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; - qcom,cpu4-cpu-llcc-latmon { - /delete-property/ qcom,cpulist; - qcom,cpulist = <&CPU4 &CPU5>; - qcom,core-dev-table = - < 691200 MHZ_TO_MBPS( 300, 16) >, - < 940800 MHZ_TO_MBPS( 466, 16) >, - < 1228800 MHZ_TO_MBPS( 600, 16) >, - < 1651200 MHZ_TO_MBPS( 806, 16) >; - }; - - qcom,cpu4-llcc-ddr-latmon { - /delete-property/ qcom,cpulist; - qcom,cpulist = <&CPU4 &CPU5>; - ddr4-map { - qcom,core-dev-table = - < 691200 MHZ_TO_MBPS( 451, 4) >, - < 940800 MHZ_TO_MBPS( 547, 4) >, - < 1228800 MHZ_TO_MBPS(1017, 4) >, - < 1651200 MHZ_TO_MBPS(1555, 4) >; - }; - - ddr5-map { - qcom,core-dev-table = - < 691200 MHZ_TO_MBPS( 451, 4) >, - < 940800 MHZ_TO_MBPS( 547, 4) >, - < 1228800 MHZ_TO_MBPS( 768, 4) >, - < 1651200 MHZ_TO_MBPS(1555, 4) >, - < 1900800 MHZ_TO_MBPS(1708, 4) >; - }; - }; - - qcom,cpu4-computemon { - /delete-property/ qcom,cpulist; - qcom,cpulist = <&CPU4 &CPU5>; - ddr4-map { - qcom,core-dev-table = - < 691200 MHZ_TO_MBPS( 451, 4) >, - < 1228800 MHZ_TO_MBPS( 547, 4) >, - < 1516800 MHZ_TO_MBPS( 768, 4) >, - < 1651200 MHZ_TO_MBPS(1017, 4) >, - < 1900800 MHZ_TO_MBPS(1555, 4) >; - }; - - ddr5-map { - qcom,core-dev-table = - < 691200 MHZ_TO_MBPS( 451, 4) >, - < 1228800 MHZ_TO_MBPS( 547, 4) >, - < 1516800 MHZ_TO_MBPS( 768, 4) >, - < 1651200 MHZ_TO_MBPS(1555, 4) >, - < 1900800 MHZ_TO_MBPS(1708, 4) >; - }; - }; - - qcom,cpu4-llcc-computemon { - /delete-property/ qcom,cpulist; - qcom,cpulist = <&CPU4 &CPU5>; - qcom,core-dev-table = - < 1900800 MHZ_TO_MBPS( 150, 16) >; - }; - - qcom,cpu4-qoslatmon { - /delete-property/ qcom,cpulist; - qcom,cpulist = <&CPU4 &CPU5>; - }; - - - /delete-node/ qcom,cpu7-qoslatmon; - /delete-node/ qcom,cpu7-l3-computemon; - /delete-node/ qcom,cpu7-computemon; - }; - - qcom,cpu4_grp { - /delete-property/ qcom,cpulist; - qcom,cpulist = <&CPU4 &CPU5>; - - qcom,cpu4-rimps-l3-latmon { - /delete-property/ qcom,cpulist; - qcom,cpulist = <&CPU4 &CPU5>; - qcom,core-dev-table = - < 940800 556800000 >, - < 1228800 768000000 >, - < 1651200 1190400000 >, - < 1900800 1401600000 >; - }; - }; - - /delete-node/ qcom,cpu7-cpu-ddr-latfloor; - /delete-node/ qcom,cpu7-cpu-l3-latfloor; - /delete-node/ qcom,cpu7-cpu-ddr-qoslatfloor; - /delete-node/ qcom,cpu7_grp; - /delete-node/ etm@7640000; - /delete-node/ etm@7740000; - /delete-node/ cti@7620000; - /delete-node/ cti@7720000; - - qcom,lpm-levels { - qcom,pm-cluster@0 { - qcom,pm-cpu@1 { - /delete-property/ qcom,cpu; - qcom,cpu = <&CPU4 &CPU5>; - }; - }; - }; -}; - -&cpufreq_hw { - qcom,cpu-isolation { - cpu6_isolate: cpu6-isolate { - /delete-property/ qcom,cpu; - }; - - - cpu7_isolate: cpu7-isolate { - /delete-property/ qcom,cpu; - }; - }; - - qcom,cpu-hotplug { - cpu6_hotplug: cpu6-hotplug { - /delete-property/ qcom,cpu; - }; - - - cpu7_hotplug: cpu7-hotplug { - /delete-property/ qcom,cpu; - }; - }; - - qcom,cpu-voltage-cdev { - apc1_cluster: thermal-cluster-4-7 { - /delete-property/ qcom,cluster0; - /delete-property/ qcom,cluster1; - }; - }; - -}; - -&funnel_apss { - in-ports { - /delete-node/ port@6; - /delete-node/ port@7; - }; -}; - -&thermal_zones { - cpu-1-0-step { - cooling-maps { - /delete-node/ cpu10_cdev1; - }; - }; - - cpu-1-1-step { - cooling-maps { - /delete-node/ cpu11_cdev1; - }; - }; - - cpu-1-2-step { - cooling-maps { - /delete-node/ cpu12_cdev1; - }; - }; - - cpu-1-3-step { - cooling-maps { - /delete-node/ cpu13_cdev1; - }; - }; - - cpu-1-4-step { - cooling-maps { - /delete-node/ cpu14_cdev; - /delete-node/ cpu14_cdev1; - /delete-node/ cpu14_cdev2; - }; - }; - - cpu-1-5-step { - cooling-maps { - /delete-node/ cpu15_cdev; - /delete-node/ cpu15_cdev1; - /delete-node/ cpu15_cdev2; - }; - }; - - cpu-1-6-step { - cooling-maps { - /delete-node/ cpu16_cdev; - /delete-node/ cpu16_cdev2; - }; - }; - - cpu-1-7-step { - cooling-maps { - /delete-node/ cpu17_cdev; - /delete-node/ cpu17_cdev2; - }; - }; - - mx-pe-step { - cooling-maps { - /delete-node/ mx_pe_cdev_cpu6; - /delete-node/ mx_pe_cdev_cpu7; - }; - }; -}; diff --git a/qcom/katmai.dtsi b/qcom/katmai.dtsi index 090f1fda63f3..58b7e15ad52f 100644 --- a/qcom/katmai.dtsi +++ b/qcom/katmai.dtsi @@ -1,5 +1,5 @@ #include "yupik-iot.dtsi" -#include "katmai-cpu.dtsi" +#include "katmai-cpu-fp2.dtsi" / { model = "Qualcomm Technologies, Inc. KATMAI SoC"; From c594bd2fdfa33b5553948ddff31c5e3535a38e8b Mon Sep 17 00:00:00 2001 From: Jyothi Kumar Seerapu Date: Fri, 14 Oct 2022 19:16:12 +0530 Subject: [PATCH 119/122] ARM: dts: qcom: Set PCIe Wr halt to 1GB and disable BDF halt for sdxlemur This change will set the PCIe Wr halt window size to 1GB and disables BDF halt for sdxlemur for HSP CPE attach. In sdxlemur for HSP CPE attaches observed throughput degradation due to PCIe latencies with default PCIe write halt window of 1MB and BDF halt feature enable. So, increased PCIe Wr halt window size to 1GB and disabled BDF halt for sdxlemur. Change-Id: Ibfcccd54e91fa18702bce8b81402acce34bfdc5e --- qcom/sdxlemur-mtp-cpe-hsp.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe-hsp.dtsi b/qcom/sdxlemur-mtp-cpe-hsp.dtsi index e8ba2208d897..477a478c99db 100644 --- a/qcom/sdxlemur-mtp-cpe-hsp.dtsi +++ b/qcom/sdxlemur-mtp-cpe-hsp.dtsi @@ -2,6 +2,8 @@ &pcie0 { qcom,boot-option = <0x1>; + qcom,bdf-halt-dis; + qcom,wr-halt-size = <0x1e>; }; &pcie0_bus2_dev2_fn0 { From 0a1fb1d0380e510c984f3b0a4979d21ae2741877 Mon Sep 17 00:00:00 2001 From: Pradnya Dahiwale Date: Thu, 29 Sep 2022 22:02:46 +0530 Subject: [PATCH 120/122] ARM: dts: msm: CPU changes for katmai target Updated DT changes for for Katmai targets 4xgold A78(2.1GHz) +4x Silver A55(1.8GHz). Change-Id: I81649f0117445ab5157555f0d9dfe7266453dfe2 --- qcom/katmai-cpu-fp2.dtsi | 343 ++++++++++++++++++++++++++++++--------- 1 file changed, 266 insertions(+), 77 deletions(-) diff --git a/qcom/katmai-cpu-fp2.dtsi b/qcom/katmai-cpu-fp2.dtsi index f7af471759e9..045ae1660bb3 100644 --- a/qcom/katmai-cpu-fp2.dtsi +++ b/qcom/katmai-cpu-fp2.dtsi @@ -1,89 +1,278 @@ -&cpu4_cpu_llcc_latmon { - qcom,core-dev-table = - < 691200 MHZ_TO_MBPS( 300, 16) >, - < 940800 MHZ_TO_MBPS( 466, 16) >, - < 1228800 MHZ_TO_MBPS( 600, 16) >, - < 1651200 MHZ_TO_MBPS( 806, 16) >; -}; +/ { + /delete-node/ cpus; +// /delete-node/ energy-costs; -&cpu4_llcc_ddr_latmon { - ddr4-map { - qcom,core-dev-table = - < 691200 MHZ_TO_MBPS( 451, 4) >, - < 940800 MHZ_TO_MBPS( 547, 4) >, - < 1228800 MHZ_TO_MBPS(1017, 4) >, - < 1651200 MHZ_TO_MBPS(1555, 4) >; - }; + cpus { + #address-cells = <2>; + #size-cells = <0>; - ddr5-map { - qcom,core-dev-table = - < 691200 MHZ_TO_MBPS( 451, 4) >, - < 940800 MHZ_TO_MBPS( 547, 4) >, - < 1228800 MHZ_TO_MBPS( 768, 4) >, - < 1651200 MHZ_TO_MBPS(1555, 4) >, - < 1900800 MHZ_TO_MBPS(1708, 4) >; + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + qcom,freq-domain = <&cpufreq_hw 0 4>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <3>; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + qcom,freq-domain = <&cpufreq_hw 0 4>; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + qcom,freq-domain = <&cpufreq_hw 0 4>; + next-level-cache = <&L2_2>; + L2_2: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + qcom,freq-domain = <&cpufreq_hw 0 4>; + next-level-cache = <&L2_3>; + L2_3: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x400>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <520>; + qcom,freq-domain = <&cpufreq_hw 1 4>; + next-level-cache = <&L2_4>; + #cooling-cells = <2>; + L2_4: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x500>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <520>; + qcom,freq-domain = <&cpufreq_hw 1 4>; + next-level-cache = <&L2_5>; + L2_5: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x600>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <520>; + qcom,freq-domain = <&cpufreq_hw 1 4>; + next-level-cache = <&L2_6>; + L2_6: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x700>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + capacity-dmips-mhz = <1964>; + dynamic-power-coefficient = <520>; + qcom,freq-domain = <&cpufreq_hw 1 4>; + next-level-cache = <&L2_7>; + L2_7: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; }; }; -&cpu4_computemon { - ddr4-map { - qcom,core-dev-table = - < 691200 MHZ_TO_MBPS( 451, 4) >, - < 1228800 MHZ_TO_MBPS( 547, 4) >, - < 1516800 MHZ_TO_MBPS( 768, 4) >, - < 1651200 MHZ_TO_MBPS(1017, 4) >, - < 1900800 MHZ_TO_MBPS(1555, 4) >; +&soc { + qcom,cpu0-cpugrp { + qcom,cpu4-cpu-llcc-latmon { + qcom,core-dev-table = + < 691200 MHZ_TO_MBPS( 300, 16) >, + < 940800 MHZ_TO_MBPS( 466, 16) >, + < 1228800 MHZ_TO_MBPS( 600, 16) >, + < 1651200 MHZ_TO_MBPS( 806, 16) >; + }; + + qcom,cpu4-llcc-ddr-latmon { + ddr4-map { + qcom,core-dev-table = + < 691200 MHZ_TO_MBPS( 451, 4) >, + < 940800 MHZ_TO_MBPS( 547, 4) >, + < 1228800 MHZ_TO_MBPS(1017, 4) >, + < 1651200 MHZ_TO_MBPS(1555, 4) >; + }; + + ddr5-map { + qcom,core-dev-table = + < 691200 MHZ_TO_MBPS( 451, 4) >, + < 940800 MHZ_TO_MBPS( 547, 4) >, + < 1228800 MHZ_TO_MBPS( 768, 4) >, + < 1651200 MHZ_TO_MBPS(1555, 4) >, + < 1900800 MHZ_TO_MBPS(1708, 4) >; + }; + }; + + qcom,cpu4-computemon { + /delete-property/ qcom,cpulist; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + ddr4-map { + qcom,core-dev-table = + < 691200 MHZ_TO_MBPS( 451, 4) >, + < 1228800 MHZ_TO_MBPS( 547, 4) >, + < 1516800 MHZ_TO_MBPS( 768, 4) >, + < 1651200 MHZ_TO_MBPS(1017, 4) >, + < 1900800 MHZ_TO_MBPS(1555, 4) >; + }; + + ddr5-map { + qcom,core-dev-table = + < 691200 MHZ_TO_MBPS( 451, 4) >, + < 1228800 MHZ_TO_MBPS( 547, 4) >, + < 1516800 MHZ_TO_MBPS( 768, 4) >, + < 1651200 MHZ_TO_MBPS(1555, 4) >, + < 1900800 MHZ_TO_MBPS(1708, 4) >; + }; + }; + + qcom,cpu4-llcc-computemon { + qcom,core-dev-table = + < 1900800 MHZ_TO_MBPS( 150, 16) >; + }; + + qcom,cpu4-qoslatmon { + /delete-property/ qcom,cpulist; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + }; + + /delete-node/ qcom,cpu7-qoslatmon; + /delete-node/ qcom,cpu7-l3-computemon; + /delete-node/ qcom,cpu7-computemon; }; - ddr5-map { - qcom,core-dev-table = - < 691200 MHZ_TO_MBPS( 451, 4) >, - < 1228800 MHZ_TO_MBPS( 547, 4) >, - < 1516800 MHZ_TO_MBPS( 768, 4) >, - < 1651200 MHZ_TO_MBPS(1555, 4) >, - < 1900800 MHZ_TO_MBPS(1708, 4) >; - }; -}; + qcom,cpu4_grp { + /delete-property/ qcom,cpulist; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; -&cpu4_llcc_computemon { - qcom,core-dev-table = - < 1900800 MHZ_TO_MBPS( 150, 16) >; -}; - -&cpu7_computemon { - ddr4-map { - qcom,core-dev-table = - < 2380800 MHZ_TO_MBPS( 451, 4) >; + qcom,cpu4-rimps-l3-latmon { + /delete-property/ qcom,cpulist; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,core-dev-table = + < 940800 556800000 >, + < 1228800 768000000 >, + < 1651200 1190400000 >, + < 1900800 1401600000 >; + }; }; - ddr5-map { - qcom,core-dev-table = - < 2380800 MHZ_TO_MBPS( 451, 4) >; - }; + /delete-node/ qcom,cpu7-cpu-ddr-latfloor; + /delete-node/ qcom,cpu7-cpu-l3-latfloor; + /delete-node/ qcom,cpu7-cpu-ddr-qoslatfloor; + /delete-node/ qcom,cpu7_grp; }; -&cpu7_l3_computemon { - qcom,core-dev-table = - < 2035200 300000000 >; -}; - -&cpu7_qoslatmon { - qcom,core-dev-table = - < 2035200 1 >; - -}; - -&cpu4_rimps_l3_latmon { - qcom,core-dev-table = - < 940800 556800000 >, - < 1228800 768000000 >, - < 1651200 1190400000 >, - < 1900800 1401600000 >; -}; - -&cpu7_rimps_l3_latmon { - qcom,core-dev-table = - < 1056000 556800000 >, - < 1324800 768000000 >, - < 1766400 1190400000 >; -}; From 920c0ba452e03dcc63a3325c60beb80058fdf0c9 Mon Sep 17 00:00:00 2001 From: Jyothi Kumar Seerapu Date: Mon, 17 Oct 2022 16:20:44 +0530 Subject: [PATCH 121/122] ARM: dts: qcom: Set PCIe Wr halt to 1GB and disable BDF halt for sdxlemur This change will set the PCIe Wr halt window size to 1GB and disables BDF halt for sdxlemur for HSP MBB direct attach. In sdxlemur for HSP MBB direct attaches observed throughput degradation due to PCIe latencies with default PCIe write halt window of 1MB and BDF halt feature enable. So, increased PCIe Wr halt window size to 1GB and disabled BDF halt for sdxlemur. Change-Id: If18101e5ea9b969a8f7d9dc66d2c795d5a960507 --- qcom/sdxlemur-mtp-mbb.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index 4127b6f32dc4..88692e8b80fc 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -29,6 +29,8 @@ &pcie0 { qcom,boot-option = <0x1>; + qcom,bdf-halt-dis; + qcom,wr-halt-size = <0x1e>; }; &pm7250b_vadc { From beba15262c6e7855356a1011f064fbc28e12a498 Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Fri, 11 Nov 2022 16:33:53 +0530 Subject: [PATCH 122/122] ARM: dts: msm: adding wdi client scaling exceptions For WLAN LAN-LAN use cases, there won't be any other peripheral vote and IPA vote will not scale correctly. Make changes to add scaling exceptions to vote correctly for WLAN standalone cases. Change-Id: I621fe76446e8a31fa5530d2eae9b43f2d120a6c7 --- qcom/sdxlemur-mtp-cpe-pine1x.dts | 4 ++++ qcom/sdxlemur-mtp-cpe-pine2x.dts | 1 + qcom/sdxlemur-v2-mtp-cpe-pine1x.dts | 4 ++++ qcom/sdxlemur-v2-mtp-cpe-pine2x.dts | 1 + 4 files changed, 10 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe-pine1x.dts b/qcom/sdxlemur-mtp-cpe-pine1x.dts index 7fa9d4a9e077..bf0c719460f4 100644 --- a/qcom/sdxlemur-mtp-cpe-pine1x.dts +++ b/qcom/sdxlemur-mtp-cpe-pine1x.dts @@ -12,3 +12,7 @@ "qcom,sdxlemur", "qcom,mtp"; qcom,board-id = <0x9010008 0x309>; }; + +&ipa_hw { + qcom,scaling-exceptions = "wdi", "1400", "4800", "10000"; +}; diff --git a/qcom/sdxlemur-mtp-cpe-pine2x.dts b/qcom/sdxlemur-mtp-cpe-pine2x.dts index bac797bbdba5..b32efdfad3f8 100644 --- a/qcom/sdxlemur-mtp-cpe-pine2x.dts +++ b/qcom/sdxlemur-mtp-cpe-pine2x.dts @@ -15,5 +15,6 @@ &ipa_hw { qcom,use-dual-pine-config; + qcom,scaling-exceptions = "wdi", "1400", "4800", "10000", "wdi1", "1400", "4800", "10000"; }; diff --git a/qcom/sdxlemur-v2-mtp-cpe-pine1x.dts b/qcom/sdxlemur-v2-mtp-cpe-pine1x.dts index f9b9f4cf7f00..0bc9d50d4566 100644 --- a/qcom/sdxlemur-v2-mtp-cpe-pine1x.dts +++ b/qcom/sdxlemur-v2-mtp-cpe-pine1x.dts @@ -12,3 +12,7 @@ "qcom,sdxlemur", "qcom,mtp"; qcom,board-id = <0x9010008 0x309>; }; + +&ipa_hw { + qcom,scaling-exceptions = "wdi", "1400", "4800", "10000"; +}; diff --git a/qcom/sdxlemur-v2-mtp-cpe-pine2x.dts b/qcom/sdxlemur-v2-mtp-cpe-pine2x.dts index fab16854eaad..9adb514f8274 100644 --- a/qcom/sdxlemur-v2-mtp-cpe-pine2x.dts +++ b/qcom/sdxlemur-v2-mtp-cpe-pine2x.dts @@ -15,5 +15,6 @@ &ipa_hw { qcom,use-dual-pine-config; + qcom,scaling-exceptions = "wdi", "1400", "4800", "10000", "wdi1", "1400", "4800", "10000"; };