mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-14 00:24:41 -04:00
Merge "clk: qcom: Add GPU clock driver for SM6150"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
95f9eaf581
7 changed files with 7023 additions and 0 deletions
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@ -683,6 +683,42 @@ config SM_DEBUGCC_YUPIK
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Say Y if you want to support the debug clocks such as clock measurement
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functionality.
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config SM_GCC_6150
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tristate "SM6150 Global Clock Controller"
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depends on COMMON_CLK_QCOM
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help
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Support for the global clock controller on Qualcomm Technologies, Inc
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SM6150 devices.
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Say Y if you want to use peripheral devices such as UART, SPI, I2C,
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USB, UFS, SD/eMMC, PCIe, etc.
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config SM_CAMCC_6150
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tristate "SM6150 Camera Clock Controller"
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select SM_GCC_6150
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help
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Support for the camera clock controller on Qualcomm Technologies, Inc
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SM6150 devices.
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Say Y if you want to support camera devices and functionality such as
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capturing pictures.
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config SM_DISPCC_6150
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tristate "SM6150 Display Clock Controller"
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select SM_GCC_6150
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help
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Support for the display clock controller on Qualcomm Technologies, Inc
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SM6150 devices.
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Say Y if you want to support display devices and functionality such as
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splash pictures.
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config SM_GPUCC_6150
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tristate "SM6150 Graphics Clock Controller"
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select SM_GCC_6150
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help
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Support for the graphics clock controller on Qualcomm Technologies, Inc.
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sm6150 devices.
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Say Y if you want to support graphics controller devices and
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functionality such as 3D graphics.
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endif
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config VIRTIO_CLK
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@ -71,6 +71,7 @@ obj-$(CONFIG_SDX_DEBUGCC_LEMUR) += debugcc-sdxlemur.o
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obj-$(CONFIG_SDX_DEBUGCC_NIGHTJAR) += debugcc-sdxnightjar.o
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obj-$(CONFIG_SDX_GCC_LEMUR) += gcc-sdxlemur.o
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obj-$(CONFIG_SDX_GCC_NIGHTJAR) += gcc-sdxnightjar.o
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obj-$(CONFIG_SM_CAMCC_6150) += camcc-sm6150.o
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obj-$(CONFIG_SM_CAMCC_8150) += camcc-sm8150.o
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obj-$(CONFIG_SM_CAMCC_SHIMA) += camcc-shima.o
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obj-$(CONFIG_SM_CAMCC_YUPIK) += camcc-yupik.o
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@ -78,14 +79,17 @@ obj-$(CONFIG_SM_DEBUGCC_8150) += debugcc-sm8150.o
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obj-$(CONFIG_SM_DEBUGCC_HOLI) += debugcc-holi.o
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obj-$(CONFIG_SM_DEBUGCC_SHIMA) += debugcc-shima.o
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obj-$(CONFIG_SM_DEBUGCC_YUPIK) += debugcc-yupik.o
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obj-$(CONFIG_SM_DISPCC_6150) += dispcc-sm6150.o
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obj-$(CONFIG_SM_DISPCC_8150) += dispcc-sm8150.o
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obj-$(CONFIG_SM_DISPCC_HOLI) += dispcc-holi.o
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obj-$(CONFIG_SM_DISPCC_SHIMA) += dispcc-shima.o
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obj-$(CONFIG_SM_DISPCC_YUPIK) += dispcc-yupik.o
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obj-$(CONFIG_SM_GCC_6150) += gcc-sm6150.o
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obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
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obj-$(CONFIG_SM_GCC_HOLI) += gcc-holi.o
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obj-$(CONFIG_SM_GCC_SHIMA) += gcc-shima.o
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obj-$(CONFIG_SM_GCC_YUPIK) += gcc-yupik.o
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obj-$(CONFIG_SM_GPUCC_6150) += gpucc-sm6150.o
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obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
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obj-$(CONFIG_SM_GPUCC_HOLI) += gpucc-holi.o
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obj-$(CONFIG_SM_GPUCC_SHIMA) += gpucc-shima.o
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1790
drivers/clk/qcom/camcc-sm6150.c
Normal file
1790
drivers/clk/qcom/camcc-sm6150.c
Normal file
File diff suppressed because it is too large
Load diff
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@ -445,6 +445,24 @@ static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
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.num_clks = ARRAY_SIZE(sm8150_rpmh_clocks),
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};
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static struct clk_hw *sm6150_rpmh_clocks[] = {
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[RPMH_CXO_CLK] = &sm8150_bi_tcxo.hw,
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[RPMH_CXO_CLK_A] = &sm8150_bi_tcxo_ao.hw,
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[RPMH_LN_BB_CLK2] = &sm8150_ln_bb_clk2.hw,
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[RPMH_LN_BB_CLK2_A] = &sm8150_ln_bb_clk2_ao.hw,
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[RPMH_LN_BB_CLK3] = &sm8150_ln_bb_clk3.hw,
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[RPMH_LN_BB_CLK3_A] = &sm8150_ln_bb_clk3_ao.hw,
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[RPMH_RF_CLK1] = &sm8150_rf_clk1.hw,
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[RPMH_RF_CLK1_A] = &sm8150_rf_clk1_ao.hw,
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[RPMH_RF_CLK2] = &sm8150_rf_clk2.hw,
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[RPMH_RF_CLK2_A] = &sm8150_rf_clk2_ao.hw,
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};
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static const struct clk_rpmh_desc clk_rpmh_sm6150 = {
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.clks = sm6150_rpmh_clocks,
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.num_clks = ARRAY_SIZE(sm6150_rpmh_clocks),
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};
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DEFINE_CLK_RPMH_ARC(lahaina, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2);
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DEFINE_CLK_RPMH_VRM_OPT(lahaina, div_clk1, div_clk1_ao, "divclka1", 2);
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DEFINE_CLK_RPMH_VRM(lahaina, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2);
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@ -651,6 +669,7 @@ static const struct of_device_id clk_rpmh_match_table[] = {
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{ .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
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{ .compatible = "qcom,kona-rpmh-clk", .data = &clk_rpmh_kona},
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{ .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
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{ .compatible = "qcom,sm6150-rpmh-clk", .data = &clk_rpmh_sm6150},
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{ .compatible = "qcom,lahaina-rpmh-clk", .data = &clk_rpmh_lahaina},
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{ .compatible = "qcom,shima-rpmh-clk", .data = &clk_rpmh_shima},
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{ .compatible = "qcom,sdxlemur-rpmh-clk", .data = &clk_rpmh_sdxlemur},
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937
drivers/clk/qcom/dispcc-sm6150.c
Normal file
937
drivers/clk/qcom/dispcc-sm6150.c
Normal file
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@ -0,0 +1,937 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,dispcc-sm6150.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "common.h"
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#include "vdd-level-sm6150.h"
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static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);
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enum {
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P_BI_TCXO,
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P_DISP_CC_PLL0_OUT_MAIN,
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P_DP_PHY_PLL_LINK_CLK,
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P_DP_PHY_PLL_VCO_DIV_CLK,
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P_DSI0_PHY_PLL_OUT_BYTECLK,
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P_DSI0_PHY_PLL_OUT_DSICLK,
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P_DSI1_PHY_PLL_OUT_DSICLK,
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P_GPLL0_OUT_MAIN,
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};
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static struct pll_vco disp_cc_pll_vco[] = {
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{ 500000000, 1000000000, 2 },
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};
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/* 576MHz configuration */
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static struct alpha_pll_config disp_cc_pll0_config = {
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.l = 0x1E,
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.vco_val = 0x2 << 20,
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.vco_mask = 0x3 << 20,
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.main_output_mask = BIT(0),
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.config_ctl_val = 0x4001055b,
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.test_ctl_hi_val = 0x1,
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.test_ctl_hi_mask = 0x1,
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};
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static struct clk_init_data disp_cc_pll0_sa6155 = {
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.name = "disp_cc_pll0",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_slew_ops,
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};
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static struct clk_alpha_pll disp_cc_pll0 = {
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.offset = 0x0,
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.vco_table = disp_cc_pll_vco,
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.num_vco = ARRAY_SIZE(disp_cc_pll_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.flags = SUPPORTS_DYNAMIC_UPDATE,
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.config = &disp_cc_pll0_config,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_pll0",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_ops,
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},
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.vdd_data = {
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 1100000000,
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[VDD_NOMINAL] = 2000000000},
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},
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},
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};
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static const struct parent_map disp_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_DP_PHY_PLL_LINK_CLK, 1 },
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{ P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
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};
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static const struct clk_parent_data disp_cc_parent_data_0[] = {
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{ .fw_name = "bi_tcxo" },
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{ .fw_name = "dp_phy_pll_link_clk", .name = "dp_phy_pll_link_clk" },
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{ .fw_name = "dp_phy_pll_vco_div_clk", .name =
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"dp_phy_pll_vco_div_clk" },
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};
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static const struct parent_map disp_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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};
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static const struct clk_parent_data disp_cc_parent_data_1[] = {
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{ .fw_name = "bi_tcxo" },
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};
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static const struct parent_map disp_cc_parent_map_2[] = {
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{ P_BI_TCXO, 0 },
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{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
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};
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static const struct clk_parent_data disp_cc_parent_data_2[] = {
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{ .fw_name = "bi_tcxo" },
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{ .fw_name = "dsi0_phy_pll_out_byteclk", .name =
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"dsi0_phy_pll_out_byteclk" },
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};
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static const struct parent_map disp_cc_parent_map_3[] = {
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{ P_BI_TCXO, 0 },
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{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
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{ P_GPLL0_OUT_MAIN, 4 },
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};
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static const struct clk_parent_data disp_cc_parent_data_3[] = {
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{ .fw_name = "bi_tcxo" },
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{ .hw = &disp_cc_pll0.clkr.hw },
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{ .fw_name = "gpll0" },
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};
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static const struct parent_map disp_cc_parent_map_4[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPLL0_OUT_MAIN, 4 },
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};
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static const struct clk_parent_data disp_cc_parent_data_4[] = {
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{ .fw_name = "bi_tcxo" },
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{ .fw_name = "gpll0" },
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};
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static const struct parent_map disp_cc_parent_map_5[] = {
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{ P_BI_TCXO, 0 },
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{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
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{ P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
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};
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static const struct clk_parent_data disp_cc_parent_data_5[] = {
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{ .fw_name = "bi_tcxo" },
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{ .fw_name = "dsi0_phy_pll_out_dsiclk", .name =
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"dsi0_phy_pll_out_dsiclk" },
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{ .fw_name = "dsi1_phy_pll_out_dsiclk", .name =
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"dsi1_phy_pll_out_dsiclk" },
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};
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static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0),
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F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
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{ }
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};
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static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
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.cmd_rcgr = 0x2170,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_4,
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.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
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.enable_safe_config = true,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_ahb_clk_src",
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.parent_data = disp_cc_parent_data_4,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
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.ops = &clk_rcg2_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER] = 19200000,
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[VDD_LOW] = 37500000,
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[VDD_NOMINAL] = 75000000},
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},
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};
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static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
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.cmd_rcgr = 0x20c0,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_2,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_byte0_clk_src",
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.parent_data = disp_cc_parent_data_2,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
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.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
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.ops = &clk_byte2_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER] = 164000000,
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[VDD_LOW] = 187500000},
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},
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};
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static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux1_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
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.cmd_rcgr = 0x2158,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_1,
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.freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_dp_aux_clk_src",
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.parent_data = disp_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
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.ops = &clk_rcg2_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER] = 19200000},
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},
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};
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static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = {
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F( 180000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0),
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F( 360000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0),
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{ }
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};
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static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
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.cmd_rcgr = 0x2110,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_0,
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.freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_dp_crypto_clk_src",
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.parent_data = disp_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
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.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER] = 180000,
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[VDD_LOW_L1] = 360000},
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},
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};
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static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = {
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F( 162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
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F( 270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
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F( 540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
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.cmd_rcgr = 0x20f4,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src,
|
||||
.enable_safe_config = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_link_clk_src",
|
||||
.parent_data = disp_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
||||
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.vdd_data = {
|
||||
.vdd_class = &vdd_cx,
|
||||
.num_rate_max = VDD_NUM,
|
||||
.rate_max = (unsigned long[VDD_NUM]) {
|
||||
[VDD_LOWER] = 270000,
|
||||
[VDD_LOW_L1] = 540000},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {
|
||||
.cmd_rcgr = 0x2140,
|
||||
.mnd_width = 16,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_0,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_pixel1_clk_src",
|
||||
.parent_data = disp_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
||||
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_dp_ops,
|
||||
},
|
||||
.clkr.vdd_data = {
|
||||
.vdd_class = &vdd_cx,
|
||||
.num_rate_max = VDD_NUM,
|
||||
.rate_max = (unsigned long[VDD_NUM]) {
|
||||
[VDD_LOWER] = 337500},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
|
||||
.cmd_rcgr = 0x2128,
|
||||
.mnd_width = 16,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_0,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_pixel_clk_src",
|
||||
.parent_data = disp_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
||||
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_dp_ops,
|
||||
},
|
||||
.clkr.vdd_data = {
|
||||
.vdd_class = &vdd_cx,
|
||||
.num_rate_max = VDD_NUM,
|
||||
.rate_max = (unsigned long[VDD_NUM]) {
|
||||
[VDD_LOWER] = 337500},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
|
||||
.cmd_rcgr = 0x20dc,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_2,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_esc0_clk_src",
|
||||
.parent_data = disp_cc_parent_data_2,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.vdd_data = {
|
||||
.vdd_class = &vdd_cx,
|
||||
.num_rate_max = VDD_NUM,
|
||||
.rate_max = (unsigned long[VDD_NUM]) {
|
||||
[VDD_LOWER] = 19200000},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
||||
F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
||||
F(307000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
|
||||
.cmd_rcgr = 0x2078,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_3,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
|
||||
.enable_safe_config = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_mdp_clk_src",
|
||||
.parent_data = disp_cc_parent_data_3,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.vdd_data = {
|
||||
.vdd_class = &vdd_cx,
|
||||
.num_rate_max = VDD_NUM,
|
||||
.rate_max = (unsigned long[VDD_NUM]) {
|
||||
[VDD_LOWER] = 192000000,
|
||||
[VDD_LOW] = 256000000,
|
||||
[VDD_LOW_L1] = 307200000},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
|
||||
.cmd_rcgr = 0x2060,
|
||||
.mnd_width = 8,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_5,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_pclk0_clk_src",
|
||||
.parent_data = disp_cc_parent_data_5,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
|
||||
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_pixel_ops,
|
||||
},
|
||||
.clkr.vdd_data = {
|
||||
.vdd_class = &vdd_cx,
|
||||
.num_rate_max = VDD_NUM,
|
||||
.rate_max = (unsigned long[VDD_NUM]) {
|
||||
[VDD_LOWER] = 183310056,
|
||||
[VDD_LOW] = 250000000},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
|
||||
.cmd_rcgr = 0x2090,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_3,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
|
||||
.enable_safe_config = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_rot_clk_src",
|
||||
.parent_data = disp_cc_parent_data_3,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.vdd_data = {
|
||||
.vdd_class = &vdd_cx,
|
||||
.num_rate_max = VDD_NUM,
|
||||
.rate_max = (unsigned long[VDD_NUM]) {
|
||||
[VDD_LOWER] = 192000000,
|
||||
[VDD_LOW] = 256000000,
|
||||
[VDD_LOW_L1] = 307200000},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
|
||||
.cmd_rcgr = 0x20a8,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_vsync_clk_src",
|
||||
.parent_data = disp_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.vdd_data = {
|
||||
.vdd_class = &vdd_cx,
|
||||
.num_rate_max = VDD_NUM,
|
||||
.rate_max = (unsigned long[VDD_NUM]) {
|
||||
[VDD_LOWER] = 19200000},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
|
||||
.reg = 0x20d8,
|
||||
.shift = 0,
|
||||
.width = 2,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_byte0_div_clk_src",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &disp_cc_mdss_byte0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
|
||||
.reg = 0x210c,
|
||||
.shift = 0,
|
||||
.width = 2,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dp_link_div_clk_src",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_ahb_clk = {
|
||||
.halt_reg = 0x2048,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2048,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_ahb_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_byte0_clk = {
|
||||
.halt_reg = 0x2024,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2024,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_byte0_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &disp_cc_mdss_byte0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
|
||||
.halt_reg = 0x2028,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2028,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_byte0_intf_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_dp_aux_clk = {
|
||||
.halt_reg = 0x2044,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2044,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_aux_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &disp_cc_mdss_dp_aux_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
|
||||
.halt_reg = 0x2038,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2038,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_crypto_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_dp_link_clk = {
|
||||
.halt_reg = 0x2030,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2030,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_link_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
|
||||
.halt_reg = 0x2034,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2034,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_link_intf_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_dp_pixel1_clk = {
|
||||
.halt_reg = 0x2040,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2040,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_pixel1_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
|
||||
.halt_reg = 0x203c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x203c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_pixel_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_esc0_clk = {
|
||||
.halt_reg = 0x202c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x202c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_esc0_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &disp_cc_mdss_esc0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_mdp_clk = {
|
||||
.halt_reg = 0x2008,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2008,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_mdp_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &disp_cc_mdss_mdp_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
|
||||
.halt_reg = 0x2018,
|
||||
.halt_check = BRANCH_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2018,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_mdp_lut_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &disp_cc_mdss_mdp_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
|
||||
.halt_reg = 0x4004,
|
||||
.halt_check = BRANCH_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x4004,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_non_gdsc_ahb_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_pclk0_clk = {
|
||||
.halt_reg = 0x2004,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2004,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_pclk0_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &disp_cc_mdss_pclk0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_rot_clk = {
|
||||
.halt_reg = 0x2010,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2010,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_rot_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &disp_cc_mdss_rot_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
|
||||
.halt_reg = 0x400c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x400c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_rscc_ahb_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
|
||||
.halt_reg = 0x4008,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x4008,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_rscc_vsync_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &disp_cc_mdss_vsync_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_vsync_clk = {
|
||||
.halt_reg = 0x2020,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2020,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_vsync_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &disp_cc_mdss_vsync_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_xo_clk = {
|
||||
.halt_reg = 0x6054,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x6054,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_xo_clk",
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap *disp_cc_sm6150_clocks[] = {
|
||||
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
|
||||
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
|
||||
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
|
||||
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
|
||||
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
|
||||
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
|
||||
[DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
|
||||
[DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
|
||||
[DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
|
||||
[DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr,
|
||||
[DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
|
||||
[DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
|
||||
[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] =
|
||||
&disp_cc_mdss_dp_link_div_clk_src.clkr,
|
||||
[DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
|
||||
[DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr,
|
||||
[DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] = &disp_cc_mdss_dp_pixel1_clk_src.clkr,
|
||||
[DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
|
||||
[DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
|
||||
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
|
||||
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
|
||||
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
|
||||
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
|
||||
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
|
||||
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
|
||||
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
|
||||
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
|
||||
[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
|
||||
[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
|
||||
[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
|
||||
[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
|
||||
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
|
||||
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
|
||||
[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
|
||||
[DISP_CC_XO_CLK] = &disp_cc_xo_clk.clkr,
|
||||
};
|
||||
|
||||
static const struct regmap_config disp_cc_sm6150_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x10000,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc disp_cc_sm6150_desc = {
|
||||
.config = &disp_cc_sm6150_regmap_config,
|
||||
.clks = disp_cc_sm6150_clocks,
|
||||
.num_clks = ARRAY_SIZE(disp_cc_sm6150_clocks),
|
||||
};
|
||||
|
||||
static const struct of_device_id disp_cc_sm6150_match_table[] = {
|
||||
{ .compatible = "qcom,sm6150-dispcc" },
|
||||
{ .compatible = "qcom,sa6155-dispcc" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, disp_cc_sm6150_match_table);
|
||||
|
||||
static void dispcc_sm6150_fixup_sa6155(struct platform_device *pdev)
|
||||
{
|
||||
vdd_cx.num_levels = VDD_NUM_SA6155;
|
||||
vdd_cx.cur_level = VDD_NUM_SA6155;
|
||||
disp_cc_pll0.clkr.hw.init = &disp_cc_pll0_sa6155;
|
||||
}
|
||||
|
||||
static int disp_cc_sm6150_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int ret, is_sa6155;
|
||||
|
||||
vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx");
|
||||
if (IS_ERR(vdd_cx.regulator[0])) {
|
||||
if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER))
|
||||
dev_err(&pdev->dev, "Unable to get vdd_cx regulator\n");
|
||||
return PTR_ERR(vdd_cx.regulator[0]);
|
||||
}
|
||||
|
||||
is_sa6155 = of_device_is_compatible(pdev->dev.of_node,
|
||||
"qcom,sa6155-dispcc");
|
||||
if (is_sa6155)
|
||||
dispcc_sm6150_fixup_sa6155(pdev);
|
||||
|
||||
regmap = qcom_cc_map(pdev, &disp_cc_sm6150_desc);
|
||||
if (IS_ERR(regmap)) {
|
||||
pr_err("Failed to map the disp_cc registers\n");
|
||||
return PTR_ERR(regmap);
|
||||
}
|
||||
|
||||
clk_alpha_pll_configure(&disp_cc_pll0, regmap, disp_cc_pll0.config);
|
||||
|
||||
ret = qcom_cc_really_probe(pdev, &disp_cc_sm6150_desc, regmap);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to register DISP CC clocks\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "Registered DISP CC clocks\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct platform_driver disp_cc_sm6150_driver = {
|
||||
.probe = disp_cc_sm6150_probe,
|
||||
.driver = {
|
||||
.name = "disp_cc-sm6150",
|
||||
.of_match_table = disp_cc_sm6150_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init disp_cc_sm6150_init(void)
|
||||
{
|
||||
return platform_driver_register(&disp_cc_sm6150_driver);
|
||||
}
|
||||
subsys_initcall(disp_cc_sm6150_init);
|
||||
|
||||
static void __exit disp_cc_sm6150_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&disp_cc_sm6150_driver);
|
||||
}
|
||||
module_exit(disp_cc_sm6150_exit);
|
||||
|
||||
MODULE_DESCRIPTION("QTI DISP_CC SM6150 Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
3630
drivers/clk/qcom/gcc-sm6150.c
Normal file
3630
drivers/clk/qcom/gcc-sm6150.c
Normal file
File diff suppressed because it is too large
Load diff
607
drivers/clk/qcom/gpucc-sm6150.c
Normal file
607
drivers/clk/qcom/gpucc-sm6150.c
Normal file
|
|
@ -0,0 +1,607 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,gpucc-sm6150.h>
|
||||
|
||||
#include "clk-alpha-pll.h"
|
||||
#include "clk-branch.h"
|
||||
#include "clk-rcg.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "common.h"
|
||||
#include "vdd-level-sm6150.h"
|
||||
|
||||
static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);
|
||||
static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_corner);
|
||||
|
||||
enum {
|
||||
P_BI_TCXO,
|
||||
P_GPLL0_OUT_MAIN,
|
||||
P_GPLL0_OUT_MAIN_DIV,
|
||||
P_GPU_CC_PLL0_2X_CLK,
|
||||
P_CRC_DIV_PLL0_OUT_AUX2,
|
||||
P_GPU_CC_PLL0_OUT_MAIN,
|
||||
P_GPU_CC_PLL1_OUT_AUX,
|
||||
P_CRC_DIV_PLL1_OUT_AUX2,
|
||||
P_GPU_CC_PLL1_OUT_MAIN,
|
||||
};
|
||||
|
||||
static struct pll_vco gpu_cc_pll0_vco[] = {
|
||||
{ 1000000000, 2000000000, 0 },
|
||||
};
|
||||
|
||||
static struct pll_vco gpu_cc_pll1_vco[] = {
|
||||
{ 500000000, 1000000000, 2 },
|
||||
};
|
||||
|
||||
/* 1020MHz configuration */
|
||||
static struct alpha_pll_config gpu_pll0_config = {
|
||||
.l = 0x35,
|
||||
.config_ctl_val = 0x4001055b,
|
||||
.test_ctl_hi_val = 0x1,
|
||||
.test_ctl_hi_mask = 0x1,
|
||||
.alpha_hi = 0x20,
|
||||
.alpha = 0x00,
|
||||
.alpha_en_mask = BIT(24),
|
||||
.vco_val = 0x0 << 20,
|
||||
.vco_mask = 0x3 << 20,
|
||||
.aux2_output_mask = BIT(2),
|
||||
};
|
||||
|
||||
static struct clk_init_data gpu_cc_pll0_sa6155 = {
|
||||
.name = "gpu_cc_pll0",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.fw_name = "bi_tcxo",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_slew_ops,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll gpu_cc_pll0 = {
|
||||
.offset = 0x0,
|
||||
.vco_table = gpu_cc_pll0_vco,
|
||||
.num_vco = ARRAY_SIZE(gpu_cc_pll0_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
|
||||
.flags = SUPPORTS_DYNAMIC_UPDATE,
|
||||
.config = &gpu_pll0_config,
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_pll0",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.fw_name = "bi_tcxo",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_ops,
|
||||
},
|
||||
.vdd_data = {
|
||||
.vdd_class = &vdd_mx,
|
||||
.num_rate_max = VDD_NUM,
|
||||
.rate_max = (unsigned long[VDD_NUM]) {
|
||||
[VDD_MIN] = 1100000000,
|
||||
[VDD_NOMINAL] = 2000000000},
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* 930MHz configuration */
|
||||
static struct alpha_pll_config gpu_pll1_config = {
|
||||
.l = 0x30,
|
||||
.config_ctl_val = 0x4001055b,
|
||||
.test_ctl_hi_val = 0x1,
|
||||
.test_ctl_hi_mask = 0x1,
|
||||
.alpha_hi = 0x70,
|
||||
.alpha = 0x00,
|
||||
.alpha_en_mask = BIT(24),
|
||||
.vco_val = 0x2 << 20,
|
||||
.vco_mask = 0x3 << 20,
|
||||
.aux2_output_mask = BIT(2),
|
||||
};
|
||||
|
||||
static struct clk_init_data gpu_cc_pll1_sa6155 = {
|
||||
.name = "gpu_cc_pll1",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.fw_name = "bi_tcxo",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_slew_ops,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll gpu_cc_pll1 = {
|
||||
.offset = 0x100,
|
||||
.vco_table = gpu_cc_pll1_vco,
|
||||
.num_vco = ARRAY_SIZE(gpu_cc_pll1_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
|
||||
.flags = SUPPORTS_DYNAMIC_UPDATE,
|
||||
.config = &gpu_pll1_config,
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_pll1",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.fw_name = "bi_tcxo",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_ops,
|
||||
},
|
||||
.vdd_data = {
|
||||
.vdd_class = &vdd_mx,
|
||||
.num_rate_max = VDD_NUM,
|
||||
.rate_max = (unsigned long[VDD_NUM]) {
|
||||
[VDD_MIN] = 1100000000,
|
||||
[VDD_NOMINAL] = 2000000000},
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor crc_div_pll0 = {
|
||||
.mult = 1,
|
||||
.div = 2,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "crc_div_pll0",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gpu_cc_pll0.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor crc_div_pll1 = {
|
||||
.mult = 1,
|
||||
.div = 2,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "crc_div_pll1",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gpu_cc_pll1.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_0[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
|
||||
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
|
||||
{ P_GPLL0_OUT_MAIN, 5 },
|
||||
{ P_GPLL0_OUT_MAIN_DIV, 6 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
|
||||
{ .fw_name = "bi_tcxo"},
|
||||
{ .hw = &gpu_cc_pll0.clkr.hw },
|
||||
{ .hw = &gpu_cc_pll1.clkr.hw },
|
||||
{ .fw_name = "gpll0"},
|
||||
{ .fw_name = "gpll0_out_main_div"},
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_1[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPU_CC_PLL0_2X_CLK, 1 },
|
||||
{ P_CRC_DIV_PLL0_OUT_AUX2, 2 },
|
||||
{ P_GPU_CC_PLL1_OUT_AUX, 3 },
|
||||
{ P_CRC_DIV_PLL1_OUT_AUX2, 4 },
|
||||
{ P_GPLL0_OUT_MAIN, 5 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
|
||||
{ .fw_name = "bi_tcxo"},
|
||||
{ .hw = &gpu_cc_pll0.clkr.hw },
|
||||
{ .hw = &crc_div_pll0.hw },
|
||||
{ .hw = &gpu_cc_pll1.clkr.hw },
|
||||
{ .hw = &crc_div_pll1.hw },
|
||||
{ .fw_name = "gpll0"},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
|
||||
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
|
||||
.cmd_rcgr = 0x1120,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
|
||||
.enable_safe_config = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gmu_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.vdd_data = {
|
||||
.vdd_class = &vdd_cx,
|
||||
.num_rate_max = VDD_NUM,
|
||||
.rate_max = (unsigned long[VDD_NUM]) {
|
||||
[VDD_LOWER] = 200000000},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
|
||||
F(290000000, P_CRC_DIV_PLL1_OUT_AUX2, 1, 0, 0),
|
||||
F(350000000, P_CRC_DIV_PLL1_OUT_AUX2, 1, 0, 0),
|
||||
F(435000000, P_CRC_DIV_PLL1_OUT_AUX2, 1, 0, 0),
|
||||
F(500000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0),
|
||||
F(550000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0),
|
||||
F(650000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0),
|
||||
F(700000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0),
|
||||
F(745000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0),
|
||||
F(845000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0),
|
||||
F(895000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
|
||||
.cmd_rcgr = 0x101c,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
|
||||
.flags = FORCE_ENABLE_RCG,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_gfx3d_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.vdd_data = {
|
||||
.vdd_class = &vdd_cx,
|
||||
.num_rate_max = VDD_NUM,
|
||||
.rate_max = (unsigned long[VDD_NUM]) {
|
||||
[VDD_LOWER] = 290000000,
|
||||
[VDD_LOW] = 435000000,
|
||||
[VDD_LOW_L1] = 550000000,
|
||||
[VDD_NOMINAL] = 700000000,
|
||||
[VDD_NOMINAL_L1] = 745000000,
|
||||
[VDD_HIGH] = 845000000,
|
||||
[VDD_HIGH_L1] = 895000000},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_ahb_clk = {
|
||||
.halt_reg = 0x1078,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1078,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_ahb_clk",
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_crc_ahb_clk = {
|
||||
.halt_reg = 0x107c,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x107c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_crc_ahb_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_gfx3d_clk = {
|
||||
.halt_reg = 0x10a4,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x10a4,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cx_gfx3d_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_gfx3d_slv_clk = {
|
||||
.halt_reg = 0x10a8,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x10a8,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cx_gfx3d_slv_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_gmu_clk = {
|
||||
.halt_reg = 0x1098,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1098,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cx_gmu_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gpu_cc_gmu_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
|
||||
.halt_reg = 0x108c,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x108c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cx_snoc_dvm_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cxo_aon_clk = {
|
||||
.halt_reg = 0x1004,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1004,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cxo_aon_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cxo_clk = {
|
||||
.halt_reg = 0x109c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x109c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cxo_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_gfx3d_clk = {
|
||||
.halt_reg = 0x1054,
|
||||
.halt_check = BRANCH_HALT_SKIP,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1054,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_gfx3d_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_gmu_clk = {
|
||||
.halt_reg = 0x1064,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1064,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_gmu_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gpu_cc_gmu_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
|
||||
.halt_reg = 0x5000,
|
||||
.halt_check = BRANCH_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x5000,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_sleep_clk = {
|
||||
.halt_reg = 0x1090,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1090,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_sleep_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
struct clk_hw *gpu_cc_sm6150_hws[] = {
|
||||
[CRC_DIV_PLL0] = &crc_div_pll0.hw,
|
||||
[CRC_DIV_PLL1] = &crc_div_pll1.hw,
|
||||
};
|
||||
|
||||
static struct clk_regmap *gpu_cc_sm6150_clocks[] = {
|
||||
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
|
||||
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
|
||||
[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
|
||||
[GPU_CC_CX_GFX3D_SLV_CLK] = &gpu_cc_cx_gfx3d_slv_clk.clkr,
|
||||
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
|
||||
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
|
||||
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
|
||||
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
|
||||
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
|
||||
[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
|
||||
[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
|
||||
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
|
||||
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
|
||||
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
|
||||
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
|
||||
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
|
||||
};
|
||||
|
||||
static const struct regmap_config gpu_cc_sm6150_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x7008,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc gpu_cc_sm6150_desc = {
|
||||
.config = &gpu_cc_sm6150_regmap_config,
|
||||
.clks = gpu_cc_sm6150_clocks,
|
||||
.num_clks = ARRAY_SIZE(gpu_cc_sm6150_clocks),
|
||||
.clk_hws = gpu_cc_sm6150_hws,
|
||||
.num_clk_hws = ARRAY_SIZE(gpu_cc_sm6150_hws),
|
||||
|
||||
};
|
||||
|
||||
static const struct of_device_id gpu_cc_sm6150_match_table[] = {
|
||||
{ .compatible = "qcom,sm6150-gpucc" },
|
||||
{ .compatible = "qcom,sa6155-gpucc" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, gpu_cc_sm6150_match_table);
|
||||
|
||||
static void configure_crc(struct regmap *regmap)
|
||||
{
|
||||
unsigned int value, mask;
|
||||
|
||||
/* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */
|
||||
mask = 0xf << 8;
|
||||
mask |= 0xf << 4;
|
||||
value = 0xf << 8 | 0xf << 4;
|
||||
regmap_update_bits(regmap, gpu_cc_cx_gmu_clk.clkr.enable_reg,
|
||||
mask, value);
|
||||
|
||||
/*
|
||||
* After POR, Clock Ramp Controller(CRC) will be in bypass mode.
|
||||
* Software needs to do the following operation to enable the CRC
|
||||
* for GFX3D clock and divide the input clock by div by 2.
|
||||
*/
|
||||
regmap_update_bits(regmap, 0x1028, 0x00015011, 0x00015011);
|
||||
regmap_update_bits(regmap, 0x1024, 0x00800000, 0x00800000);
|
||||
}
|
||||
|
||||
static void gpucc_sm6150_fixup_sa6155(struct platform_device *pdev)
|
||||
{
|
||||
vdd_cx.num_levels = VDD_NUM_SA6155;
|
||||
vdd_cx.cur_level = VDD_NUM_SA6155;
|
||||
vdd_mx.num_levels = VDD_NUM_SA6155;
|
||||
vdd_mx.cur_level = VDD_NUM_SA6155;
|
||||
gpu_cc_gx_gfx3d_clk_src.clkr.vdd_data.rate_max[VDD_HIGH_L1] = 0;
|
||||
|
||||
gpu_cc_pll0.clkr.hw.init = &gpu_cc_pll0_sa6155;
|
||||
gpu_cc_pll1.clkr.hw.init = &gpu_cc_pll1_sa6155;
|
||||
}
|
||||
|
||||
static int gpu_cc_sm6150_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int ret, is_sa6155;
|
||||
|
||||
/* Get CX voltage regulator for CX and GMU clocks. */
|
||||
vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx");
|
||||
if (IS_ERR(vdd_cx.regulator[0])) {
|
||||
if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER))
|
||||
dev_err(&pdev->dev,
|
||||
"Unable to get vdd_cx regulator\n");
|
||||
return PTR_ERR(vdd_cx.regulator[0]);
|
||||
}
|
||||
|
||||
/* Get MX voltage regulator for GPU PLL graphic clock. */
|
||||
vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx");
|
||||
if (IS_ERR(vdd_mx.regulator[0])) {
|
||||
if (!(PTR_ERR(vdd_mx.regulator[0]) == -EPROBE_DEFER))
|
||||
dev_err(&pdev->dev,
|
||||
"Unable to get vdd_mx regulator\n");
|
||||
return PTR_ERR(vdd_mx.regulator[0]);
|
||||
}
|
||||
|
||||
is_sa6155 = of_device_is_compatible(pdev->dev.of_node,
|
||||
"qcom,sa6155-gpucc");
|
||||
if (is_sa6155)
|
||||
gpucc_sm6150_fixup_sa6155(pdev);
|
||||
|
||||
regmap = qcom_cc_map(pdev, &gpu_cc_sm6150_desc);
|
||||
if (IS_ERR(regmap)) {
|
||||
pr_err("Failed to map the gpu_cc registers\n");
|
||||
return PTR_ERR(regmap);
|
||||
}
|
||||
|
||||
clk_alpha_pll_configure(&gpu_cc_pll0, regmap, gpu_cc_pll0.config);
|
||||
clk_alpha_pll_configure(&gpu_cc_pll1, regmap, gpu_cc_pll1.config);
|
||||
|
||||
ret = qcom_cc_really_probe(pdev, &gpu_cc_sm6150_desc, regmap);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to register GPU CC clocks\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
configure_crc(regmap);
|
||||
|
||||
dev_info(&pdev->dev, "Registered GPU CC clocks\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct platform_driver gpu_cc_sm6150_driver = {
|
||||
.probe = gpu_cc_sm6150_probe,
|
||||
.driver = {
|
||||
.name = "gpu_cc-sm6150",
|
||||
.of_match_table = gpu_cc_sm6150_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init gpu_cc_sm6150_init(void)
|
||||
{
|
||||
return platform_driver_register(&gpu_cc_sm6150_driver);
|
||||
}
|
||||
subsys_initcall(gpu_cc_sm6150_init);
|
||||
|
||||
static void __exit gpu_cc_sm6150_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&gpu_cc_sm6150_driver);
|
||||
}
|
||||
module_exit(gpu_cc_sm6150_exit);
|
||||
|
||||
MODULE_DESCRIPTION("QTI GPU_CC SM6150 Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in a new issue