From 96101caa9db8860ca1dca774caf2c63ca78f9e3a Mon Sep 17 00:00:00 2001
From: Veera Vegivada <vvegivad@qti.qualcomm.com>
Date: Tue, 1 Dec 2020 12:01:36 +0530
Subject: [PATCH] ARM: dts: msm: Add RSC and cmd_db support for SDMSHRIKE

Add apps_rsc, disp_rsc and cmd_db support.

Change-Id: I301d33796caba4fe8ffd322389abef556dc8479f
---
 qcom/sdmshrike.dtsi | 33 ++++++++++++++++++++++++++-------
 1 file changed, 26 insertions(+), 7 deletions(-)

diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi
index c1079ca2028a..c97dd9653df4 100644
--- a/qcom/sdmshrike.dtsi
+++ b/qcom/sdmshrike.dtsi
@@ -314,6 +314,12 @@
 			reg = <0x0 0x85ffd000 0x0 0x3000>;
 		};
 
+		aop_cmd_db: memory@85f20000 {
+			compatible = "qcom,cmd-db";
+			reg = <0x0 0x85f20000 0x0 0x20000>;
+			no-map;
+		};
+
 		smem_region: smem@86000000 {
 			no-map;
 			reg = <0x0 0x86000000 0x0 0x200000>;
@@ -620,19 +626,32 @@
 		label = "apps_rsc";
 		compatible = "qcom,rpmh-rsc";
 		reg = <0x18200000 0x10000>,
-			<0x18210000 0x10000>,
-			<0x18220000 0x10000>;
+		      <0x18210000 0x10000>,
+		      <0x18220000 0x10000>;
 		reg-names = "drv-0", "drv-1", "drv-2";
 		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 		qcom,tcs-offset = <0xd00>;
 		qcom,drv-id = <2>;
 		qcom,tcs-config = <ACTIVE_TCS  2>,
-				<SLEEP_TCS   1>,
-				<WAKE_TCS    1>,
-				<CONTROL_TCS 0>;
+				  <SLEEP_TCS   3>,
+				  <WAKE_TCS    3>,
+				  <CONTROL_TCS 1>;
+	};
 
+	disp_rsc: rsc@af20000 {
+		label = "disp_rsc";
+		compatible = "qcom,rpmh-rsc";
+		reg = <0xaf20000 0x10000>;
+		reg-names = "drv-0";
+		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,tcs-offset = <0x1c00>;
+		qcom,drv-id = <0>;
+		qcom,tcs-config = <SLEEP_TCS   1>,
+				  <WAKE_TCS    1>,
+				  <ACTIVE_TCS  2>,
+				  <CONTROL_TCS 0>;
 	};
 
 	qupv3_id_1: geniqup@ac0000 {