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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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Samsung S5PV210 DT support for v3.17
- support common clock framework for s5pv210 clock - add generic PHY driver on s5pv210 to support it via DT - add dt support for s5pv210-goni, smdkc110, smdkv210 and torbreck boards - remove board files from mach-s5pv210 and unused codes - enable multiplatform for s5pv210 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJT0ZTrAAoJEA0Cl+kVi2xqaAgP/RZjKZizSPCTTM71wQv4QWjU TR3SJMgejnePLzHU6h22P11PBV1KOCec9nko+7M+vQeSCJscoJsudmSiKRceh0tC 9ATq5eSIw/p3WVjRSFOsj95O1urKdFQPzQ/odwwtw4WRnFerZoY9ihRBKnZxRCJc oQdFTDTJeBVlPUxLV1/slS+HWP+I/csYXnAF1Y2tz0GxEX+7iQ6LS7YuCB3kGiG1 S4mcNyfyhUjpxO4oL0QazCEpsX7UgyNm9MMaW7jGxjc7J7GraiVnFdo3C8yZIeS/ zAkA6YnOBoFqwCwgJsvo8VBsfqUtMC49GVJYSFiVNe3s9W6awuLfr8GhhHLX7q6t dGib2p0DtYbVNGRUHW1PWkwBefdFEGkYmNugcS9/WiqTL2oUr3L11LaAEbzVC2pq cBnT7+8lyEoaBmpeMDpmXUti4fyQH4uNxMjoRT4qDI1d/U20+d5pZFZzuQbuZ5xX UZnk4vs6YRZAqYgkPh9Wg5A56J+ku21oHBlnbjIxBgrjA9UjP4foCk3rA8iZT1JD eH7r033zcOZ1LUOZWO53O4/l5pE8cfU6FweEb9h6ADfrMB8vKTAeDbwipI4n+l0v /VxlIV+cRCEuWPCNuYJkOLpqj7L36MFkbkppJy8wyPPPu1UUrpAWpq/Pw60uEW7M hkVo/JtpTjqzUEEb7mC1 =7b91 -----END PGP SIGNATURE----- Merge tag 's5pv210-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc Merge "Samsung S5PV210 DT support for v3.17" from Kukjin Kim: - support common clock framework for s5pv210 clock - add generic PHY driver on s5pv210 to support it via DT - add dt support for s5pv210-goni, smdkc110, smdkv210 and torbreck boards - remove board files from mach-s5pv210 and unused codes - enable multiplatform for s5pv210 * tag 's5pv210-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: clk: samsung: s5pv210: Remove legacy board support ARM: SAMSUNG: Remove remaining legacy code gpio: samsung: Remove legacy support of S5PV210 ARM: S5PV210: Enable multi-platform build support cpufreq: s5pv210: Make the driver multiplatform aware ARM: S5PV210: Register cpufreq platform device ARM: S5PV210: move debug-macro.S into the common space ARM: S5PV210: Untie PM support from legacy code ARM: S5PV210: Remove support for board files ARM: dts: Add Device tree for s5pc110/s5pv210 boards ARM: dts: Add Device tree for s5pv210 SoC ARM: S5PV210: Add board file for boot using Device Tree phy: Add support for S5PV210 to the Exynos USB 2.0 PHY driver clk: samsung: Add S5PV210 Audio Subsystem clock driver ARM: SAMSUNG: Remove legacy clock code serial: samsung: Remove support for legacy clock code cpufreq: s3c24xx: Remove some dead code ARM: S5PV210: Migrate clock handling to Common Clock Framework clk: samsung: Add clock driver for S5PV210 and compatible SoCs Signed-off-by: Arnd Bergmann <[email protected]>
This commit is contained in:
Arnd Bergmann
commit
96bda115ec
123 changed files with 4786 additions and 9352 deletions
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@ -1169,234 +1169,9 @@ static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
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#endif
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};
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/*
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* Followings are the gpio banks in S5PV210/S5PC110
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*
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* The 'config' member when left to NULL, is initialized to the default
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* structure samsung_gpio_cfgs[3] in the init function below.
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*
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* The 'base' member is also initialized in the init function below.
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* Note: The initialization of 'base' member of samsung_gpio_chip structure
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* uses the above macro and depends on the banks being listed in order here.
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*/
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static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
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#ifdef CONFIG_CPU_S5PV210
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{
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.chip = {
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.base = S5PV210_GPA0(0),
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.ngpio = S5PV210_GPIO_A0_NR,
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.label = "GPA0",
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},
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}, {
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.chip = {
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.base = S5PV210_GPA1(0),
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.ngpio = S5PV210_GPIO_A1_NR,
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.label = "GPA1",
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},
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}, {
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.chip = {
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.base = S5PV210_GPB(0),
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.ngpio = S5PV210_GPIO_B_NR,
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.label = "GPB",
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},
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}, {
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.chip = {
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.base = S5PV210_GPC0(0),
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.ngpio = S5PV210_GPIO_C0_NR,
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.label = "GPC0",
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},
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}, {
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.chip = {
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.base = S5PV210_GPC1(0),
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.ngpio = S5PV210_GPIO_C1_NR,
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.label = "GPC1",
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},
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}, {
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.chip = {
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.base = S5PV210_GPD0(0),
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.ngpio = S5PV210_GPIO_D0_NR,
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.label = "GPD0",
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},
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}, {
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.chip = {
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.base = S5PV210_GPD1(0),
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.ngpio = S5PV210_GPIO_D1_NR,
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.label = "GPD1",
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},
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}, {
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.chip = {
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.base = S5PV210_GPE0(0),
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.ngpio = S5PV210_GPIO_E0_NR,
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.label = "GPE0",
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},
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}, {
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.chip = {
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.base = S5PV210_GPE1(0),
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.ngpio = S5PV210_GPIO_E1_NR,
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.label = "GPE1",
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},
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}, {
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.chip = {
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.base = S5PV210_GPF0(0),
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.ngpio = S5PV210_GPIO_F0_NR,
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.label = "GPF0",
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},
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}, {
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.chip = {
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.base = S5PV210_GPF1(0),
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.ngpio = S5PV210_GPIO_F1_NR,
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.label = "GPF1",
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},
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}, {
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.chip = {
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.base = S5PV210_GPF2(0),
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.ngpio = S5PV210_GPIO_F2_NR,
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.label = "GPF2",
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},
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}, {
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.chip = {
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.base = S5PV210_GPF3(0),
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.ngpio = S5PV210_GPIO_F3_NR,
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.label = "GPF3",
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},
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}, {
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.chip = {
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.base = S5PV210_GPG0(0),
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.ngpio = S5PV210_GPIO_G0_NR,
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.label = "GPG0",
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},
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}, {
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.chip = {
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.base = S5PV210_GPG1(0),
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.ngpio = S5PV210_GPIO_G1_NR,
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.label = "GPG1",
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},
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}, {
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.chip = {
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.base = S5PV210_GPG2(0),
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.ngpio = S5PV210_GPIO_G2_NR,
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.label = "GPG2",
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},
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}, {
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.chip = {
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.base = S5PV210_GPG3(0),
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.ngpio = S5PV210_GPIO_G3_NR,
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.label = "GPG3",
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},
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}, {
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.chip = {
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.base = S5PV210_GPI(0),
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.ngpio = S5PV210_GPIO_I_NR,
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.label = "GPI",
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},
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}, {
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.chip = {
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.base = S5PV210_GPJ0(0),
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.ngpio = S5PV210_GPIO_J0_NR,
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.label = "GPJ0",
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},
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}, {
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.chip = {
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.base = S5PV210_GPJ1(0),
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.ngpio = S5PV210_GPIO_J1_NR,
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.label = "GPJ1",
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},
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}, {
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.chip = {
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.base = S5PV210_GPJ2(0),
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.ngpio = S5PV210_GPIO_J2_NR,
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.label = "GPJ2",
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},
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}, {
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.chip = {
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.base = S5PV210_GPJ3(0),
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.ngpio = S5PV210_GPIO_J3_NR,
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.label = "GPJ3",
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},
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}, {
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.chip = {
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.base = S5PV210_GPJ4(0),
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.ngpio = S5PV210_GPIO_J4_NR,
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.label = "GPJ4",
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},
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}, {
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.chip = {
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.base = S5PV210_MP01(0),
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.ngpio = S5PV210_GPIO_MP01_NR,
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.label = "MP01",
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},
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}, {
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.chip = {
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.base = S5PV210_MP02(0),
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.ngpio = S5PV210_GPIO_MP02_NR,
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.label = "MP02",
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},
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}, {
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.chip = {
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.base = S5PV210_MP03(0),
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.ngpio = S5PV210_GPIO_MP03_NR,
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.label = "MP03",
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},
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}, {
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.chip = {
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.base = S5PV210_MP04(0),
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.ngpio = S5PV210_GPIO_MP04_NR,
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.label = "MP04",
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},
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}, {
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.chip = {
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.base = S5PV210_MP05(0),
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.ngpio = S5PV210_GPIO_MP05_NR,
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.label = "MP05",
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},
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}, {
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.base = (S5P_VA_GPIO + 0xC00),
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.irq_base = IRQ_EINT(0),
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.chip = {
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.base = S5PV210_GPH0(0),
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.ngpio = S5PV210_GPIO_H0_NR,
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.label = "GPH0",
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.to_irq = samsung_gpiolib_to_irq,
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},
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}, {
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.base = (S5P_VA_GPIO + 0xC20),
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.irq_base = IRQ_EINT(8),
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.chip = {
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.base = S5PV210_GPH1(0),
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.ngpio = S5PV210_GPIO_H1_NR,
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.label = "GPH1",
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.to_irq = samsung_gpiolib_to_irq,
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},
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}, {
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.base = (S5P_VA_GPIO + 0xC40),
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.irq_base = IRQ_EINT(16),
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.chip = {
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.base = S5PV210_GPH2(0),
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.ngpio = S5PV210_GPIO_H2_NR,
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.label = "GPH2",
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.to_irq = samsung_gpiolib_to_irq,
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},
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}, {
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.base = (S5P_VA_GPIO + 0xC60),
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.irq_base = IRQ_EINT(24),
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.chip = {
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.base = S5PV210_GPH3(0),
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.ngpio = S5PV210_GPIO_H3_NR,
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.label = "GPH3",
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.to_irq = samsung_gpiolib_to_irq,
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},
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},
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#endif
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};
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/* TODO: cleanup soc_is_* */
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static __init int samsung_gpiolib_init(void)
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{
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struct samsung_gpio_chip *chip;
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int i, nr_chips;
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int group = 0;
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/*
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* Currently there are two drivers that can provide GPIO support for
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* Samsung SoCs. For device tree enabled platforms, the new
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@ -1420,21 +1195,6 @@ static __init int samsung_gpiolib_init(void)
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S3C64XX_VA_GPIO);
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samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
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ARRAY_SIZE(s3c64xx_gpios_4bit2));
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} else if (soc_is_s5pv210()) {
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group = 0;
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chip = s5pv210_gpios_4bit;
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nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);
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for (i = 0; i < nr_chips; i++, chip++) {
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if (!chip->config) {
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chip->config = &samsung_gpio_cfgs[3];
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chip->group = group++;
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}
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}
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samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);
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#if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
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s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
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#endif
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} else {
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WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
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return -ENODEV;
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