From c2bdf83c4f9aedc8903009691e92ad3f4cd1b988 Mon Sep 17 00:00:00 2001 From: David Dai Date: Tue, 12 Nov 2019 13:27:33 -0800 Subject: [PATCH 1/2] ARM: dts: msm: Add regmap and clocks for interconnects on Lahaina Add regmaps for MMIO registers for QoS configurations and required clocks to access certain QoS registers. Change-Id: I28814e6a7b8808500005f3f785e7ee8a491189de --- qcom/lahaina.dtsi | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 6b8aef464f33..15a10649ce7d 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -1060,14 +1060,21 @@ aggre1_noc: interconnect@16e0000 { compatible = "qcom,lahaina-aggre1_noc"; + reg = <0x016E0000 0x1f180>; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&clock_gcc GCC_AGGRE_USB3_SEC_AXI_CLK>; }; aggre2_noc: interconnect@1700000 { + reg = <0x1700000 0x3d180>; compatible = "qcom,lahaina-aggre2_noc"; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&clock_gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&clock_gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; }; clk_virt: interconnect { @@ -1077,24 +1084,28 @@ }; config_noc: interconnect@1500000 { + reg = <0x1500000 0x28000>; compatible = "qcom,lahaina-config_noc"; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; }; dc_noc: interconnect@14e0000 { + reg = <0x90C0000 0x4200>; compatible = "qcom,lahaina-dc_noc"; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; }; gem_noc: interconnect@1380000 { + reg = <0x9100000 0xae200>; compatible = "qcom,lahaina-gem_noc"; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; }; - lpass_ag_noc: interconnect@1480000 { + lpass_ag_noc: interconnect@3c40000 { + reg = <0x03c40000 0xf080>; compatible = "qcom,lahaina-lpass_ag_noc"; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -1107,18 +1118,21 @@ }; mmss_noc: interconnect@1740000 { + reg = <0x1740000 0x1f080>; compatible = "qcom,lahaina-mmss_noc"; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; }; - nsp_noc: interconnect@1750000 { + nsp_noc: interconnect@a0c0000 { + reg = <0x0a0c0000 0x10000>; compatible = "qcom,lahaina-nsp_noc"; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; }; - system_noc: interconnect@1620000 { + system_noc: interconnect@1680000 { + reg = <0x1680000 0x1EE00>; compatible = "qcom,lahaina-system_noc"; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; From 2604230bfa24b7ff17aec36dab6e7370a0b986ed Mon Sep 17 00:00:00 2001 From: David Dai Date: Mon, 20 Jan 2020 16:53:55 -0800 Subject: [PATCH 2/2] ARM: dts: msm: Add and enable disp rsc support for Lahaina Add interconnect bcm voter devices for display specific RSC and phandles for interconnect NoC devies to target display RSC. Change-Id: I72b310ab0cc7a3f673452e6b333f5a428eb80f4b --- qcom/lahaina.dtsi | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 15a10649ce7d..119461c2fc57 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -1062,6 +1062,7 @@ compatible = "qcom,lahaina-aggre1_noc"; reg = <0x016E0000 0x1f180>; #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; clocks = <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, @@ -1072,6 +1073,7 @@ reg = <0x1700000 0x3d180>; compatible = "qcom,lahaina-aggre2_noc"; #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; clocks = <&clock_gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, <&clock_gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; @@ -1080,6 +1082,7 @@ clk_virt: interconnect { compatible = "qcom,lahaina-clk_virt"; #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -1087,6 +1090,7 @@ reg = <0x1500000 0x28000>; compatible = "qcom,lahaina-config_noc"; #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -1094,6 +1098,7 @@ reg = <0x90C0000 0x4200>; compatible = "qcom,lahaina-dc_noc"; #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -1101,33 +1106,39 @@ reg = <0x9100000 0xae200>; compatible = "qcom,lahaina-gem_noc"; #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; }; lpass_ag_noc: interconnect@3c40000 { reg = <0x03c40000 0xf080>; compatible = "qcom,lahaina-lpass_ag_noc"; #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; }; mc_virt: interconnect@1580000 { + reg = <0x1580000 0x4>; compatible = "qcom,lahaina-mc_virt"; #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; }; mmss_noc: interconnect@1740000 { reg = <0x1740000 0x1f080>; compatible = "qcom,lahaina-mmss_noc"; #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; }; nsp_noc: interconnect@a0c0000 { reg = <0x0a0c0000 0x10000>; compatible = "qcom,lahaina-nsp_noc"; #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -1135,6 +1146,7 @@ reg = <0x1680000 0x1EE00>; compatible = "qcom,lahaina-system_noc"; #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -1482,7 +1494,6 @@ }; disp_rsc: rsc@af20000 { - status = "disabled"; label = "disp_rsc"; compatible = "qcom,rpmh-rsc"; reg = <0xaf20000 0x10000>; @@ -1494,6 +1505,11 @@ , , ; + + disp_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; + }; spmi_bus: qcom,spmi@c440000 {