mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 10:41:38 -04:00
MTD updates for 4.12-rc1:
NAND, from Boris:
"""
- some minor fixes/improvements on existing drivers (fsmc, gpio, ifc,
davinci, brcmnand, omap)
- a huge cleanup/rework of the denali driver accompanied with core
fixes/improvements to simplify the driver code
- a complete rewrite of the atmel driver to support new DT bindings
make future evolution easier
- the addition of per-vendor detection/initialization steps to avoid
extending the nand_ids table with more extended-id entries
"""
SPI NOR, from Cyrille:
"""
- fixes in the hisi SPI controller driver.
- fixes in the intel SPI controller driver.
- fixes in the Mediatek SPI controller driver.
- fixes to some SPI flash memories not supported the Chip Erase command.
- add support to some new memory parts (Winbond, Macronix, Micron, ESMT).
- add new driver for the STM32 QSPI controller.
"""
And a few fixes for Gemini and Versatile platforms on physmap-of
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Merge tag 'for-linus-20170510' of git://git.infradead.org/linux-mtd
Pull MTD updates from Brian Norris:
"NAND, from Boris:
- some minor fixes/improvements on existing drivers (fsmc, gpio, ifc,
davinci, brcmnand, omap)
- a huge cleanup/rework of the denali driver accompanied with core
fixes/improvements to simplify the driver code
- a complete rewrite of the atmel driver to support new DT bindings
make future evolution easier
- the addition of per-vendor detection/initialization steps to avoid
extending the nand_ids table with more extended-id entries
SPI NOR, from Cyrille:
- fixes in the hisi, intel and Mediatek SPI controller drivers
- fixes to some SPI flash memories not supporting the Chip Erase
command.
- add support to some new memory parts (Winbond, Macronix, Micron,
ESMT).
- add new driver for the STM32 QSPI controller
And a few fixes for Gemini and Versatile platforms on physmap-of"
* tag 'for-linus-20170510' of git://git.infradead.org/linux-mtd: (100 commits)
MAINTAINERS: Update NAND subsystem git repositories
mtd: nand: gpio: update binding
mtd: nand: add ooblayout for old hamming layout
mtd: oxnas_nand: Allocating more than necessary in probe()
dt-bindings: mtd: Document the STM32 QSPI bindings
mtd: mtk-nor: set controller's address width according to nor flash
mtd: spi-nor: add driver for STM32 quad spi flash controller
mtd: nand: brcmnand: Check flash #WP pin status before nand erase/program
mtd: nand: davinci: add comment on NAND subpage write status on keystone
mtd: nand: omap2: Fix partition creation via cmdline mtdparts
mtd: nand: NULL terminate a of_device_id table
mtd: nand: Fix a couple error codes
mtd: nand: allow drivers to request minimum alignment for passed buffer
mtd: nand: allocate aligned buffers if NAND_OWN_BUFFERS is unset
mtd: nand: denali: allow to override revision number
mtd: nand: denali_dt: use pdev instead of ofdev for platform_device
mtd: nand: denali_dt: remove dma-mask DT property
mtd: nand: denali: support 64bit capable DMA engine
mtd: nand: denali_dt: enable HW_ECC_FIXUP for Altera SOCFPGA variant
mtd: nand: denali: support HW_ECC_FIXUP capability
...
This commit is contained in:
Linus Torvalds
commit
9786e34e0a
53 changed files with 6173 additions and 3834 deletions
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@ -1,4 +1,109 @@
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Atmel NAND flash
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Atmel NAND flash controller bindings
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The NAND flash controller node should be defined under the EBI bus (see
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Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
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One or several NAND devices can be defined under this NAND controller.
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The NAND controller might be connected to an ECC engine.
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* NAND controller bindings:
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Required properties:
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- compatible: should be one of the following
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"atmel,at91rm9200-nand-controller"
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"atmel,at91sam9260-nand-controller"
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"atmel,at91sam9261-nand-controller"
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"atmel,at91sam9g45-nand-controller"
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"atmel,sama5d3-nand-controller"
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- ranges: empty ranges property to forward EBI ranges definitions.
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- #address-cells: should be set to 2.
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- #size-cells: should be set to 1.
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- atmel,nfc-io: phandle to the NFC IO block. Only required for sama5d3
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controllers.
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- atmel,nfc-sram: phandle to the NFC SRAM block. Only required for sama5d3
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controllers.
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Optional properties:
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- ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds
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a PMECC engine.
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* NAND device/chip bindings:
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Required properties:
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- reg: describes the CS lines assigned to the NAND device. If the NAND device
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exposes multiple CS lines (multi-dies chips), your reg property will
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contain X tuples of 3 entries.
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1st entry: the CS line this NAND chip is connected to
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2nd entry: the base offset of the memory region assigned to this
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device (always 0)
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3rd entry: the memory region size (always 0x800000)
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Optional properties:
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- rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND.
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- cs-gpios: the GPIO(s) used to control the CS line.
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- det-gpios: the GPIO used to detect if a Smartmedia Card is present.
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- atmel,rb: an integer identifying the native Ready/Busy pin. Only meaningful
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on sama5 SoCs.
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All generic properties described in
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Documentation/devicetree/bindings/mtd/{common,nand}.txt also apply to the NAND
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device node, and NAND partitions should be defined under the NAND node as
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described in Documentation/devicetree/bindings/mtd/partition.txt.
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* ECC engine (PMECC) bindings:
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Required properties:
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- compatible: should be one of the following
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"atmel,at91sam9g45-pmecc"
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"atmel,sama5d4-pmecc"
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"atmel,sama5d2-pmecc"
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- reg: should contain 2 register ranges. The first one is pointing to the PMECC
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block, and the second one to the PMECC_ERRLOC block.
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Example:
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pmecc: ecc-engine@ffffc070 {
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compatible = "atmel,at91sam9g45-pmecc";
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reg = <0xffffc070 0x490>,
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<0xffffc500 0x100>;
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};
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ebi: ebi@10000000 {
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compatible = "atmel,sama5d3-ebi";
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#address-cells = <2>;
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#size-cells = <1>;
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atmel,smc = <&hsmc>;
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reg = <0x10000000 0x10000000
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0x40000000 0x30000000>;
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ranges = <0x0 0x0 0x10000000 0x10000000
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0x1 0x0 0x40000000 0x10000000
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0x2 0x0 0x50000000 0x10000000
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0x3 0x0 0x60000000 0x10000000>;
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clocks = <&mck>;
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nand_controller: nand-controller {
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compatible = "atmel,sama5d3-nand-controller";
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atmel,nfc-sram = <&nfc_sram>;
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atmel,nfc-io = <&nfc_io>;
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ecc-engine = <&pmecc>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges;
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nand@3 {
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reg = <0x3 0x0 0x800000>;
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atmel,rb = <0>;
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/*
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* Put generic NAND/MTD properties and
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* subnodes here.
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*/
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};
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};
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};
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-----------------------------------------------------------------------
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Deprecated bindings (should not be used in new device trees):
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Required properties:
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- compatible: The possible values are:
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@ -1,11 +1,11 @@
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* Denali NAND controller
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Required properties:
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- compatible : should be "denali,denali-nand-dt"
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- compatible : should be one of the following:
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"altr,socfpga-denali-nand" - for Altera SOCFPGA
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- reg : should contain registers location and length for data and reg.
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- reg-names: Should contain the reg names "nand_data" and "denali_reg"
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- interrupts : The interrupt number.
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- dm-mask : DMA bit mask
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The device tree may optionally contain sub-nodes describing partitions of the
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address space. See partition.txt for more detail.
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@ -15,9 +15,8 @@ Examples:
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nand: nand@ff900000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "denali,denali-nand-dt";
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compatible = "altr,socfpga-denali-nand";
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reg = <0xff900000 0x100000>, <0xffb80000 0x10000>;
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reg-names = "nand_data", "denali_reg";
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interrupts = <0 144 4>;
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dma-mask = <0xffffffff>;
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};
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@ -12,7 +12,7 @@ Required properties:
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- #address-cells, #size-cells : Must be present if the device has sub-nodes
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representing partitions.
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- gpios : Specifies the GPIO pins to control the NAND device. The order of
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GPIO references is: RDY, nCE, ALE, CLE, and an optional nWP.
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GPIO references is: RDY, nCE, ALE, CLE, and nWP. nCE and nWP are optional.
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Optional properties:
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- bank-width : Width (in bytes) of the device. If not present, the width
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@ -36,7 +36,7 @@ gpio-nand@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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gpios = <&banka 1 0>, /* RDY */
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<&banka 2 0>, /* nCE */
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<0>, /* nCE */
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<&banka 3 0>, /* ALE */
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<&banka 4 0>, /* CLE */
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<0>; /* nWP */
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43
Documentation/devicetree/bindings/mtd/stm32-quadspi.txt
Normal file
43
Documentation/devicetree/bindings/mtd/stm32-quadspi.txt
Normal file
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@ -0,0 +1,43 @@
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* STMicroelectronics Quad Serial Peripheral Interface(QuadSPI)
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Required properties:
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- compatible: should be "st,stm32f469-qspi"
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- reg: the first contains the register location and length.
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the second contains the memory mapping address and length
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- reg-names: should contain the reg names "qspi" "qspi_mm"
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- interrupts: should contain the interrupt for the device
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- clocks: the phandle of the clock needed by the QSPI controller
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- A pinctrl must be defined to set pins in mode of operation for QSPI transfer
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Optional properties:
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- resets: must contain the phandle to the reset controller.
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A spi flash must be a child of the nor_flash node and could have some
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properties. Also see jedec,spi-nor.txt.
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Required properties:
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- reg: chip-Select number (QSPI controller may connect 2 nor flashes)
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- spi-max-frequency: max frequency of spi bus
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Optional property:
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- spi-rx-bus-width: see ../spi/spi-bus.txt for the description
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Example:
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qspi: spi@a0001000 {
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compatible = "st,stm32f469-qspi";
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reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;
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reg-names = "qspi", "qspi_mm";
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interrupts = <91>;
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resets = <&rcc STM32F4_AHB3_RESET(QSPI)>;
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clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi0>;
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flash@0 {
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reg = <0>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <108000000>;
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...
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};
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};
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