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Merge "msm: kgsl: Get resource address from cmd-db driver"

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This commit is contained in:
qctecmdr 2020-04-20 08:54:30 -07:00 • committed by Gerrit - the friendly Code Review server
commit 9795c1b6f1
1 changed files with 17 additions and 4 deletions
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21
drivers/gpu/msm/adreno_a6xx_gmu.c
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@ -121,6 +121,8 @@ static int a6xx_load_pdc_ucode(struct kgsl_device *device)
const struct adreno_a6xx_core *a6xx_core = to_a6xx_core(adreno_dev);
u32 vrm_resource_addr = cmd_db_read_addr("vrm.soc");
u32 xo_resource_addr = cmd_db_read_addr("xo.lvl");
u32 cx_res_addr = cmd_db_read_addr("cx.lvl");
u32 mx_res_addr = cmd_db_read_addr("mx.lvl");
if (!xo_resource_addr) {
dev_err(&gmu->pdev->dev,
@ -128,6 +130,17 @@ static int a6xx_load_pdc_ucode(struct kgsl_device *device)
return -ENOENT;
}
if (!cx_res_addr) {
dev_err(&gmu->pdev->dev,
"Failed to get 'cx.lvl' addr from cmd_db\n");
return -ENOENT;
}
if (!mx_res_addr) {
dev_err(&gmu->pdev->dev,
"Failed to get 'mx.lvl' addr from cmd_db\n");
return -ENOENT;
}
/*
* Older A6x platforms specified PDC registers in the DT using a
* single base pointer that encompassed the entire PDC range. Current
@ -205,10 +218,10 @@ static int a6xx_load_pdc_ucode(struct kgsl_device *device)
_regwrite(cfg, PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);
_regwrite(cfg, PDC_GPU_TCS1_CONTROL, 0);
_regwrite(cfg, PDC_GPU_TCS1_CMD0_MSGID, 0x10108);
_regwrite(cfg, PDC_GPU_TCS1_CMD0_ADDR, 0x30010);
_regwrite(cfg, PDC_GPU_TCS1_CMD0_ADDR, mx_res_addr);
_regwrite(cfg, PDC_GPU_TCS1_CMD0_DATA, 1);
_regwrite(cfg, PDC_GPU_TCS1_CMD0_MSGID + PDC_CMD_OFFSET, 0x10108);
_regwrite(cfg, PDC_GPU_TCS1_CMD0_ADDR + PDC_CMD_OFFSET, 0x30000);
_regwrite(cfg, PDC_GPU_TCS1_CMD0_ADDR + PDC_CMD_OFFSET, cx_res_addr);
_regwrite(cfg, PDC_GPU_TCS1_CMD0_DATA + PDC_CMD_OFFSET, 0x0);
_regwrite(cfg, PDC_GPU_TCS1_CMD0_MSGID + PDC_CMD_OFFSET * 2, 0x10108);
@ -230,10 +243,10 @@ static int a6xx_load_pdc_ucode(struct kgsl_device *device)
_regwrite(cfg, PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);
_regwrite(cfg, PDC_GPU_TCS3_CONTROL, 0);
_regwrite(cfg, PDC_GPU_TCS3_CMD0_MSGID, 0x10108);
_regwrite(cfg, PDC_GPU_TCS3_CMD0_ADDR, 0x30010);
_regwrite(cfg, PDC_GPU_TCS3_CMD0_ADDR, mx_res_addr);
_regwrite(cfg, PDC_GPU_TCS3_CMD0_DATA, 2);
_regwrite(cfg, PDC_GPU_TCS3_CMD0_MSGID + PDC_CMD_OFFSET, 0x10108);
_regwrite(cfg, PDC_GPU_TCS3_CMD0_ADDR + PDC_CMD_OFFSET, 0x30000);
_regwrite(cfg, PDC_GPU_TCS3_CMD0_ADDR + PDC_CMD_OFFSET, cx_res_addr);
if (adreno_is_a618(adreno_dev) || adreno_is_a650_family(adreno_dev))
_regwrite(cfg, PDC_GPU_TCS3_CMD0_DATA + PDC_CMD_OFFSET, 0x2);