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ARM: arm-soc platform updates for 3.10, part 1
This branch contains platform updates for 3.10. Among the highlights: - Support for the new Atmel Cortex-A5 based platforms (SAMA5D3) - New support for CSR SiRFatlas6 SoCs - A handful of updates for NVidia T114 (a.k.a. Tegra 4) - A bunch of updates for the shmobile platforms - A handful of updates for davinci - A few updates for Qualcomm MSM - Plus a handful of other patches, defconfig updates, etc. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJRgg+LAAoJEIwa5zzehBx3ePcP/3NUsSOTRQ2SZIVpyjnWOhkf RMZiRaVsxrY0BPfDB9E2Vcb6lannKmACTujs/Ux7kJC22BreuFM1PnZoDfhkRuSE n/nVB1981XJS82z2uONRSZGlUPSGWYzhTTUDJ0nHiBGmIGf5ctnC0iYWp3As3lv9 kNY14H7NkwQ4zBVNEMu7WfW8d2IJgqZJgR9xhZPv5fOZ+LlQmK6VaHWTmQtjyea1 bG1qoJ0dPbfJB4Vnr3a49rBkSJxZUiv8xQucw9+vo+ADRi64M4sZ1Jj2vVyDpqZp F4fxBNMVvg7xM0TcBbItFFYJBXlUjeT4z+UI5iYjkbnE7EV9ndFeZXHCWX1qzOSy X/nrJKuoe7ISQanBE9SHS9DpDGlkPDO0Mn0vb1f2VUQOY513pt/D1iFYEucZ6WCN fWUYtvt5GayidUr55D1U8ssbE0oGt2rizd9x7GUk4KbRVAnUUNopIQAhXrefTrZm jfdZNDckJ2F3aq8IPjsKuyJTpe61xD4Wvb3P/pEE3Q8fowPF5WIxXV+qjqHQ9vtt Tz4LkP/YdynVFGmhOwz3QZmPaQItaabaYyCcZ5cVCvt5mdxx5VuHYppafhCPJz+V KCQpKi1azuIv+sDR+nlGOl6+Ideea3s7TsRudfbmQFp5GsqkqOdJzR9gbbKmJauQ 4JPpRd+4W8wC8zXQnhVY =HXX3 -----END PGP SIGNATURE----- Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Olof Johansson: "This branch contains part 1 of the platform updates for 3.10. Among the highlights: - Support for the new Atmel Cortex-A5 based platforms (SAMA5D3) - New support for CSR SiRFatlas6 SoCs - A handful of updates for NVidia T114 (a.k.a. Tegra 4) - A bunch of updates for the shmobile platforms - A handful of updates for davinci - A few updates for Qualcomm MSM - Plus a handful of other patches, defconfig updates, etc." * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (135 commits) ARM: tegra: pm: fix build error w/o PM_SLEEP ARM: davinci: ensure global variables are declared ARM: davinci: sram.c: fix incorrect type in assignment ARM: davinci: da8xx dt: make file local symbols static ARM: davinci: da8xx: add remoteproc support ARM: socfpga: Upgrade clk driver for socfpga to make use of dts clock entries ARM: socfpga: Add clock entries into device tree ARM: socfpga: Enable soft reset ARM: EXYNOS: replace cpumask by the corresponding macro ARM: EXYNOS: handle properly the return values ARM: EXYNOS: factor out the idle states ARM: OMAP4: Enable fix for Cortex-A9 erratas ARM: OMAP2+: Export SoC information to userspace ARM: OMAP2+: SoC name and revision unification ARM: OMAP2+: Move common part of late init into common function ARM: tegra: pm: remove duplicated include from pm.c ARM: davinci: da850: override mmc DT node device name ARM: davinci: da850: add mmc DT entries mmc: davinci_mmc: add DT support ARM: SAMSUNG: check processor type before cache restoration in resume ...
This commit is contained in:
Linus Torvalds
commit
97b1007a29
164 changed files with 6029 additions and 846 deletions
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Altera SOCFPGA Clock Manager
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Required properties:
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- compatible : "altr,clk-mgr"
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- reg : Should contain base address and length for Clock Manager
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Example:
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clkmgr@ffd04000 {
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compatible = "altr,clk-mgr";
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reg = <0xffd04000 0x1000>;
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};
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19
Documentation/devicetree/bindings/arm/bcm/bcm,kona-timer.txt
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19
Documentation/devicetree/bindings/arm/bcm/bcm,kona-timer.txt
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Broadcom Kona Family timer
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-----------------------------------------------------
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This timer is used in the following Broadcom SoCs:
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BCM11130, BCM11140, BCM11351, BCM28145, BCM28155
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Required properties:
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- compatible : "bcm,kona-timer"
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- reg : Register range for the timer
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- interrupts : interrupt for the timer
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- clock-frequency: frequency that the clock operates
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Example:
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timer@35006000 {
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compatible = "bcm,kona-timer";
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reg = <0x35006000 0x1000>;
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interrupts = <0x0 7 0x4>;
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clock-frequency = <32768>;
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};
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@ -3,36 +3,35 @@
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Properties:
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- compatible : Should at least contain "qcom,msm-timer". More specific
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properties such as "qcom,msm-gpt" and "qcom,msm-dgt" specify a general
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purpose timer and a debug timer respectively.
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properties specify which subsystem the timers are paired with.
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- interrupts : Interrupt indicating a match event.
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"qcom,kpss-timer" - krait subsystem
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"qcom,scss-timer" - scorpion subsystem
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- reg : Specifies the base address of the timer registers. The second region
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specifies an optional register used to configure the clock divider.
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- interrupts : Interrupts for the the debug timer, the first general purpose
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timer, and optionally a second general purpose timer in that
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order.
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- clock-frequency : The frequency of the timer in Hz.
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- reg : Specifies the base address of the timer registers.
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- clock-frequency : The frequency of the debug timer and the general purpose
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timer(s) in Hz in that order.
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Optional:
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- cpu-offset : per-cpu offset used when the timer is accessed without the
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CPU remapping facilities. The offset is cpu-offset * cpu-nr.
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CPU remapping facilities. The offset is
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cpu-offset + (0x10000 * cpu-nr).
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Example:
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timer@200a004 {
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compatible = "qcom,msm-gpt", "qcom,msm-timer";
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interrupts = <1 2 0x301>;
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reg = <0x0200a004 0x10>;
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clock-frequency = <32768>;
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cpu-offset = <0x40000>;
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};
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timer@200a024 {
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compatible = "qcom,msm-dgt", "qcom,msm-timer";
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interrupts = <1 3 0x301>;
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reg = <0x0200a024 0x10>,
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<0x0200a034 0x4>;
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clock-frequency = <6750000>;
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timer@200a000 {
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compatible = "qcom,scss-timer", "qcom,msm-timer";
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interrupts = <1 1 0x301>,
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<1 2 0x301>,
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<1 3 0x301>;
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reg = <0x0200a000 0x100>;
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clock-frequency = <19200000>,
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<32768>;
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cpu-offset = <0x40000>;
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};
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NVIDIA Tegra Power Management Controller (PMC)
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Properties:
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The PMC block interacts with an external Power Management Unit. The PMC
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mostly controls the entry and exit of the system from different sleep
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modes. It provides power-gating controllers for SoC and CPU power-islands.
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Required properties:
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- name : Should be pmc
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- compatible : Should contain "nvidia,tegra<chip>-pmc".
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- reg : Offset and length of the register set for the device
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- clocks : Must contain an entry for each entry in clock-names.
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- clock-names : Must include the following entries:
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"pclk" (The Tegra clock of that name),
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"clk32k_in" (The 32KHz clock input to Tegra).
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Optional properties:
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- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
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The PMU is an external Power Management Unit, whose interrupt output
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signal is fed into the PMC. This signal is optionally inverted, and then
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fed into the ARM GIC. The PMC is not involved in the detection or
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handling of this interrupt signal, merely its inversion.
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- nvidia,suspend-mode : The suspend mode that the platform should use.
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Valid values are 0, 1 and 2:
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0 (LP0): CPU + Core voltage off and DRAM in self-refresh
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1 (LP1): CPU voltage off and DRAM in self-refresh
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2 (LP2): CPU voltage off
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- nvidia,core-power-req-active-high : Boolean, core power request active-high
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- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high
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- nvidia,combined-power-req : Boolean, combined power request for CPU & Core
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- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
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is enabled.
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Required properties when nvidia,suspend-mode is specified:
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- nvidia,cpu-pwr-good-time : CPU power good time in uS.
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- nvidia,cpu-pwr-off-time : CPU power off time in uS.
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- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time>
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Core power good time in uS.
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- nvidia,core-pwr-off-time : Core power off time in uS.
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Required properties when nvidia,suspend-mode=<0>:
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- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector
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The LP0 vector contains the warm boot code that is executed by AVP when
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resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7
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processor and always being the first boot processor when chip is power on
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or resume from deep sleep mode. When the system is resumed from the deep
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sleep mode, the warm boot code will restore some PLLs, clocks and then
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bring up CPU0 for resuming the system.
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Example:
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/ SoC dts including file
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pmc@7000f400 {
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compatible = "nvidia,tegra20-pmc";
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reg = <0x7000e400 0x400>;
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clocks = <&tegra_car 110>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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nvidia,invert-interrupt;
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nvidia,suspend-mode = <1>;
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nvidia,cpu-pwr-good-time = <2000>;
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nvidia,cpu-pwr-off-time = <100>;
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nvidia,core-pwr-good-time = <3845 3845>;
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nvidia,core-pwr-off-time = <458>;
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nvidia,core-power-req-active-high;
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nvidia,sys-clock-req-active-high;
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nvidia,lp0-vec = <0xbdffd000 0x2000>;
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};
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/ Tegra board dts file
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{
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...
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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clk32k_in: clock {
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compatible = "fixed-clock";
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reg=<0>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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...
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};
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18
Documentation/devicetree/bindings/clock/altr_socfpga.txt
Normal file
18
Documentation/devicetree/bindings/clock/altr_socfpga.txt
Normal file
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Device Tree Clock bindings for Altera's SoCFPGA platform
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be one of the following:
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"altr,socfpga-pll-clock" - for a PLL clock
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"altr,socfpga-perip-clock" - The peripheral clock divided from the
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PLL clock.
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- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
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- clocks : shall be the input parent clock phandle for the clock. This is
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either an oscillator or a pll output.
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- #clock-cells : from common clock binding, shall be set to 0.
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Optional properties:
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- fixed-divider : If clocks have a fixed divider value, use this property.
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33
Documentation/devicetree/bindings/mmc/davinci_mmc.txt
Normal file
33
Documentation/devicetree/bindings/mmc/davinci_mmc.txt
Normal file
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* TI Highspeed MMC host controller for DaVinci
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The Highspeed MMC Host Controller on TI DaVinci family
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provides an interface for MMC, SD and SDIO types of memory cards.
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This file documents the properties used by the davinci_mmc driver.
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Required properties:
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- compatible:
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Should be "ti,da830-mmc": for da830, da850, dm365
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Should be "ti,dm355-mmc": for dm355, dm644x
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Optional properties:
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- bus-width: Number of data lines, can be <1>, <4>, or <8>, default <1>
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- max-frequency: Maximum operating clock frequency, default 25MHz.
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- dmas: List of DMA specifiers with the controller specific format
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as described in the generic DMA client binding. A tx and rx
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specifier is required.
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- dma-names: RX and TX DMA request names. These strings correspond
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1:1 with the DMA specifiers listed in dmas.
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Example:
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mmc0: mmc@1c40000 {
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compatible = "ti,da830-mmc",
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reg = <0x40000 0x1000>;
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interrupts = <16>;
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status = "okay";
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bus-width = <4>;
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max-frequency = <50000000>;
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dmas = <&edma 16
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&edma 17>;
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dma-names = "rx", "tx";
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};
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