From 97f4757feebdd3fb0d8f157e55d279031bdad736 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Tue, 30 Jun 2020 17:20:48 +0530 Subject: [PATCH] clk: qcom: Add support for pm ops for Multimedia clock controllers Add support for pm ops for Camera, Graphics and Video clock controllers. Change-Id: Ic9c01a35385a8c24899b66c9652810135bc42ac7 Signed-off-by: Jagadeesh Kona --- drivers/clk/qcom/camcc-shima.c | 28 +++++++++++++++++++++++++++- drivers/clk/qcom/gpucc-shima.c | 28 +++++++++++++++++++++++++++- drivers/clk/qcom/videocc-shima.c | 28 +++++++++++++++++++++++++++- 3 files changed, 81 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/camcc-shima.c b/drivers/clk/qcom/camcc-shima.c index aa4ce8a76bf6..238063e42111 100644 --- a/drivers/clk/qcom/camcc-shima.c +++ b/drivers/clk/qcom/camcc-shima.c @@ -9,6 +9,8 @@ #include #include #include +#include +#include #include #include @@ -2737,6 +2739,17 @@ static int cam_cc_shima_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); + pm_runtime_enable(&pdev->dev); + ret = pm_clk_create(&pdev->dev); + if (ret) + goto disable_pm_runtime; + + ret = pm_clk_add(&pdev->dev, "cfg_ahb"); + if (ret < 0) { + dev_err(&pdev->dev, "Unable to get ahb clock handle\n"); + goto destroy_pm_clk; + } + clk_lucid_5lpe_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); clk_lucid_5lpe_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); clk_zonda_5lpe_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); @@ -2748,14 +2761,26 @@ static int cam_cc_shima_probe(struct platform_device *pdev) ret = qcom_cc_really_probe(pdev, &cam_cc_shima_desc, regmap); if (ret) { dev_err(&pdev->dev, "Failed to register CAM CC clocks\n"); - return ret; + goto destroy_pm_clk; } dev_info(&pdev->dev, "Registered CAM CC clocks\n"); + return 0; + +destroy_pm_clk: + pm_clk_destroy(&pdev->dev); + +disable_pm_runtime: + pm_runtime_disable(&pdev->dev); + return ret; } +static const struct dev_pm_ops cam_cc_shima_pm_ops = { + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static void cam_cc_shima_sync_state(struct device *dev) { qcom_cc_sync_state(dev, &cam_cc_shima_desc); @@ -2767,6 +2792,7 @@ static struct platform_driver cam_cc_shima_driver = { .name = "cam_cc-shima", .of_match_table = cam_cc_shima_match_table, .sync_state = cam_cc_shima_sync_state, + .pm = &cam_cc_shima_pm_ops, }, }; diff --git a/drivers/clk/qcom/gpucc-shima.c b/drivers/clk/qcom/gpucc-shima.c index 9b577f008482..23f7cccadfc9 100644 --- a/drivers/clk/qcom/gpucc-shima.c +++ b/drivers/clk/qcom/gpucc-shima.c @@ -8,6 +8,8 @@ #include #include #include +#include +#include #include #include @@ -519,20 +521,43 @@ static int gpu_cc_shima_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); + pm_runtime_enable(&pdev->dev); + ret = pm_clk_create(&pdev->dev); + if (ret) + goto disable_pm_runtime; + + ret = pm_clk_add(&pdev->dev, "cfg_ahb"); + if (ret < 0) { + dev_err(&pdev->dev, "Unable to get ahb clock handle\n"); + goto destroy_pm_clk; + } + clk_lucid_5lpe_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); clk_lucid_5lpe_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); ret = qcom_cc_really_probe(pdev, &gpu_cc_shima_desc, regmap); if (ret) { dev_err(&pdev->dev, "Failed to register GPU CC clocks\n"); - return ret; + goto destroy_pm_clk; } dev_info(&pdev->dev, "Registered GPU CC clocks\n"); + return 0; + +destroy_pm_clk: + pm_clk_destroy(&pdev->dev); + +disable_pm_runtime: + pm_runtime_disable(&pdev->dev); + return ret; } +static const struct dev_pm_ops gpu_cc_shima_pm_ops = { + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static void gpu_cc_shima_sync_state(struct device *dev) { qcom_cc_sync_state(dev, &gpu_cc_shima_desc); @@ -544,6 +569,7 @@ static struct platform_driver gpu_cc_shima_driver = { .name = "gpu_cc-shima", .of_match_table = gpu_cc_shima_match_table, .sync_state = gpu_cc_shima_sync_state, + .pm = &gpu_cc_shima_pm_ops, }, }; diff --git a/drivers/clk/qcom/videocc-shima.c b/drivers/clk/qcom/videocc-shima.c index 614353d98bf4..cae46f83a983 100644 --- a/drivers/clk/qcom/videocc-shima.c +++ b/drivers/clk/qcom/videocc-shima.c @@ -8,6 +8,8 @@ #include #include #include +#include +#include #include #include @@ -575,20 +577,43 @@ static int video_cc_shima_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); + pm_runtime_enable(&pdev->dev); + ret = pm_clk_create(&pdev->dev); + if (ret) + goto disable_pm_runtime; + + ret = pm_clk_add(&pdev->dev, "cfg_ahb"); + if (ret < 0) { + dev_err(&pdev->dev, "Unable to get ahb clock handle\n"); + goto destroy_pm_clk; + } + clk_lucid_5lpe_pll_configure(&video_pll0, regmap, &video_pll0_config); clk_lucid_5lpe_pll_configure(&video_pll1, regmap, &video_pll1_config); ret = qcom_cc_really_probe(pdev, &video_cc_shima_desc, regmap); if (ret) { dev_err(&pdev->dev, "Failed to register VIDEO CC clocks\n"); - return ret; + goto destroy_pm_clk; } dev_info(&pdev->dev, "Registered VIDEO CC clocks\n"); + return 0; + +destroy_pm_clk: + pm_clk_destroy(&pdev->dev); + +disable_pm_runtime: + pm_runtime_disable(&pdev->dev); + return ret; } +static const struct dev_pm_ops video_cc_shima_pm_ops = { + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static void video_cc_shima_sync_state(struct device *dev) { qcom_cc_sync_state(dev, &video_cc_shima_desc); @@ -600,6 +625,7 @@ static struct platform_driver video_cc_shima_driver = { .name = "video_cc-shima", .of_match_table = video_cc_shima_match_table, .sync_state = video_cc_shima_sync_state, + .pm = &video_cc_shima_pm_ops, }, };