From 06b9ee95f93f50553457c7b1828b532fb98f487f Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Tue, 1 Dec 2020 17:20:47 +0530 Subject: [PATCH 1/4] ARM: dts: msm: Add core-hang detect nodes to SM6150 Add core-hang detect nodes for silver and gold core on SM6150. Change-Id: Id7177bedd71eba6c4287602b3ac668e1f48bd396 --- qcom/sm6150.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 6460aff6ac7e..b9b30eea4ef0 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -2139,6 +2139,23 @@ qcom,ipi-ping; qcom,wakeup-enable; }; + + qcom,chd_sliver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x18000058 0x18010058 0x18020058 + 0x18030058 0x18040058 0x18050058>; + qcom,config-arr = <0x18000060 0x18010060 0x18020060 + 0x18030060 0x18040060 0x18050060>; + }; + + qcom,chd_gold { + compatible = "qcom,core-hang-detect"; + label = "gold"; + qcom,threshold-arr = <0x18060058 0x18070058>; + qcom,config-arr = <0x18060060 0x18070060>; + }; + }; #include "sm6150-qupv3.dtsi" From 10e0744a3268028574d47bbc8b895793478bbb66 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Tue, 1 Dec 2020 00:20:47 +0530 Subject: [PATCH 2/4] ARM: dts: msm: Add mem-dump and CPU dump nodes to SM6150 Add mem-dump and CPU memory dump nodes to SM6150. Change-Id: If38e0285007e59b35ade8f74d3a983b08a802562 --- qcom/sm6150.dtsi | 340 +++++++++++++++++++++++++++++------------------ 1 file changed, 210 insertions(+), 130 deletions(-) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index b9b30eea4ef0..85ec4979f0c5 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -65,20 +65,6 @@ cache-level = <3>; }; }; - - L1_I_0: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x8800>; - }; - - L1_D_0: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9000>; - }; - - L2_TLB_0: l2-tlb { - qcom,dump-size = <0x5000>; - }; }; CPU1: cpu@100 { @@ -98,20 +84,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - - L1_I_100: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x8800>; - }; - - L1_D_100: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9000>; - }; - - L2_TLB_100: l1-tlb { - qcom,dump-size = <0x5000>; - }; }; @@ -132,20 +104,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - - L1_I_200: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x8800>; - }; - - L1_D_200: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9000>; - }; - - L2_TLB_200: l1-tlb { - qcom,dump-size = <0x5000>; - }; }; CPU3: cpu@300 { @@ -165,20 +123,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - - L1_I_300: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x8800>; - }; - - L1_D_300: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9000>; - }; - - L2_TLB_300: l1-tlb { - qcom,dump-size = <0x5000>; - }; }; CPU4: cpu@400 { @@ -198,20 +142,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - - L1_I_400: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x8800>; - }; - - L1_D_400: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9000>; - }; - - L2_TLB_400: l1-tlb { - qcom,dump-size = <0x5000>; - }; }; CPU5: cpu@500 { @@ -231,20 +161,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - - L1_I_500: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x8800>; - }; - - L1_D_500: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9000>; - }; - - L2_TLB_500: l1-tlb { - qcom,dump-size = <0x5000>; - }; }; CPU6: cpu@600 { @@ -263,29 +179,6 @@ cache-size = <0x40000>; cache-level = <2>; next-level-cache = <&L3_0>; - qcom,dump-size = <0x48000>; - }; - - L1_I_600: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x11000>; - }; - - L1_D_600: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x12000>; - }; - - L1_ITLB_600: l1-itlb { - qcom,dump-size = <0x300>; - }; - - L1_DTLB_600: l1-dtlb { - qcom,dump-size = <0x480>; - }; - - L2_TLB_600: l2-tlb { - qcom,dump-size = <0x7800>; }; }; @@ -305,29 +198,6 @@ cache-size = <0x40000>; cache-level = <2>; next-level-cache = <&L3_0>; - qcom,dump-size = <0x48000>; - }; - - L1_I_700: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x11000>; - }; - - L1_D_700: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x12000>; - }; - - L1_ITLB_700: l1-itlb { - qcom,dump-size = <0x300>; - }; - - L1_DTLB_700: l1-dtlb { - qcom,dump-size = <0x480>; - }; - - L2_TLB_700: l2-tlb { - qcom,dump-size = <0x7800>; }; }; @@ -1008,6 +878,216 @@ cap-based-alloc-and-pwr-collapse; }; + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + rpmh { + qcom,dump-size = <0x2000000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + tmc_etf { + qcom,dump-size = <0x8000>; + qcom,dump-id = <0xf0>; + }; + + etf_swao { + qcom,dump-size = <0x8000>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etf_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x101>; + }; + + etfswao_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + l1_icache0 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x60>; + }; + + l1_icache100 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x61>; + }; + + l1_icache200 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x62>; + }; + + l1_icache300 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x63>; + }; + + l1_icache400 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x64>; + }; + + l1_icache500 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x65>; + }; + + l1_icache600 { + qcom,dump-size = <0x11000>; + qcom,dump-id = <0x66>; + }; + + l1_icache700 { + qcom,dump-size = <0x11000>; + qcom,dump-id = <0x67>; + }; + + l1_dcache0 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x80>; + }; + + l1_dcache100 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x81>; + }; + + l1_dcache200 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x82>; + }; + + l1_dcache300 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x83>; + }; + + l1_dcache400 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x84>; + }; + + l1_dcache500 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x85>; + }; + + l1_dcache600 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x86>; + }; + + l1_dcache700 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x87>; + }; + + l1_itlb600 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x26>; + }; + + l1_itlb700 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x27>; + }; + + l1_dtlb600 { + qcom,dump-size = <0x480>; + qcom,dump-id = <0x46>; + }; + + l1_dtlb700 { + qcom,dump-size = <0x480>; + qcom,dump-id = <0x47>; + }; + + l2_cache600 { + qcom,dump-size = <0x48000>; + qcom,dump-id = <0xc6>; + }; + + l2_cache700 { + qcom,dump-size = <0x48000>; + qcom,dump-id = <0xc7>; + }; + + l2_tlb0 { + qcom,dump-size = <0x5000>; + qcom,dump-id = <0x120>; + }; + + l2_tlb100 { + qcom,dump-size = <0x5000>; + qcom,dump-id = <0x121>; + }; + + l2_tlb200 { + qcom,dump-size = <0x5000>; + qcom,dump-id = <0x122>; + }; + + l2_tlb300 { + qcom,dump-size = <0x5000>; + qcom,dump-id = <0x123>; + }; + + l2_tlb400 { + qcom,dump-size = <0x5000>; + qcom,dump-id = <0x124>; + }; + + l2_tlb500 { + qcom,dump-size = <0x5000>; + qcom,dump-id = <0x125>; + }; + + l2_tlb600 { + qcom,dump-size = <0x7800>; + qcom,dump-id = <0x126>; + }; + + l2_tlb700 { + qcom,dump-size = <0x7800>; + qcom,dump-id = <0x127>; + }; + + llcc1_d_cache { + qcom,dump-size = <0x6c000>; + qcom,dump-id = <0x140>; + }; + }; + apps_rsc: rsc@18200000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc"; From 15048bee5ec0493631b5ecc02480e3a12edf000d Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Mon, 12 Oct 2020 17:26:06 +0530 Subject: [PATCH 3/4] ARM: dts: msm: Add secure_buffer and qcom,scm device on SM6150 Add device nodes for secure buffer and scm for SM6150 SoC. This is needed to secure memory buffers, and protect them against unauthorized access. Change-Id: I44b78b96382133485b0d3eb45e07264dd04555b4 --- qcom/sm6150.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 85ec4979f0c5..2b04e0d68c73 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -419,6 +419,11 @@ linux,cma-default; }; }; + + qcom-secure-buffer { + compatible = "qcom,secure-buffer"; + }; + }; &soc { @@ -865,6 +870,12 @@ qcom,rtb-size = <0x100000>; }; + pil_scm_pas { + compatible = "qcom,pil-tz-scm-pas"; + interconnects = <&aggre1_noc MASTER_CRYPTO + &mc_virt SLAVE_EBI1>; + }; + qcom,mpm2-sleep-counter@0xc221000 { compatible = "qcom,mpm2-sleep-counter"; reg = <0xc221000 0x1000>; @@ -2245,6 +2256,12 @@ #include "sm6150-regulator.dtsi" #include "sm6150-gdsc.dtsi" +&firmware { + scm { + compatible = "qcom,scm"; + }; +}; + &emac_gdsc { status = "ok"; }; From 3fef3a83cec04ac735d86da98315d1812d7edab4 Mon Sep 17 00:00:00 2001 From: Akshay Adiga Date: Wed, 18 Nov 2020 16:24:38 +0530 Subject: [PATCH 4/4] ARM: dts: msm: Add dt node for msm-poweroff on SM6150 Add dt node for msm-poweroff on SM6150. Change-Id: Ib219816131d8a951bdf4e6a86d0d77c5c22c1f31 --- qcom/sm6150.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 2b04e0d68c73..32b3967c4faf 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -865,6 +865,13 @@ }; }; + restart@c264000 { + compatible = "qcom,pshold"; + reg = <0xc264000 0x4>, + <0x1fd3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + qcom,msm-rtb { compatible = "qcom,msm-rtb"; qcom,rtb-size = <0x100000>;