From 248a81aded737d486ed241310bf0dacdda8b488d Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Fri, 17 Jul 2020 16:27:23 +0530 Subject: [PATCH] ARM: dts: msm: Add eMMC, SD card support for holi Add eMMC, SD card support for holi. Change-Id: I109cfa4e90fe05b5be56efdda0ac7119f5a64c71 --- qcom/holi-pinctrl.dtsi | 102 +++++++++++++++++++++++++++++++++++++++++ qcom/holi-rumi.dtsi | 41 +++++++++++++++++ qcom/holi.dtsi | 45 ++++++++++++++++++ 3 files changed, 188 insertions(+) diff --git a/qcom/holi-pinctrl.dtsi b/qcom/holi-pinctrl.dtsi index 6b04ec959676..c03572c4c98d 100644 --- a/qcom/holi-pinctrl.dtsi +++ b/qcom/holi-pinctrl.dtsi @@ -384,6 +384,108 @@ }; }; + sdc1_on: sdc1_on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_off: sdc1_off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_on: sdc2_on { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio94"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc2_off { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd { + pins = "gpio94"; + bias-disable; + drive-strength = <2>; + }; + }; + pmx_sde_te: pmx_sde_te { sde_te_active: sde_te_active { mux { diff --git a/qcom/holi-rumi.dtsi b/qcom/holi-rumi.dtsi index 55a700f47966..e6b2dbb0010c 100644 --- a/qcom/holi-rumi.dtsi +++ b/qcom/holi-rumi.dtsi @@ -1,3 +1,4 @@ +#include &soc { timer { clock-frequency = <500000>; @@ -43,6 +44,46 @@ }; }; +&sdhc_1 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + cap-mmc-highspeed; + + vdd-supply = <&L7E>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L12A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; +}; + +&sdhc_2 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cap-sd-highspeed; + + vdd-supply = <&L9E>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L6E>; + qcom,vdd-io-voltage-level = <2960000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; +}; + &ufsphy_mem { compatible = "qcom,ufs-phy-qrbtc-sdm845"; diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 63168dd34e94..1515cfcf97b0 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -22,6 +22,9 @@ aliases { ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ + + sdhc1 = &sdhc_1; /*SDC1 eMMC slot*/ + sdhc2 = &sdhc_2; /* SDC2 SD card slot */ serial0 = &qupv3_se9_2uart; hsuart0 = &qupv3_se1_4uart; }; @@ -1517,6 +1520,48 @@ status = "disabled"; }; + sdhc_1: sdhci@4744000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x04744000 0x1000>, <0x04745000 0x1000>; + reg-names = "hc_mem", "cqhci_mem"; + + iommus = <&apps_smmu 0x20 0x0>; + qcom,iommu-dma = "bypass"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; + clock-names = "core", "iface"; + + bus-width = <8>; + non-removable; + supports-cqe; + + status = "disabled"; + }; + + sdhc_2: sdhci@4784000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x04784000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; + clock-names = "core", "iface"; + + bus-width = <4>; + + iommus = <&apps_smmu 0x40 0x0>; + qcom,iommu-dma = "bypass"; + + status = "disabled"; + }; + qcom,lpass@a400000 { compatible = "qcom,pil-tz-generic"; reg = <0xa400000 0x00100>;