From a1a9d1bd1584e03198496014d438c4bba6720d7b Mon Sep 17 00:00:00 2001 From: Mohammed Mirza Mandayappurath Manzoor Date: Wed, 24 Jun 2020 22:05:24 -0700 Subject: [PATCH 1/4] msm: kgsl: Include data from all power levels in ACD table Update the logic to include data from all powerlevels in ACD table for ACD to be enabled on all levels. Change-Id: I0da7ab5e4449bbe38bc292c63f0d1a72c3991a0f Signed-off-by: Mohammed Mirza Mandayappurath Manzoor --- drivers/gpu/msm/adreno_a6xx_gmu.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/msm/adreno_a6xx_gmu.c b/drivers/gpu/msm/adreno_a6xx_gmu.c index b583a336cda9..9f4674ad476b 100644 --- a/drivers/gpu/msm/adreno_a6xx_gmu.c +++ b/drivers/gpu/msm/adreno_a6xx_gmu.c @@ -2437,9 +2437,10 @@ static void a6xx_gmu_acd_probe(struct kgsl_device *device, { struct adreno_device *adreno_dev = ADRENO_DEVICE(device); struct kgsl_pwrctrl *pwr = &device->pwrctrl; + struct kgsl_pwrlevel *pwrlevel = + &pwr->pwrlevels[pwr->num_pwrlevels - 1]; struct hfi_acd_table_cmd *cmd = &gmu->hfi.acd_table; - u32 acd_level, cmd_idx, numlvl = pwr->num_pwrlevels; - int ret, i; + int ret, i, cmd_idx = 0; if (!ADRENO_FEATURE(adreno_dev, ADRENO_ACD)) return; @@ -2449,12 +2450,17 @@ static void a6xx_gmu_acd_probe(struct kgsl_device *device, cmd->stride = 1; cmd->enable_by_level = 0; - for (i = 0, cmd_idx = 0; i < numlvl; i++) { - acd_level = pwr->pwrlevels[numlvl - i].acd_level; - if (acd_level) { - cmd->enable_by_level |= (1 << i); - cmd->data[cmd_idx++] = acd_level; + /* + * Iterate through each gpu power level and generate a mask for GMU + * firmware for ACD enabled levels and store the corresponding control + * register configurations to the acd_table structure. + */ + for (i = 0; i < pwr->num_pwrlevels; i++) { + if (pwrlevel->acd_level) { + cmd->enable_by_level |= (1 << (i + 1)); + cmd->data[cmd_idx++] = pwrlevel->acd_level; } + pwrlevel--; } if (!cmd->enable_by_level) From e12a8b83d2307a0a0205269c2a85c50f741935c8 Mon Sep 17 00:00:00 2001 From: Mohammed Mirza Mandayappurath Manzoor Date: Tue, 2 Jun 2020 12:33:26 -0700 Subject: [PATCH 2/4] msm: kgsl: Enable Adaptive Clock Distribution feature for A660 v2 ACD is a power saving feature to mitigate voltage droops. Change-Id: I43502bd44946463f7db30011e233255217cb02e0 Signed-off-by: Mohammed Mirza Mandayappurath Manzoor --- drivers/gpu/msm/adreno-gpulist.h | 34 +++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/msm/adreno-gpulist.h b/drivers/gpu/msm/adreno-gpulist.h index 33c7ac12b21b..f43efef02fb3 100644 --- a/drivers/gpu/msm/adreno-gpulist.h +++ b/drivers/gpu/msm/adreno-gpulist.h @@ -1551,7 +1551,7 @@ static const struct a6xx_protected_regs a660_protected_regs[] = { static const struct adreno_a6xx_core adreno_gpu_core_a660 = { .base = { - DEFINE_ADRENO_REV(ADRENO_REV_A660, 6, 6, 0, ANY_ID), + DEFINE_ADRENO_REV(ADRENO_REV_A660, 6, 6, 0, 0), .features = ADRENO_RPMH | ADRENO_GPMU | ADRENO_APRIV | ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC | ADRENO_PREEMPTION, @@ -1580,6 +1580,37 @@ static const struct adreno_a6xx_core adreno_gpu_core_a660 = { .ctxt_record_size = 2496 * 1024, }; +static const struct adreno_a6xx_core adreno_gpu_core_a660v2 = { + .base = { + DEFINE_ADRENO_REV(ADRENO_REV_A660, 6, 6, 0, ANY_ID), + .features = ADRENO_RPMH | ADRENO_GPMU | ADRENO_APRIV | + ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION | + ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_ACD, + .gpudev = &adreno_a6xx_gmu_gpudev, + .gmem_base = 0, + .gmem_size = SZ_1M + SZ_512K, + .bus_width = 32, + .snapshot_size = SZ_2M, + }, + .prim_fifo_threshold = 0x00300000, + .gmu_major = 2, + .gmu_minor = 0, + .sqefw_name = "a660_sqe.fw", + .gmufw_name = "a660_gmu.bin", + .zap_name = "a660_zap", + .hwcg = a660_hwcg_regs, + .hwcg_count = ARRAY_SIZE(a660_hwcg_regs), + .vbif = a650_gbif_regs, + .vbif_count = ARRAY_SIZE(a650_gbif_regs), + .hang_detect_cycles = 0xcfffff, + .veto_fal10 = true, + .protected_regs = a660_protected_regs, + .disable_tseskip = true, + .highest_bank_bit = 16, + .pdc_in_aop = true, + .ctxt_record_size = 2496 * 1024, +}; + static const struct adreno_a6xx_core adreno_gpu_core_a660_shima = { .base = { DEFINE_ADRENO_REV(ADRENO_REV_A660, 6, 6, 0, ANY_ID), @@ -1639,6 +1670,7 @@ static const struct adreno_gpu_core *adreno_gpulist[] = { &adreno_gpu_core_a650.base, &adreno_gpu_core_a650v2.base, &adreno_gpu_core_a660.base, + &adreno_gpu_core_a660v2.base, &adreno_gpu_core_a680.base, &adreno_gpu_core_a612.base, &adreno_gpu_core_a616.base, From eb3e2f6ce3405123a26a22eb81d6103fa353c1c6 Mon Sep 17 00:00:00 2001 From: Mohammed Mirza Mandayappurath Manzoor Date: Wed, 12 Aug 2020 12:53:53 -0700 Subject: [PATCH 3/4] msm: kgsl: Fix maximum allowed power level for A660 Update the logic that checks maximum allowed power level to accommodate new frequency corners. Change-Id: I85c9db7e39c75b14ee77464ca6fcdf5855653b25 Signed-off-by: Mohammed Mirza Mandayappurath Manzoor --- drivers/gpu/msm/governor_msm_adreno_tz.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/msm/governor_msm_adreno_tz.c b/drivers/gpu/msm/governor_msm_adreno_tz.c index 70dac21ebf6c..7d75b95bf992 100644 --- a/drivers/gpu/msm/governor_msm_adreno_tz.c +++ b/drivers/gpu/msm/governor_msm_adreno_tz.c @@ -480,7 +480,7 @@ static int tz_start(struct devfreq *devfreq) priv->nb.notifier_call = tz_notify; out = 1; - if (devfreq->profile->max_state < MSM_ADRENO_MAX_PWRLEVELS) { + if (devfreq->profile->max_state < ARRAY_SIZE(tz_pwrlevels)) { for (i = 0; i < devfreq->profile->max_state; i++) tz_pwrlevels[out++] = devfreq->profile->freq_table[i]; tz_pwrlevels[0] = i; From 44bfe6de8e67ae69c71f18857644d76c59b9fadf Mon Sep 17 00:00:00 2001 From: Mohammed Mirza Mandayappurath Manzoor Date: Mon, 3 Aug 2020 09:36:00 -0700 Subject: [PATCH 4/4] msm: kgsl: Make ACD QMP message sending failure non fatal If ACD fails to send its state through the QMP mailbox, we do not get the power saving as expected. An error message will do and need not fail probe. Change-Id: I821d0d3c774cc45726a8c7b281d226ff5da83fa5 Signed-off-by: Mohammed Mirza Mandayappurath Manzoor --- drivers/gpu/msm/adreno_a6xx_gmu.c | 29 +++++++++++------------------ 1 file changed, 11 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/msm/adreno_a6xx_gmu.c b/drivers/gpu/msm/adreno_a6xx_gmu.c index 9f4674ad476b..21f0521b245d 100644 --- a/drivers/gpu/msm/adreno_a6xx_gmu.c +++ b/drivers/gpu/msm/adreno_a6xx_gmu.c @@ -2059,22 +2059,27 @@ void a6xx_gmu_snapshot(struct adreno_device *adreno_dev, } -static int a6xx_gmu_aop_send_acd_state(struct mbox_chan *channel, bool flag) +static void a6xx_gmu_aop_send_acd_state(struct a6xx_gmu_device *gmu, bool flag) { char msg_buf[33]; + int ret; struct { u32 len; void *msg; } msg; - if (IS_ERR_OR_NULL(channel)) - return 0; + if (IS_ERR_OR_NULL(gmu->mailbox.channel)) + return; msg.len = scnprintf(msg_buf, sizeof(msg_buf), "{class: gpu, res: acd, value: %d}", flag); msg.msg = msg_buf; - return mbox_send_message(channel, &msg); + ret = mbox_send_message(gmu->mailbox.channel, &msg); + + if (ret < 0) + dev_err(&gmu->pdev->dev, + "AOP mbox send message failed: %d\n", ret); } static int a6xx_gmu_enable_gdsc(struct adreno_device *adreno_dev) @@ -2140,13 +2145,7 @@ static int a6xx_gmu_first_boot(struct adreno_device *adreno_dev) trace_kgsl_pwr_request_state(device, KGSL_STATE_AWARE); - ret = a6xx_gmu_aop_send_acd_state(gmu->mailbox.channel, - adreno_dev->acd_enabled); - if (ret) { - dev_err(&gmu->pdev->dev, - "AOP mbox send message failed: %d\n", ret); - return ret; - } + a6xx_gmu_aop_send_acd_state(gmu, adreno_dev->acd_enabled); ret = a6xx_gmu_enable_gdsc(adreno_dev); if (ret) @@ -2314,15 +2313,9 @@ gdsc_off: static void set_acd(struct adreno_device *adreno_dev, void *priv) { struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev); - int ret; adreno_dev->acd_enabled = *((bool *)priv); - - ret = a6xx_gmu_aop_send_acd_state(gmu->mailbox.channel, - adreno_dev->acd_enabled); - if (ret) - dev_err(&gmu->pdev->dev, - "AOP mbox send message failed: %d\n", ret); + a6xx_gmu_aop_send_acd_state(gmu, adreno_dev->acd_enabled); } static int a6xx_gmu_acd_set(struct kgsl_device *device, bool val)