mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-10 22:40:54 -04:00
input: himax_v2_mmi: add hx83102d driver
input/himax_v2_mmi: Add HX83102D driver. HX83102D is different from others, so need to add CODE_OVERLAY and its own drivers. The first TP is hx83102D without flash Change-Id: I68df2f1cc365041367de75ef8b52cecf677c70d0 Reviewed-on: https://gerrit.mot.com/1478452 SLTApproved: Slta Waiver SME-Granted: SME Approvals Granted Tested-by: Jira Key Reviewed-by: Huosheng Liao <liaohs@motorola.com> Submit-Approved: Jira Key
This commit is contained in:
parent
aa3a6cf3d8
commit
99014c1e2b
14 changed files with 1841 additions and 5 deletions
|
|
@ -22,6 +22,10 @@ ifneq ($(BOARD_USES_HIMAX_MULTI_BIN),)
|
|||
KERNEL_CFLAGS += CONFIG_INPUT_HIMAX_V2_MMI_ENABLE_MULTI_BIN=y
|
||||
endif
|
||||
|
||||
ifeq ($(HIMAX_V2_MMI_HX83102D),true)
|
||||
KERNEL_CFLAGS += CONFIG_INPUT_HIMAX_V2_MMI_IC_NAME_D=hx83102d
|
||||
endif
|
||||
|
||||
include $(CLEAR_VARS)
|
||||
LOCAL_MODULE := himax_v2_mmi.ko
|
||||
LOCAL_MODULE_TAGS := optional
|
||||
|
|
|
|||
|
|
@ -16,6 +16,11 @@ ifneq ($(filter hx83102,$(CONFIG_INPUT_HIMAX_V2_MMI_IC_NAME)),)
|
|||
EXTRA_CFLAGS += -D__HIMAX_HX83102_MOD__
|
||||
endif
|
||||
|
||||
ifneq ($(filter hx83102d,$(CONFIG_INPUT_HIMAX_V2_MMI_IC_NAME_D)),)
|
||||
EXTRA_CFLAGS += -D__HIMAX_HX83102D_MOD__
|
||||
EXTRA_CFLAGS += -DHX_CODE_OVERLAY
|
||||
endif
|
||||
|
||||
ifneq ($(filter m y,$(CONFIG_INPUT_TOUCHSCREEN_HIMAX_V2_MMI_ENABLE_PALM)),)
|
||||
EXTRA_CFLAGS += -DHIMAX_PALM_SENSOR_EN
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -3154,6 +3154,10 @@ GET_TOUCH_FAIL:
|
|||
#else
|
||||
g_core_fp.fp_system_reset();
|
||||
#endif
|
||||
#if defined(HX_ZERO_FLASH) && defined(HX83102D)
|
||||
if (g_core_fp.fp_0f_reload_to_active)
|
||||
g_core_fp.fp_0f_reload_to_active();
|
||||
#endif
|
||||
END_FUNCTION:
|
||||
if (debug_data != NULL)
|
||||
debug_data->fp_ts_dbg_func(ts, HX_FINGER_LEAVE);
|
||||
|
|
|
|||
|
|
@ -461,7 +461,7 @@ struct himax_ts_data {
|
|||
struct workqueue_struct *himax_diag_wq;
|
||||
struct delayed_work himax_diag_delay_wrok;
|
||||
|
||||
#ifdef HX_SMART_WAKEUP
|
||||
#if defined (HX_SMART_WAKEUP) || defined (HX_CODE_OVERLAY)
|
||||
uint8_t SMWP_enable;
|
||||
uint8_t gesture_cust_en[26];
|
||||
struct wakeup_source ts_SMWP_wake_lock;
|
||||
|
|
|
|||
|
|
@ -1577,6 +1577,10 @@ static ssize_t himax_reset_write(char *buf, size_t len)
|
|||
g_core_fp.fp_ic_reset(true, true);
|
||||
/* else if (buf[0] == '5') */
|
||||
/* ESD_HW_REST(); */
|
||||
#endif
|
||||
#if defined(HX_ZERO_FLASH) && defined(HX83102D)
|
||||
if (g_core_fp.fp_0f_reload_to_active)
|
||||
g_core_fp.fp_0f_reload_to_active();
|
||||
#endif
|
||||
return len;
|
||||
}
|
||||
|
|
@ -2337,6 +2341,10 @@ static ssize_t himax_debug_write(struct file *file, const char *buff,
|
|||
g_core_fp.fp_ic_reset(true, false);
|
||||
#else
|
||||
g_core_fp.fp_system_reset();
|
||||
#endif
|
||||
#if defined(HX_ZERO_FLASH) && defined(HX83102D)
|
||||
if (g_core_fp.fp_0f_reload_to_active)
|
||||
g_core_fp.fp_0f_reload_to_active();
|
||||
#endif
|
||||
himax_int_enable(1);
|
||||
/* himax_check_chip_version(); */
|
||||
|
|
@ -2503,6 +2511,10 @@ static ssize_t himax_debug_write(struct file *file, const char *buff,
|
|||
return len;
|
||||
} else if (buf[0] == 'x') {
|
||||
g_core_fp.fp_system_reset();
|
||||
#if defined(HX_ZERO_FLASH) && defined(HX83102D)
|
||||
if (g_core_fp.fp_0f_reload_to_active)
|
||||
g_core_fp.fp_0f_reload_to_active();
|
||||
#endif
|
||||
return len;
|
||||
#endif
|
||||
} else if (buf[0] == 'l' && buf[1] == 'o' && buf[2] == 't') {
|
||||
|
|
@ -2522,6 +2534,10 @@ firmware_upgrade_done:
|
|||
g_core_fp.fp_touch_information();
|
||||
#ifdef HX_RST_PIN_FUNC
|
||||
g_core_fp.fp_ic_reset(true, false);
|
||||
#if defined(HX_ZERO_FLASH) && defined(HX83102D)
|
||||
if (g_core_fp.fp_0f_reload_to_active)
|
||||
g_core_fp.fp_0f_reload_to_active();
|
||||
#endif
|
||||
#else
|
||||
g_core_fp.fp_sense_on(0x00);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -64,6 +64,11 @@
|
|||
#define HX_MOD_KSYM_HX83102 HX_MOD_KSYM_HX83102
|
||||
#endif
|
||||
|
||||
#if defined(__HIMAX_HX83102D_MOD__)
|
||||
#define HX_MOD_KSYM_HX83102 HX_MOD_KSYM_HX83102
|
||||
#define HX83102D
|
||||
#endif
|
||||
|
||||
#if defined(__HIMAX_HX83103_MOD__)
|
||||
#define HX_MOD_KSYM_HX83103 HX_MOD_KSYM_HX83103
|
||||
#endif
|
||||
|
|
@ -473,6 +478,16 @@ struct hx_guest_info {
|
|||
#define zf_data_activ_in 0xEC
|
||||
|
||||
#if defined(HX_CODE_OVERLAY)
|
||||
#if defined(HX83102D)
|
||||
#define ovl_section_num 3
|
||||
#define ovl_gesture_request 0x11
|
||||
#define ovl_gesture_reply 0x22
|
||||
#define ovl_border_request 0x55
|
||||
#define ovl_border_reply 0x66
|
||||
#define ovl_sorting_request 0x99
|
||||
#define ovl_sorting_reply 0xAA
|
||||
#define ovl_fault 0xFF
|
||||
#else
|
||||
#define ovl_isram_addr 0x20008CE0
|
||||
#define ovl_handshaking_addr 0x10007FFC
|
||||
#define ovl_gesture_request 0x11
|
||||
|
|
@ -480,6 +495,7 @@ struct hx_guest_info {
|
|||
#define ovl_border_request 0x55
|
||||
#define ovl_border_reply 0x66
|
||||
#endif
|
||||
#endif
|
||||
|
||||
struct zf_info {
|
||||
uint8_t sram_addr[4];
|
||||
|
|
@ -945,6 +961,9 @@ struct himax_core_fp {
|
|||
int (*fp_0f_op_file_dirly)(char *file_name);
|
||||
void (*fp_0f_operation)(struct work_struct *work);
|
||||
int (*fp_0f_esd_check)(void);
|
||||
#if defined(HX83102D)
|
||||
void (*fp_0f_reload_to_active)(void);
|
||||
#endif
|
||||
#ifdef HX_0F_DEBUG
|
||||
void (*fp_read_sram_0f)(const struct firmware *fw_entry, uint8_t *addr, int start_index, int read_len);
|
||||
void (*fp_read_all_sram)(uint8_t *addr, int read_len);
|
||||
|
|
|
|||
|
|
@ -30,6 +30,10 @@ EXPORT_SYMBOL(pdriver_op);
|
|||
#ifdef HX_ZERO_FLASH
|
||||
struct zf_operation *pzf_op;
|
||||
EXPORT_SYMBOL(pzf_op);
|
||||
#if defined(HX_CODE_OVERLAY) && defined(HX83102D)
|
||||
uint8_t *ovl_idx;
|
||||
EXPORT_SYMBOL(ovl_idx);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
void (*himax_mcu_cmd_struct_free)(void);
|
||||
|
|
@ -2610,6 +2614,149 @@ int himax_sram_write_crc_check(const struct firmware *fw_entry, uint8_t *addr, i
|
|||
|
||||
return crc;
|
||||
}
|
||||
#if defined(HX83102D)
|
||||
int hx_parse_bin_cfg_data(const struct firmware *fw_entry, struct zf_info *zf_info_arr, uint8_t *FW_buf, uint8_t *sram_min)
|
||||
{
|
||||
int part_num = 0;
|
||||
int i = 0;
|
||||
uint8_t buf[16];
|
||||
int i_max = 0;
|
||||
int i_min = 0;
|
||||
uint32_t dsram_base = 0xFFFFFFFF;
|
||||
uint32_t dsram_max = 0;
|
||||
int cfg_sz = 0;
|
||||
#if defined(HX_CODE_OVERLAY)
|
||||
uint8_t j = 0;
|
||||
int allovlidx = 0;
|
||||
|
||||
if (ovl_idx == NULL) {
|
||||
ovl_idx = kzalloc(ovl_section_num, GFP_KERNEL);
|
||||
if (ovl_idx == NULL) {
|
||||
E("%s, ovl_idx alloc failed!\n",
|
||||
__func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
} else {
|
||||
memset(ovl_idx, 0, ovl_section_num);
|
||||
}
|
||||
#endif
|
||||
/*1. get number of partition*/
|
||||
part_num = fw_entry->data[HX64K + 12];
|
||||
I("%s, Number of partition is %d\n", __func__, part_num);
|
||||
if (part_num <= 1) {
|
||||
E("%s, size of cfg part failed! part_num = %d\n",
|
||||
__func__, part_num);
|
||||
return LENGTH_FAIL;
|
||||
}
|
||||
|
||||
/* i = 0 is fw entity, it need to update by itself*/
|
||||
for (i = 1; i < part_num; i++) {
|
||||
/*3. get all partition*/
|
||||
memcpy(buf, &fw_entry->data[i * 0x10 + HX64K], 16);
|
||||
memcpy(zf_info_arr[i].sram_addr, buf, 4);
|
||||
zf_info_arr[i].write_size = buf[7] << 24
|
||||
| buf[6] << 16
|
||||
| buf[5] << 8
|
||||
| buf[4];
|
||||
zf_info_arr[i].fw_addr = buf[11] << 24
|
||||
| buf[10] << 16
|
||||
| buf[9] << 8
|
||||
| buf[8];
|
||||
zf_info_arr[i].cfg_addr = zf_info_arr[i].sram_addr[0];
|
||||
zf_info_arr[i].cfg_addr += zf_info_arr[i].sram_addr[1] << 8;
|
||||
zf_info_arr[i].cfg_addr += zf_info_arr[i].sram_addr[2] << 16;
|
||||
zf_info_arr[i].cfg_addr += zf_info_arr[i].sram_addr[3] << 24;
|
||||
|
||||
#if defined(HX_CODE_OVERLAY)
|
||||
/*overlay section*/
|
||||
|
||||
if ((buf[15] == 0x55 && buf[14] == 0x66)
|
||||
|| (buf[3] == 0x20 && buf[2] == 0x00
|
||||
&& buf[1] == 0x8C && buf[0] == 0xE0)) {
|
||||
I("%s: catch overlay section in index %d\n",
|
||||
__func__, i);
|
||||
|
||||
/* record index of overlay section */
|
||||
allovlidx |= 1<<i;
|
||||
|
||||
if (buf[15] == 0x55 && buf[14] == 0x66) {
|
||||
/* current mechanism */
|
||||
j = buf[13];
|
||||
if (j < ovl_section_num)
|
||||
ovl_idx[j] = i;
|
||||
} else {
|
||||
/* previous mechanism */
|
||||
if (j < ovl_section_num)
|
||||
ovl_idx[j++] = i;
|
||||
}
|
||||
|
||||
continue;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (dsram_base > zf_info_arr[i].cfg_addr) {
|
||||
dsram_base = zf_info_arr[i].cfg_addr;
|
||||
i_min = i;
|
||||
}
|
||||
if (dsram_max < zf_info_arr[i].cfg_addr) {
|
||||
dsram_max = zf_info_arr[i].cfg_addr;
|
||||
i_max = i;
|
||||
}
|
||||
}
|
||||
for (i = 0; i < ADDR_LEN_4; i++)
|
||||
sram_min[i] = zf_info_arr[i_min].sram_addr[i];
|
||||
|
||||
cfg_sz = (dsram_max - dsram_base) + zf_info_arr[i_max].write_size;
|
||||
if (cfg_sz % 16 != 0)
|
||||
cfg_sz = cfg_sz + 16 - (cfg_sz % 16);
|
||||
|
||||
I("%s, cfg_sz = %d!, dsram_base = %X, dsram_max = %X\n", __func__,
|
||||
cfg_sz, dsram_base, dsram_max);
|
||||
if (cfg_sz <= FW_BIN_16K_SZ)
|
||||
memset(FW_buf, 0x00, sizeof(uint8_t) * cfg_sz);
|
||||
else
|
||||
memset(FW_buf, 0x00, sizeof(uint8_t) * FW_BIN_16K_SZ);
|
||||
for (i = 1; i < part_num; i++) {
|
||||
if (zf_info_arr[i].cfg_addr % 4 != 0)
|
||||
zf_info_arr[i].cfg_addr = zf_info_arr[i].cfg_addr
|
||||
- (zf_info_arr[i].cfg_addr % 4);
|
||||
|
||||
I("%s,[%d]SRAM addr=%08X,[%d]fw_addr=%08X,[%d]write_size=%d\n",
|
||||
__func__,
|
||||
i, zf_info_arr[i].cfg_addr,
|
||||
i, zf_info_arr[i].fw_addr,
|
||||
i, zf_info_arr[i].write_size);
|
||||
|
||||
#if defined(HX_CODE_OVERLAY)
|
||||
/*overlay section*/
|
||||
if (allovlidx & (1<<i)) {
|
||||
I("%s: skip overlay section %d\n", __func__, i);
|
||||
continue;
|
||||
}
|
||||
#endif
|
||||
|
||||
memcpy(&FW_buf[zf_info_arr[i].cfg_addr - dsram_base],
|
||||
&fw_entry->data[zf_info_arr[i].fw_addr],
|
||||
zf_info_arr[i].write_size);
|
||||
}
|
||||
/* debug info */
|
||||
/* for (i = 1; i < part_num; i++) {
|
||||
* different = 0;
|
||||
* I("--cfg_addr = 0x%08X\n",zf_info_arr[i].cfg_addr);
|
||||
* I("--bin_addr = 0x%08X\n",zf_info_arr[i].fw_addr);
|
||||
* I("--write size = %d\n",zf_info_arr[i].write_size);
|
||||
* for ( j = 0; j < zf_info_arr[i].write_size; j++) {
|
||||
* if(FW_buf[zf_info_arr[i].cfg_addr - dsram_base + j] !=
|
||||
fw_entry->data[zf_info_arr[i].fw_addr + j])
|
||||
* different++;
|
||||
* }
|
||||
* I("--There are %d different\n", different);
|
||||
* }
|
||||
*/
|
||||
|
||||
return cfg_sz;
|
||||
}
|
||||
#else
|
||||
int hx_parse_bin_cfg_data(const struct firmware *fw_entry, struct zf_info *zf_info_arr, uint8_t *FW_buf, uint8_t *sram_min, uint8_t *ovl_sidx)
|
||||
{
|
||||
int part_num = 0;
|
||||
|
|
@ -2708,6 +2855,8 @@ int hx_parse_bin_cfg_data(const struct firmware *fw_entry, struct zf_info *zf_in
|
|||
|
||||
return cfg_sz;
|
||||
}
|
||||
#endif
|
||||
|
||||
int himax_zf_part_info(const struct firmware *fw_entry)
|
||||
{
|
||||
int part_num = fw_entry->data[HX64K + 12];
|
||||
|
|
@ -2722,12 +2871,21 @@ int himax_zf_part_info(const struct firmware *fw_entry)
|
|||
int retry = 3;
|
||||
|
||||
uint8_t ovl_sidx = 0;
|
||||
#if defined(HX83102D)
|
||||
uint8_t ovl_idx_t;
|
||||
#if defined(HX_SMART_WAKEUP) || defined(HX_CODE_OVERLAY)
|
||||
uint8_t tmp_addr[4] = {0xFC, 0x7F, 0x00, 0x10};
|
||||
uint8_t send_data[4] = {0};
|
||||
uint8_t recv_data[4] = {0};
|
||||
#endif
|
||||
#else
|
||||
#ifdef HX_CODE_OVERLAY
|
||||
#ifdef HX_SMART_WAKEUP
|
||||
uint8_t tmp_addr[4] = {0xFC, 0x7F, 0x00, 0x10};
|
||||
uint8_t send_data[4] = {0};
|
||||
uint8_t recv_data[4] = {0};
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*1. get number of partition*/
|
||||
|
|
@ -2753,7 +2911,11 @@ int himax_zf_part_info(const struct firmware *fw_entry)
|
|||
|
||||
/*3. Find the data in the bin file */
|
||||
/*CFG*/
|
||||
#if defined(HX83102D)
|
||||
cfg_sz = hx_parse_bin_cfg_data(fw_entry, zf_info_arr, FW_buf, sram_min);
|
||||
#else
|
||||
cfg_sz = hx_parse_bin_cfg_data(fw_entry, zf_info_arr, FW_buf, sram_min, &ovl_sidx);
|
||||
#endif
|
||||
I("Now cfg_sz=%d\n", cfg_sz);
|
||||
if (cfg_sz < 0) {
|
||||
ret = LENGTH_FAIL;
|
||||
|
|
@ -2788,6 +2950,28 @@ int himax_zf_part_info(const struct firmware *fw_entry)
|
|||
} while (cfg_crc_hw != cfg_crc_sw && retry-- > 0);
|
||||
|
||||
#ifdef HX_CODE_OVERLAY
|
||||
#if defined(HX83102D)
|
||||
/* ovl_idx[0] - sorting */
|
||||
/* ovl_idx[1] - gesture */
|
||||
/* ovl_idx[2] - border */
|
||||
|
||||
ovl_idx_t = ovl_idx[0];
|
||||
send_data[0] = ovl_sorting_reply;
|
||||
|
||||
if (private_ts->in_self_test == 0) {
|
||||
#if defined(HX_SMART_WAKEUP)
|
||||
if (private_ts->suspended && private_ts->SMWP_enable) {
|
||||
ovl_idx_t = ovl_idx[1];
|
||||
send_data[0] = ovl_gesture_reply;
|
||||
} else {
|
||||
ovl_idx_t = ovl_idx[2];
|
||||
send_data[0] = ovl_border_reply;
|
||||
}
|
||||
#else
|
||||
ovl_idx_t = ovl_idx[2];
|
||||
send_data[0] = ovl_border_reply;
|
||||
#endif
|
||||
#else
|
||||
/*do nothing when self testing ??*/
|
||||
if (private_ts->in_self_test == 0) {
|
||||
#ifdef HX_SMART_WAKEUP
|
||||
|
|
@ -2800,6 +2984,7 @@ int himax_zf_part_info(const struct firmware *fw_entry)
|
|||
ovl_sidx = ovl_sidx + 2;
|
||||
#else
|
||||
ovl_sidx = ovl_sidx + 2;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
if (himax_sram_write_crc_check(fw_entry, zf_info_arr[ovl_sidx].sram_addr, zf_info_arr[ovl_sidx].fw_addr, zf_info_arr[ovl_sidx].write_size) != 0)
|
||||
|
|
@ -2812,6 +2997,35 @@ int himax_zf_part_info(const struct firmware *fw_entry)
|
|||
g_core_fp.fp_resend_cmd_func(private_ts->suspended);
|
||||
#endif
|
||||
|
||||
#if defined(HX83102D)
|
||||
}
|
||||
I("%s: prepare upgrade overlay section = %d\n",
|
||||
__func__, ovl_idx_t);
|
||||
|
||||
if (zf_info_arr[ovl_idx_t].write_size == 0) {
|
||||
send_data[0] = ovl_fault;
|
||||
E("%s, WRONG overlay section, plese check FW!\n",
|
||||
__func__);
|
||||
} else {
|
||||
if (himax_sram_write_crc_check(fw_entry,
|
||||
zf_info_arr[ovl_idx_t].sram_addr,
|
||||
zf_info_arr[ovl_idx_t].fw_addr,
|
||||
zf_info_arr[ovl_idx_t].write_size) != 0) {
|
||||
send_data[0] = ovl_fault;
|
||||
E("%s, Overlay HW CRC FAIL\n", __func__);
|
||||
} else {
|
||||
I("%s, Overlay HW CRC PASS\n", __func__);
|
||||
}
|
||||
}
|
||||
|
||||
retry = 0;
|
||||
|
||||
do {
|
||||
g_core_fp.fp_register_write(tmp_addr, DATA_LEN_4, send_data, 0);
|
||||
g_core_fp.fp_register_read(tmp_addr, DATA_LEN_4, recv_data, 0);
|
||||
retry++;
|
||||
} while ((send_data[3] != recv_data[3] || send_data[2] != recv_data[2] || send_data[1] != recv_data[1] || send_data[0] != recv_data[0]) && retry < HIMAX_REG_RETRY_TIMES);
|
||||
#else
|
||||
#if defined(HX_SMART_WAKEUP)
|
||||
/* write overlay handshaking password */
|
||||
if (private_ts->SMWP_enable) {
|
||||
|
|
@ -2831,7 +3045,7 @@ int himax_zf_part_info(const struct firmware *fw_entry)
|
|||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
} else {
|
||||
g_core_fp.fp_clean_sram_0f(zf_info_arr[0].sram_addr, zf_info_arr[0].write_size, 2);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1858,7 +1858,7 @@ static int himax_chip_self_test(void)
|
|||
uint8_t tmp_addr[DATA_LEN_4] = {0x94, 0x72, 0x00, 0x10};
|
||||
uint8_t tmp_data[DATA_LEN_4] = {0x01, 0x00, 0x00, 0x00};
|
||||
|
||||
#ifdef HIMAX_V2_MULTI_BIN
|
||||
#if defined(HIMAX_V2_MULTI_BIN)||defined(HX_CODE_OVERLAY)
|
||||
uint8_t normalfw[32] = "Himax_firmware.bin";
|
||||
uint8_t mpapfw[32] = "Himax_mpfw.bin";
|
||||
if (private_ts->pdata->panel_supplier) {
|
||||
|
|
@ -1871,7 +1871,7 @@ static int himax_chip_self_test(void)
|
|||
|
||||
private_ts->suspend_resume_done = 0;
|
||||
|
||||
#ifdef HIMAX_V2_MULTI_BIN
|
||||
#if defined(HIMAX_V2_MULTI_BIN)||defined(HX_CODE_OVERLAY)
|
||||
g_core_fp.fp_0f_op_file_dirly(mpapfw);
|
||||
g_core_fp.fp_reload_disable(0);
|
||||
g_core_fp.fp_sense_on(0x00);
|
||||
|
|
@ -2176,7 +2176,7 @@ static int himax_chip_self_test(void)
|
|||
usleep_range(1000, 1001);
|
||||
#endif
|
||||
|
||||
#ifdef HIMAX_V2_MULTI_BIN
|
||||
#if defined(HIMAX_V2_MULTI_BIN)||defined(HX_CODE_OVERLAY)
|
||||
private_ts->in_self_test = 0;
|
||||
g_core_fp.fp_0f_op_file_dirly(normalfw);
|
||||
hx_turn_on_mp_func(0);
|
||||
|
|
|
|||
|
|
@ -107,6 +107,13 @@ static unsigned char *kp_IC_CHECKSUM;
|
|||
static u8 *kp_HX_ESD_RESET_ACTIVATE;
|
||||
#endif
|
||||
|
||||
#if defined(HX_ZERO_FLASH) && defined(HX_CODE_OVERLAY)
|
||||
#if defined(CONFIG_TOUCHSCREEN_HIMAX_INCELL)
|
||||
extern uint8_t *ovl_idx;
|
||||
static uint8_t **kp_ovl_idx;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
static unsigned long *kp_FW_VER_MAJ_FLASH_ADDR;
|
||||
static unsigned long *kp_FW_VER_MIN_FLASH_ADDR;
|
||||
static unsigned long *kp_CFG_VER_MAJ_FLASH_ADDR;
|
||||
|
|
@ -254,6 +261,12 @@ static int32_t himax_ic_setup_external_symbols(void)
|
|||
|
||||
#ifdef HX_ESD_RECOVERY
|
||||
assert_on_symbol(HX_ESD_RESET_ACTIVATE);
|
||||
#endif
|
||||
|
||||
#if defined(HX_ZERO_FLASH) && defined(HX_CODE_OVERLAY)
|
||||
#if defined(CONFIG_TOUCHSCREEN_HIMAX_INCELL)
|
||||
assert_on_symbol(ovl_idx);
|
||||
#endif
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,17 @@
|
|||
DLKM_DIR := motorola/kernel/modules
|
||||
LOCAL_PATH := $(call my-dir)
|
||||
|
||||
ifeq ($(DLKM_INSTALL_TO_VENDOR_OUT),true)
|
||||
HIMAX_MMI_IC_MODULE_PATH := $(TARGET_OUT_VENDOR)/lib/modules/
|
||||
else
|
||||
HIMAX_MMI_IC_MODULE_PATH := $(KERNEL_MODULES_OUT)
|
||||
endif
|
||||
|
||||
KERNEL_CFLAGS += CONFIG_INPUT_HIMAX_V2_MMI_IC_NAME_D=hx83102d
|
||||
|
||||
include $(CLEAR_VARS)
|
||||
LOCAL_MODULE := himax_v2_mmi_hx83102d.ko
|
||||
LOCAL_MODULE_TAGS := optional
|
||||
LOCAL_MODULE_PATH := $(HIMAX_MMI_IC_MODULE_PATH)
|
||||
LOCAL_REQUIRED_MODULES := himax_v2_mmi.ko
|
||||
include $(DLKM_DIR)/AndroidKernelModule.mk
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
# add -Wall to try to catch everything we can.
|
||||
EXTRA_CFLAGS += -Wall
|
||||
EXTRA_CFLAGS += -I$(TOP)/motorola/kernel/modules/include \
|
||||
-I$(TOP)/motorola/kernel/modules/drivers/input/touchscreen/himax_v2_mmi \
|
||||
-I$(TOP)/motorola/kernel/modules/drivers/input/touchscreen/himax_v2_mmi/support_ic \
|
||||
-I$(TOP)/motorola/kernel/modules/drivers/input/touchscreen/himax_v2_mmi/support_ic/himax_v2_mmi_hx83102d
|
||||
EXTRA_CFLAGS += -DCONFIG_TOUCHSCREEN_HIMAX_DEBUG \
|
||||
-DCONFIG_TOUCHSCREEN_HIMAX_INSPECT
|
||||
|
||||
EXTRA_CFLAGS += -DCONFIG_TOUCHSCREEN_HIMAX_INCELL
|
||||
EXTRA_CFLAGS += -DCONFIG_HMX_DB
|
||||
|
||||
ifneq ($(filter hx83102d,$(CONFIG_INPUT_HIMAX_V2_MMI_IC_NAME_D)),)
|
||||
EXTRA_CFLAGS += -D__HIMAX_HX83102D_MOD__
|
||||
EXTRA_CFLAGS += -DHX_ZERO_FLASH
|
||||
EXTRA_CFLAGS += -DHX_CODE_OVERLAY
|
||||
endif
|
||||
|
||||
obj-m := himax_v2_mmi_hx83102d.o
|
||||
himax_v2_mmi_hx83102d-objs += himax_ic_HX83102d.o
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
KERNEL_SRC ?= /lib/modules/$(shell uname -r)/build
|
||||
|
||||
all:
|
||||
$(MAKE) -C $(KERNEL_SRC) M=$(shell pwd) modules $(KBUILD_OPTIONS)
|
||||
|
||||
modules_install:
|
||||
$(MAKE) INSTALL_MOD_STRIP=1 -C $(KERNEL_SRC) M=$(shell pwd) modules_install
|
||||
|
||||
clean:
|
||||
$(MAKE) -C $(KERNEL_SRC) M=$(PWD) clean
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,65 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Himax Android Driver Sample Code for HX83102 chipset
|
||||
*
|
||||
* Copyright (C) 2019 Himax Corporation.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "himax_platform.h"
|
||||
#include "himax_common.h"
|
||||
#include "himax_ic_core.h"
|
||||
#include <linux/slab.h>
|
||||
|
||||
#define hx83102ab_fw_addr_sorting_mode_en 0x100007FC
|
||||
#define hx83102ab_fw_addr_selftest_addr_en 0x100007F8
|
||||
#define hx83102ab_data_adc_cfg_1 0x10007B00
|
||||
#define hx83102a_data_df_rx 48
|
||||
#define hx83102a_data_df_tx 24
|
||||
#define hx83102a_data_df_x_res 2160
|
||||
#define hx83102a_data_df_y_res 3840
|
||||
#define hx83102b_data_df_x_res 720
|
||||
#define hx83102b_data_df_y_res 1280
|
||||
|
||||
#define hx83102d_fw_addr_raw_out_sel 0x800204f4
|
||||
#define hx83102d_zf_data_adc_cfg_1 0x10007B00
|
||||
#define hx83102d_zf_data_adc_cfg_2 0x10006A00
|
||||
#define hx83102d_zf_data_adc_cfg_3 0x10007500
|
||||
#define hx83102d_zf_data_bor_prevent_info 0x10007268
|
||||
#define hx83102d_zf_data_notch_info 0x10007300
|
||||
#define hx83102d_zf_func_info_en 0x10007FD0
|
||||
#define hx83102d_zf_po_sub_func 0x10005A00
|
||||
#define hx83102d_zf_data_sram_start_addr 0x20000000
|
||||
#define hx83102d_data_df_x_res 720
|
||||
#define hx83102d_data_df_y_res 1280
|
||||
#define hx83102d_adr_osc_en 0x9000009C
|
||||
#define hx83102d_adr_osc_pw 0x90000280
|
||||
|
||||
#define hx83102e_fw_addr_raw_out_sel 0x100072EC
|
||||
#define hx83102e_data_df_rx 48
|
||||
#define hx83102e_data_df_tx 30
|
||||
#define hx83102e_data_df_x_res 1200
|
||||
#define hx83102e_data_df_y_res 1920
|
||||
|
||||
#if defined(HX_AUTO_UPDATE_FW) || defined(HX_ZERO_FLASH)
|
||||
#ifdef HX_EN_DYNAMIC_NAME
|
||||
#define hx83102_ic_b9_en 0x300B9000
|
||||
#define hx83102_ic_fw 0x300E8006
|
||||
|
||||
#define hx83102b_ic_osc_en 0x900880A0
|
||||
#define hx83102d_ic_osc_en 0x9000009C
|
||||
#define hx83102d_ic_osc_pw 0x90000280
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef HX_ESD_RECOVERY
|
||||
extern u8 HX_ESD_RESET_ACTIVATE;
|
||||
#endif
|
||||
|
||||
Loading…
Reference in a new issue