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asoc: bolero: Update PCM_RATE based delay for amic

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The PCM_RATE bit field in LPASS_TX_CDC_TXn_TX_PATH_CTL
ranges from 0 to 6.
In the current implementation of tx-macro, the value
read is mapped directly to the sample rate instead of
the indices. Change is to correct this.
Add the delay based on pcm_rate in va-macro as well.

Change-Id: I6cb7e58e71f2a25356608611f1dfed83171706f6
Signed-off-by: Soumya Managoli <smanag@codeaurora.org>
This commit is contained in:
Soumya Managoli 2021-02-10 17:42:05 +05:30
commit 9908997a77
2 changed files with 38 additions and 11 deletions
Download patch file Download diff file Expand all files Collapse all files

18
asoc/codecs/bolero/tx-macro.c
View file

@ -180,7 +180,7 @@ struct tx_macro_priv {
int bcs_ch;
bool bcs_clk_en;
bool hs_slow_insert_complete;
int amic_sample_rate;
int pcm_rate[NUM_DECIMATORS];
bool lpi_enable;
bool register_event_listener;
u16 current_clk_id;
@ -547,23 +547,23 @@ static void tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work)
snd_soc_component_update_bits(component, hpf_gate_reg,
0x03, 0x02);
/* Add delay between toggle hpf gate based on sample rate */
switch(tx_priv->amic_sample_rate) {
case 8000:
switch (tx_priv->pcm_rate[hpf_work->decimator]) {
case 0:
usleep_range(125, 130);
break;
case 16000:
case 1:
usleep_range(62, 65);
break;
case 32000:
case 3:
usleep_range(31, 32);
break;
case 48000:
case 4:
usleep_range(20, 21);
break;
case 96000:
case 5:
usleep_range(10, 11);
break;
case 192000:
case 6:
usleep_range(5, 6);
break;
default:
@ -1055,7 +1055,7 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
tx_fs_reg = BOLERO_CDC_TX0_TX_PATH_CTL +
TX_MACRO_TX_PATH_OFFSET * decimator;
tx_priv->amic_sample_rate = (snd_soc_component_read32(component,
tx_priv->pcm_rate[decimator] = (snd_soc_component_read32(component,
tx_fs_reg) & 0x0F);
if(!is_smic_enabled(component, decimator))
tx_macro_enable_dmic(w, kcontrol, event, adc_mux0_reg);

31
asoc/codecs/bolero/va-macro.c
View file

@ -183,6 +183,7 @@ struct va_macro_priv {
bool clk_div_switch;
int dec_mode[VA_MACRO_NUM_DECIMATORS];
u16 current_clk_id;
int pcm_rate[VA_MACRO_NUM_DECIMATORS];
};
static bool va_macro_get_data(struct snd_soc_component *component,
@ -901,8 +902,29 @@ static void va_macro_tx_hpf_corner_freq_callback(struct work_struct *work)
hpf_cut_off_freq << 5);
snd_soc_component_update_bits(component, hpf_gate_reg,
0x03, 0x02);
/* Minimum 1 clk cycle delay is required as per HW spec */
usleep_range(1000, 1010);
/* Add delay between toggle hpf gate based on sample rate */
switch (va_priv->pcm_rate[hpf_work->decimator]) {
case 0:
usleep_range(125, 130);
break;
case 1:
usleep_range(62, 65);
break;
case 3:
usleep_range(31, 32);
break;
case 4:
usleep_range(20, 21);
break;
case 5:
usleep_range(10, 11);
break;
case 6:
usleep_range(5, 6);
break;
default:
usleep_range(125, 130);
}
snd_soc_component_update_bits(component, hpf_gate_reg,
0x03, 0x01);
} else {
@ -1147,6 +1169,7 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w,
u8 hpf_cut_off_freq;
u16 adc_mux_reg = 0;
u16 adc_mux0_reg = 0;
u16 tx_fs_reg = 0;
struct device *va_dev = NULL;
struct va_macro_priv *va_priv = NULL;
int hpf_delay = BOLERO_CDC_VA_TX_DMIC_HPF_DELAY_MS;
@ -1172,6 +1195,10 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w,
VA_MACRO_ADC_MUX_CFG_OFFSET * decimator;
adc_mux0_reg = BOLERO_CDC_VA_INP_MUX_ADC_MUX0_CFG0 +
VA_MACRO_ADC_MUX_CFG_OFFSET * decimator;
tx_fs_reg = BOLERO_CDC_VA_TX0_TX_PATH_CTL +
VA_MACRO_TX_PATH_OFFSET * decimator;
va_priv->pcm_rate[decimator] = (snd_soc_component_read32(component,
tx_fs_reg) & 0x0F);
if(!is_smic_enabled(component, decimator))
va_macro_enable_dmic(w, kcontrol, event, adc_mux0_reg);