mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 18:51:56 -04:00
Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (23 commits) sh: Make intc messages consistent via pr_fmt. sh: make sure static declaration on ms7724se sh: make sure static declaration on mach-migor sh: make sure static declaration on mach-ecovec24 sh: make sure static declaration on mach-ap325rxa clocksource: sh_cmt: compute mult and shift before registration clocksource: sh_tmu: compute mult and shift before registration sh: PIO disabling for x3proto and urquell. sh: mach-sdk7786: conditionally disable PIO support. sh: support for platforms without PIO. usb: r8a66597-hcd pio to mmio accessor conversion. usb: gadget: r8a66597-udc pio to mmio accessor conversion. usb: gadget: m66592-udc pio to mmio accessor conversion. sh: add romImage MMCIF boot for sh7724 and Ecovec V2 sh: add boot code to MMCIF driver header sh: prepare MMCIF driver header file sh: allow romImage data between head.S and the zero page sh: Add support MMCIF for ecovec sh: remove duplicated #include input: serio: disable i8042 for non-cayman sh platforms. ...
This commit is contained in:
Linus Torvalds
commit
999fd1ab34
36 changed files with 642 additions and 204 deletions
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@ -412,18 +412,10 @@ static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
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static int sh_cmt_clocksource_enable(struct clocksource *cs)
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{
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struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
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int ret;
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p->total_cycles = 0;
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ret = sh_cmt_start(p, FLAG_CLOCKSOURCE);
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if (ret)
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return ret;
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/* TODO: calculate good shift from rate and counter bit width */
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cs->shift = 0;
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cs->mult = clocksource_hz2mult(p->rate, cs->shift);
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return 0;
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return sh_cmt_start(p, FLAG_CLOCKSOURCE);
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}
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static void sh_cmt_clocksource_disable(struct clocksource *cs)
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@ -450,8 +442,20 @@ static int sh_cmt_register_clocksource(struct sh_cmt_priv *p,
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cs->resume = sh_cmt_clocksource_resume;
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cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
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cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
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/* clk_get_rate() needs an enabled clock */
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clk_enable(p->clk);
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p->rate = clk_get_rate(p->clk) / (p->width == 16) ? 512 : 8;
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clk_disable(p->clk);
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/* TODO: calculate good shift from rate and counter bit width */
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cs->shift = 10;
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cs->mult = clocksource_hz2mult(p->rate, cs->shift);
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dev_info(&p->pdev->dev, "used as clock source\n");
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clocksource_register(cs);
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return 0;
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}
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@ -199,16 +199,8 @@ static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
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static int sh_tmu_clocksource_enable(struct clocksource *cs)
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{
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struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
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int ret;
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ret = sh_tmu_enable(p);
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if (ret)
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return ret;
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/* TODO: calculate good shift from rate and counter bit width */
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cs->shift = 10;
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cs->mult = clocksource_hz2mult(p->rate, cs->shift);
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return 0;
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return sh_tmu_enable(p);
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}
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static void sh_tmu_clocksource_disable(struct clocksource *cs)
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@ -228,6 +220,16 @@ static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
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cs->disable = sh_tmu_clocksource_disable;
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cs->mask = CLOCKSOURCE_MASK(32);
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cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
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/* clk_get_rate() needs an enabled clock */
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clk_enable(p->clk);
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/* channel will be configured at parent clock / 4 */
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p->rate = clk_get_rate(p->clk) / 4;
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clk_disable(p->clk);
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/* TODO: calculate good shift from rate and counter bit width */
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cs->shift = 10;
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cs->mult = clocksource_hz2mult(p->rate, cs->shift);
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dev_info(&p->pdev->dev, "used as clock source\n");
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clocksource_register(cs);
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return 0;
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@ -21,7 +21,8 @@ if SERIO
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config SERIO_I8042
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tristate "i8042 PC Keyboard controller" if EMBEDDED || !X86
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default y
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depends on !PARISC && (!ARM || ARCH_SHARK || FOOTBRIDGE_HOST) && !M68K && !BLACKFIN
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depends on !PARISC && (!ARM || ARCH_SHARK || FOOTBRIDGE_HOST) && \
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(!SUPERH || SH_CAYMAN) && !M68K && !BLACKFIN
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help
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i8042 is the chip over which the standard AT keyboard and PS/2
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mouse are connected to the computer. If you use these devices,
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@ -30,25 +30,6 @@
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#define DRIVER_NAME "sh_mmcif"
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#define DRIVER_VERSION "2010-04-28"
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#define MMCIF_CE_CMD_SET 0x00000000
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#define MMCIF_CE_ARG 0x00000008
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#define MMCIF_CE_ARG_CMD12 0x0000000C
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#define MMCIF_CE_CMD_CTRL 0x00000010
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#define MMCIF_CE_BLOCK_SET 0x00000014
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#define MMCIF_CE_CLK_CTRL 0x00000018
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#define MMCIF_CE_BUF_ACC 0x0000001C
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#define MMCIF_CE_RESP3 0x00000020
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#define MMCIF_CE_RESP2 0x00000024
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#define MMCIF_CE_RESP1 0x00000028
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#define MMCIF_CE_RESP0 0x0000002C
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#define MMCIF_CE_RESP_CMD12 0x00000030
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#define MMCIF_CE_DATA 0x00000034
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#define MMCIF_CE_INT 0x00000040
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#define MMCIF_CE_INT_MASK 0x00000044
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#define MMCIF_CE_HOST_STS1 0x00000048
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#define MMCIF_CE_HOST_STS2 0x0000004C
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#define MMCIF_CE_VERSION 0x0000007C
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/* CE_CMD_SET */
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#define CMD_MASK 0x3f000000
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#define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
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@ -207,27 +188,17 @@ struct sh_mmcif_host {
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wait_queue_head_t intr_wait;
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};
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static inline u32 sh_mmcif_readl(struct sh_mmcif_host *host, unsigned int reg)
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{
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return readl(host->addr + reg);
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}
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static inline void sh_mmcif_writel(struct sh_mmcif_host *host,
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unsigned int reg, u32 val)
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{
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writel(val, host->addr + reg);
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}
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static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
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unsigned int reg, u32 val)
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{
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writel(val | sh_mmcif_readl(host, reg), host->addr + reg);
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writel(val | readl(host->addr + reg), host->addr + reg);
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}
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static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
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unsigned int reg, u32 val)
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{
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writel(~val & sh_mmcif_readl(host, reg), host->addr + reg);
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writel(~val & readl(host->addr + reg), host->addr + reg);
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}
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@ -253,10 +224,10 @@ static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
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{
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u32 tmp;
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tmp = 0x010f0000 & sh_mmcif_readl(host, MMCIF_CE_CLK_CTRL);
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tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
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sh_mmcif_writel(host, MMCIF_CE_VERSION, SOFT_RST_ON);
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sh_mmcif_writel(host, MMCIF_CE_VERSION, SOFT_RST_OFF);
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sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
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sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
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sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
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SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
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/* byte swap on */
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@ -271,12 +242,10 @@ static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
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host->sd_error = 0;
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host->wait_int = 0;
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state1 = sh_mmcif_readl(host, MMCIF_CE_HOST_STS1);
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state2 = sh_mmcif_readl(host, MMCIF_CE_HOST_STS2);
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pr_debug("%s: ERR HOST_STS1 = %08x\n", \
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DRIVER_NAME, sh_mmcif_readl(host, MMCIF_CE_HOST_STS1));
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pr_debug("%s: ERR HOST_STS2 = %08x\n", \
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DRIVER_NAME, sh_mmcif_readl(host, MMCIF_CE_HOST_STS2));
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state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
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state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
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pr_debug("%s: ERR HOST_STS1 = %08x\n", DRIVER_NAME, state1);
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pr_debug("%s: ERR HOST_STS2 = %08x\n", DRIVER_NAME, state2);
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if (state1 & STS1_CMDSEQ) {
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sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
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@ -288,7 +257,7 @@ static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
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"command sequence timeout err\n");
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return -EIO;
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}
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if (!(sh_mmcif_readl(host, MMCIF_CE_HOST_STS1)
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if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
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& STS1_CMDSEQ))
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break;
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mdelay(1);
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@ -330,9 +299,9 @@ static int sh_mmcif_single_read(struct sh_mmcif_host *host,
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host->wait_int = 0;
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blocksize = (BLOCK_SIZE_MASK &
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sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET)) + 3;
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sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
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for (i = 0; i < blocksize / 4; i++)
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*p++ = sh_mmcif_readl(host, MMCIF_CE_DATA);
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*p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
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/* buffer read end */
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sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
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@ -353,7 +322,8 @@ static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
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long time;
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u32 blocksize, i, j, sec, *p;
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blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET);
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blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
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MMCIF_CE_BLOCK_SET);
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for (j = 0; j < data->sg_len; j++) {
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p = sg_virt(data->sg);
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host->wait_int = 0;
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@ -370,7 +340,8 @@ static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
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host->wait_int = 0;
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for (i = 0; i < blocksize / 4; i++)
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*p++ = sh_mmcif_readl(host, MMCIF_CE_DATA);
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*p++ = sh_mmcif_readl(host->addr,
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MMCIF_CE_DATA);
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}
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if (j < data->sg_len - 1)
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data->sg++;
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@ -397,9 +368,9 @@ static int sh_mmcif_single_write(struct sh_mmcif_host *host,
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host->wait_int = 0;
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blocksize = (BLOCK_SIZE_MASK &
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sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET)) + 3;
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sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
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for (i = 0; i < blocksize / 4; i++)
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sh_mmcif_writel(host, MMCIF_CE_DATA, *p++);
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sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
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/* buffer write end */
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sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
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@ -421,7 +392,8 @@ static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
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long time;
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u32 i, sec, j, blocksize, *p;
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blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET);
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blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
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MMCIF_CE_BLOCK_SET);
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for (j = 0; j < data->sg_len; j++) {
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p = sg_virt(data->sg);
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@ -439,7 +411,8 @@ static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
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host->wait_int = 0;
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for (i = 0; i < blocksize / 4; i++)
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sh_mmcif_writel(host, MMCIF_CE_DATA, *p++);
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sh_mmcif_writel(host->addr,
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MMCIF_CE_DATA, *p++);
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}
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if (j < data->sg_len - 1)
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data->sg++;
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@ -451,18 +424,18 @@ static void sh_mmcif_get_response(struct sh_mmcif_host *host,
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struct mmc_command *cmd)
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{
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if (cmd->flags & MMC_RSP_136) {
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cmd->resp[0] = sh_mmcif_readl(host, MMCIF_CE_RESP3);
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cmd->resp[1] = sh_mmcif_readl(host, MMCIF_CE_RESP2);
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cmd->resp[2] = sh_mmcif_readl(host, MMCIF_CE_RESP1);
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cmd->resp[3] = sh_mmcif_readl(host, MMCIF_CE_RESP0);
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cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
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cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
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cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
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cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
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} else
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cmd->resp[0] = sh_mmcif_readl(host, MMCIF_CE_RESP0);
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cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
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}
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static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
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struct mmc_command *cmd)
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{
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cmd->resp[0] = sh_mmcif_readl(host, MMCIF_CE_RESP_CMD12);
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cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
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}
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|
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static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
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@ -596,18 +569,19 @@ static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
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MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
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|
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if (host->data) {
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sh_mmcif_writel(host, MMCIF_CE_BLOCK_SET, 0);
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sh_mmcif_writel(host, MMCIF_CE_BLOCK_SET, mrq->data->blksz);
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sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
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sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
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mrq->data->blksz);
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}
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opc = sh_mmcif_set_cmd(host, mrq, cmd, opc);
|
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|
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sh_mmcif_writel(host, MMCIF_CE_INT, 0xD80430C0);
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sh_mmcif_writel(host, MMCIF_CE_INT_MASK, mask);
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sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
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sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
|
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/* set arg */
|
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sh_mmcif_writel(host, MMCIF_CE_ARG, cmd->arg);
|
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sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
|
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host->wait_int = 0;
|
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/* set cmd */
|
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sh_mmcif_writel(host, MMCIF_CE_CMD_SET, opc);
|
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sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
|
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|
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time = wait_event_interruptible_timeout(host->intr_wait,
|
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host->wait_int == 1 || host->sd_error == 1, host->timeout);
|
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|
|
@ -752,43 +726,44 @@ static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
|
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u32 state = 0;
|
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int err = 0;
|
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|
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state = sh_mmcif_readl(host, MMCIF_CE_INT);
|
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state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
|
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|
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if (state & INT_RBSYE) {
|
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sh_mmcif_writel(host, MMCIF_CE_INT, ~(INT_RBSYE | INT_CRSPE));
|
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sh_mmcif_writel(host->addr, MMCIF_CE_INT,
|
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~(INT_RBSYE | INT_CRSPE));
|
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sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
|
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} else if (state & INT_CRSPE) {
|
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sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_CRSPE);
|
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sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
|
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sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
|
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} else if (state & INT_BUFREN) {
|
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sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_BUFREN);
|
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sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
|
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sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
|
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} else if (state & INT_BUFWEN) {
|
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sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_BUFWEN);
|
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sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
|
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sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
|
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} else if (state & INT_CMD12DRE) {
|
||||
sh_mmcif_writel(host, MMCIF_CE_INT,
|
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sh_mmcif_writel(host->addr, MMCIF_CE_INT,
|
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~(INT_CMD12DRE | INT_CMD12RBE |
|
||||
INT_CMD12CRE | INT_BUFRE));
|
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sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
|
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} else if (state & INT_BUFRE) {
|
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sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_BUFRE);
|
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sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
|
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sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
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} else if (state & INT_DTRANE) {
|
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sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_DTRANE);
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE);
|
||||
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
|
||||
} else if (state & INT_CMD12RBE) {
|
||||
sh_mmcif_writel(host, MMCIF_CE_INT,
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_INT,
|
||||
~(INT_CMD12RBE | INT_CMD12CRE));
|
||||
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
|
||||
} else if (state & INT_ERR_STS) {
|
||||
/* err interrupts */
|
||||
sh_mmcif_writel(host, MMCIF_CE_INT, ~state);
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
|
||||
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
|
||||
err = 1;
|
||||
} else {
|
||||
pr_debug("%s: Not support int\n", DRIVER_NAME);
|
||||
sh_mmcif_writel(host, MMCIF_CE_INT, ~state);
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
|
||||
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
|
||||
err = 1;
|
||||
}
|
||||
|
|
@ -894,12 +869,12 @@ static int __devinit sh_mmcif_probe(struct platform_device *pdev)
|
|||
goto clean_up2;
|
||||
}
|
||||
|
||||
sh_mmcif_writel(host, MMCIF_CE_INT_MASK, MASK_ALL);
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
|
||||
sh_mmcif_detect(host->mmc);
|
||||
|
||||
pr_info("%s: driver version %s\n", DRIVER_NAME, DRIVER_VERSION);
|
||||
pr_debug("%s: chip ver H'%04x\n", DRIVER_NAME,
|
||||
sh_mmcif_readl(host, MMCIF_CE_VERSION) & 0x0000ffff);
|
||||
sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
|
||||
return ret;
|
||||
|
||||
clean_up2:
|
||||
|
|
@ -917,7 +892,7 @@ static int __devexit sh_mmcif_remove(struct platform_device *pdev)
|
|||
struct sh_mmcif_host *host = platform_get_drvdata(pdev);
|
||||
int irq[2];
|
||||
|
||||
sh_mmcif_writel(host, MMCIF_CE_INT_MASK, MASK_ALL);
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
|
||||
|
||||
irq[0] = platform_get_irq(pdev, 0);
|
||||
irq[1] = platform_get_irq(pdev, 1);
|
||||
|
|
|
|||
|
|
@ -16,6 +16,8 @@
|
|||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/module.h>
|
||||
|
|
@ -855,8 +857,8 @@ static void __init intc_register_irq(struct intc_desc *desc,
|
|||
primary = 1;
|
||||
|
||||
if (!data[0] && !data[1])
|
||||
pr_warning("intc: missing unique irq mask for "
|
||||
"irq %d (vect 0x%04x)\n", irq, irq2evt(irq));
|
||||
pr_warning("missing unique irq mask for irq %d (vect 0x%04x)\n",
|
||||
irq, irq2evt(irq));
|
||||
|
||||
data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
|
||||
data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
|
||||
|
|
@ -952,7 +954,7 @@ int __init register_intc_controller(struct intc_desc *desc)
|
|||
struct intc_desc_int *d;
|
||||
struct resource *res;
|
||||
|
||||
pr_info("intc: Registered controller '%s' with %u IRQs\n",
|
||||
pr_info("Registered controller '%s' with %u IRQs\n",
|
||||
desc->name, hw->nr_vectors);
|
||||
|
||||
d = kzalloc(sizeof(*d), GFP_NOWAIT);
|
||||
|
|
@ -1148,7 +1150,7 @@ int register_intc_userimask(unsigned long addr)
|
|||
if (unlikely(!uimask))
|
||||
return -ENOMEM;
|
||||
|
||||
pr_info("intc: userimask support registered for levels 0 -> %d\n",
|
||||
pr_info("userimask support registered for levels 0 -> %d\n",
|
||||
default_prio_level - 1);
|
||||
|
||||
return 0;
|
||||
|
|
@ -1286,7 +1288,7 @@ static int __init register_intc_sysdevs(void)
|
|||
}
|
||||
|
||||
if (error)
|
||||
pr_err("intc: sysdev registration error\n");
|
||||
pr_err("sysdev registration error\n");
|
||||
|
||||
return error;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -537,35 +537,35 @@ struct m66592 {
|
|||
/*-------------------------------------------------------------------------*/
|
||||
static inline u16 m66592_read(struct m66592 *m66592, unsigned long offset)
|
||||
{
|
||||
return inw((unsigned long)m66592->reg + offset);
|
||||
return ioread16(m66592->reg + offset);
|
||||
}
|
||||
|
||||
static inline void m66592_read_fifo(struct m66592 *m66592,
|
||||
unsigned long offset,
|
||||
void *buf, unsigned long len)
|
||||
{
|
||||
unsigned long fifoaddr = (unsigned long)m66592->reg + offset;
|
||||
void __iomem *fifoaddr = m66592->reg + offset;
|
||||
|
||||
if (m66592->pdata->on_chip) {
|
||||
len = (len + 3) / 4;
|
||||
insl(fifoaddr, buf, len);
|
||||
ioread32_rep(fifoaddr, buf, len);
|
||||
} else {
|
||||
len = (len + 1) / 2;
|
||||
insw(fifoaddr, buf, len);
|
||||
ioread16_rep(fifoaddr, buf, len);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void m66592_write(struct m66592 *m66592, u16 val,
|
||||
unsigned long offset)
|
||||
{
|
||||
outw(val, (unsigned long)m66592->reg + offset);
|
||||
iowrite16(val, m66592->reg + offset);
|
||||
}
|
||||
|
||||
static inline void m66592_write_fifo(struct m66592 *m66592,
|
||||
unsigned long offset,
|
||||
void *buf, unsigned long len)
|
||||
{
|
||||
unsigned long fifoaddr = (unsigned long)m66592->reg + offset;
|
||||
void __iomem *fifoaddr = m66592->reg + offset;
|
||||
|
||||
if (m66592->pdata->on_chip) {
|
||||
unsigned long count;
|
||||
|
|
@ -573,25 +573,25 @@ static inline void m66592_write_fifo(struct m66592 *m66592,
|
|||
int i;
|
||||
|
||||
count = len / 4;
|
||||
outsl(fifoaddr, buf, count);
|
||||
iowrite32_rep(fifoaddr, buf, count);
|
||||
|
||||
if (len & 0x00000003) {
|
||||
pb = buf + count * 4;
|
||||
for (i = 0; i < (len & 0x00000003); i++) {
|
||||
if (m66592_read(m66592, M66592_CFBCFG)) /* le */
|
||||
outb(pb[i], fifoaddr + (3 - i));
|
||||
iowrite8(pb[i], fifoaddr + (3 - i));
|
||||
else
|
||||
outb(pb[i], fifoaddr + i);
|
||||
iowrite8(pb[i], fifoaddr + i);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
unsigned long odd = len & 0x0001;
|
||||
|
||||
len = len / 2;
|
||||
outsw(fifoaddr, buf, len);
|
||||
iowrite16_rep(fifoaddr, buf, len);
|
||||
if (odd) {
|
||||
unsigned char *p = buf + len*2;
|
||||
outb(*p, fifoaddr);
|
||||
iowrite8(*p, fifoaddr);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1500,7 +1500,7 @@ static int __exit r8a66597_remove(struct platform_device *pdev)
|
|||
struct r8a66597 *r8a66597 = dev_get_drvdata(&pdev->dev);
|
||||
|
||||
del_timer_sync(&r8a66597->timer);
|
||||
iounmap((void *)r8a66597->reg);
|
||||
iounmap(r8a66597->reg);
|
||||
free_irq(platform_get_irq(pdev, 0), r8a66597);
|
||||
r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
|
||||
#ifdef CONFIG_HAVE_CLK
|
||||
|
|
@ -1578,7 +1578,7 @@ static int __init r8a66597_probe(struct platform_device *pdev)
|
|||
init_timer(&r8a66597->timer);
|
||||
r8a66597->timer.function = r8a66597_timer;
|
||||
r8a66597->timer.data = (unsigned long)r8a66597;
|
||||
r8a66597->reg = (unsigned long)reg;
|
||||
r8a66597->reg = reg;
|
||||
|
||||
#ifdef CONFIG_HAVE_CLK
|
||||
if (r8a66597->pdata->on_chip) {
|
||||
|
|
|
|||
|
|
@ -91,7 +91,7 @@ struct r8a66597_ep {
|
|||
|
||||
struct r8a66597 {
|
||||
spinlock_t lock;
|
||||
unsigned long reg;
|
||||
void __iomem *reg;
|
||||
|
||||
#ifdef CONFIG_HAVE_CLK
|
||||
struct clk *clk;
|
||||
|
|
@ -127,7 +127,7 @@ struct r8a66597 {
|
|||
|
||||
static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
|
||||
{
|
||||
return inw(r8a66597->reg + offset);
|
||||
return ioread16(r8a66597->reg + offset);
|
||||
}
|
||||
|
||||
static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
|
||||
|
|
@ -135,7 +135,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
|
|||
unsigned char *buf,
|
||||
int len)
|
||||
{
|
||||
unsigned long fifoaddr = r8a66597->reg + offset;
|
||||
void __iomem *fifoaddr = r8a66597->reg + offset;
|
||||
unsigned int data;
|
||||
int i;
|
||||
|
||||
|
|
@ -144,7 +144,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
|
|||
|
||||
/* aligned buf case */
|
||||
if (len >= 4 && !((unsigned long)buf & 0x03)) {
|
||||
insl(fifoaddr, buf, len / 4);
|
||||
ioread32_rep(fifoaddr, buf, len / 4);
|
||||
buf += len & ~0x03;
|
||||
len &= 0x03;
|
||||
}
|
||||
|
|
@ -152,7 +152,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
|
|||
/* unaligned buf case */
|
||||
for (i = 0; i < len; i++) {
|
||||
if (!(i & 0x03))
|
||||
data = inl(fifoaddr);
|
||||
data = ioread32(fifoaddr);
|
||||
|
||||
buf[i] = (data >> ((i & 0x03) * 8)) & 0xff;
|
||||
}
|
||||
|
|
@ -161,7 +161,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
|
|||
|
||||
/* aligned buf case */
|
||||
if (len >= 2 && !((unsigned long)buf & 0x01)) {
|
||||
insw(fifoaddr, buf, len / 2);
|
||||
ioread16_rep(fifoaddr, buf, len / 2);
|
||||
buf += len & ~0x01;
|
||||
len &= 0x01;
|
||||
}
|
||||
|
|
@ -169,7 +169,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
|
|||
/* unaligned buf case */
|
||||
for (i = 0; i < len; i++) {
|
||||
if (!(i & 0x01))
|
||||
data = inw(fifoaddr);
|
||||
data = ioread16(fifoaddr);
|
||||
|
||||
buf[i] = (data >> ((i & 0x01) * 8)) & 0xff;
|
||||
}
|
||||
|
|
@ -179,7 +179,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
|
|||
static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
|
||||
unsigned long offset)
|
||||
{
|
||||
outw(val, r8a66597->reg + offset);
|
||||
iowrite16(val, r8a66597->reg + offset);
|
||||
}
|
||||
|
||||
static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
|
||||
|
|
@ -187,21 +187,21 @@ static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
|
|||
unsigned char *buf,
|
||||
int len)
|
||||
{
|
||||
unsigned long fifoaddr = r8a66597->reg + offset;
|
||||
void __iomem *fifoaddr = r8a66597->reg + offset;
|
||||
int adj = 0;
|
||||
int i;
|
||||
|
||||
if (r8a66597->pdata->on_chip) {
|
||||
/* 32-bit access only if buf is 32-bit aligned */
|
||||
if (len >= 4 && !((unsigned long)buf & 0x03)) {
|
||||
outsl(fifoaddr, buf, len / 4);
|
||||
iowrite32_rep(fifoaddr, buf, len / 4);
|
||||
buf += len & ~0x03;
|
||||
len &= 0x03;
|
||||
}
|
||||
} else {
|
||||
/* 16-bit access only if buf is 16-bit aligned */
|
||||
if (len >= 2 && !((unsigned long)buf & 0x01)) {
|
||||
outsw(fifoaddr, buf, len / 2);
|
||||
iowrite16_rep(fifoaddr, buf, len / 2);
|
||||
buf += len & ~0x01;
|
||||
len &= 0x01;
|
||||
}
|
||||
|
|
@ -216,7 +216,7 @@ static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
|
|||
}
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
outb(buf[i], fifoaddr + adj - (i & adj));
|
||||
iowrite8(buf[i], fifoaddr + adj - (i & adj));
|
||||
}
|
||||
|
||||
static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
|
||||
|
|
|
|||
|
|
@ -2404,7 +2404,7 @@ static int __init_or_module r8a66597_remove(struct platform_device *pdev)
|
|||
|
||||
del_timer_sync(&r8a66597->rh_timer);
|
||||
usb_remove_hcd(hcd);
|
||||
iounmap((void *)r8a66597->reg);
|
||||
iounmap(r8a66597->reg);
|
||||
#ifdef CONFIG_HAVE_CLK
|
||||
if (r8a66597->pdata->on_chip)
|
||||
clk_put(r8a66597->clk);
|
||||
|
|
@ -2496,7 +2496,7 @@ static int __devinit r8a66597_probe(struct platform_device *pdev)
|
|||
init_timer(&r8a66597->rh_timer);
|
||||
r8a66597->rh_timer.function = r8a66597_timer;
|
||||
r8a66597->rh_timer.data = (unsigned long)r8a66597;
|
||||
r8a66597->reg = (unsigned long)reg;
|
||||
r8a66597->reg = reg;
|
||||
|
||||
/* make sure no interrupts are pending */
|
||||
ret = r8a66597_clock_enable(r8a66597);
|
||||
|
|
|
|||
|
|
@ -112,7 +112,7 @@ struct r8a66597_root_hub {
|
|||
|
||||
struct r8a66597 {
|
||||
spinlock_t lock;
|
||||
unsigned long reg;
|
||||
void __iomem *reg;
|
||||
#ifdef CONFIG_HAVE_CLK
|
||||
struct clk *clk;
|
||||
#endif
|
||||
|
|
@ -170,67 +170,67 @@ static inline struct urb *r8a66597_get_urb(struct r8a66597 *r8a66597,
|
|||
|
||||
static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
|
||||
{
|
||||
return inw(r8a66597->reg + offset);
|
||||
return ioread16(r8a66597->reg + offset);
|
||||
}
|
||||
|
||||
static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
|
||||
unsigned long offset, u16 *buf,
|
||||
int len)
|
||||
{
|
||||
unsigned long fifoaddr = r8a66597->reg + offset;
|
||||
void __iomem *fifoaddr = r8a66597->reg + offset;
|
||||
unsigned long count;
|
||||
|
||||
if (r8a66597->pdata->on_chip) {
|
||||
count = len / 4;
|
||||
insl(fifoaddr, buf, count);
|
||||
ioread32_rep(fifoaddr, buf, count);
|
||||
|
||||
if (len & 0x00000003) {
|
||||
unsigned long tmp = inl(fifoaddr);
|
||||
unsigned long tmp = ioread32(fifoaddr);
|
||||
memcpy((unsigned char *)buf + count * 4, &tmp,
|
||||
len & 0x03);
|
||||
}
|
||||
} else {
|
||||
len = (len + 1) / 2;
|
||||
insw(fifoaddr, buf, len);
|
||||
ioread16_rep(fifoaddr, buf, len);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
|
||||
unsigned long offset)
|
||||
{
|
||||
outw(val, r8a66597->reg + offset);
|
||||
iowrite16(val, r8a66597->reg + offset);
|
||||
}
|
||||
|
||||
static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
|
||||
unsigned long offset, u16 *buf,
|
||||
int len)
|
||||
{
|
||||
unsigned long fifoaddr = r8a66597->reg + offset;
|
||||
void __iomem *fifoaddr = r8a66597->reg + offset;
|
||||
unsigned long count;
|
||||
unsigned char *pb;
|
||||
int i;
|
||||
|
||||
if (r8a66597->pdata->on_chip) {
|
||||
count = len / 4;
|
||||
outsl(fifoaddr, buf, count);
|
||||
iowrite32_rep(fifoaddr, buf, count);
|
||||
|
||||
if (len & 0x00000003) {
|
||||
pb = (unsigned char *)buf + count * 4;
|
||||
for (i = 0; i < (len & 0x00000003); i++) {
|
||||
if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
|
||||
outb(pb[i], fifoaddr + i);
|
||||
iowrite8(pb[i], fifoaddr + i);
|
||||
else
|
||||
outb(pb[i], fifoaddr + 3 - i);
|
||||
iowrite8(pb[i], fifoaddr + 3 - i);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
int odd = len & 0x0001;
|
||||
|
||||
len = len / 2;
|
||||
outsw(fifoaddr, buf, len);
|
||||
ioread16_rep(fifoaddr, buf, len);
|
||||
if (unlikely(odd)) {
|
||||
buf = &buf[len];
|
||||
outb((unsigned char)*buf, fifoaddr);
|
||||
iowrite8((unsigned char)*buf, fifoaddr);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -991,13 +991,13 @@ static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
|
|||
priv->ch[j].lcdc = priv;
|
||||
memcpy(&priv->ch[j].cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
|
||||
|
||||
error = sh_mobile_lcdc_check_interface(&priv->ch[i]);
|
||||
error = sh_mobile_lcdc_check_interface(&priv->ch[j]);
|
||||
if (error) {
|
||||
dev_err(&pdev->dev, "unsupported interface type\n");
|
||||
goto err1;
|
||||
}
|
||||
init_waitqueue_head(&priv->ch[i].frame_end_wait);
|
||||
init_completion(&priv->ch[i].vsync_completion);
|
||||
init_waitqueue_head(&priv->ch[j].frame_end_wait);
|
||||
init_completion(&priv->ch[j].vsync_completion);
|
||||
priv->ch[j].pan_offset = 0;
|
||||
|
||||
switch (pdata->ch[i].chan) {
|
||||
|
|
|
|||
Loading…
Reference in a new issue