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irqchip: add initial support for ompic

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IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as
described in the Multi-core support section of the OpenRISC 1.2
architecture specification:

  https://github.com/openrisc/doc/raw/master/openrisc-arch-1.2-rev0.pdf

Each OpenRISC core contains a full interrupt controller which is used in
the SMP architecture for interrupt balancing.  This IPI device, the
ompic, is the only external device required for enabling SMP on
OpenRISC.

Pending ops are stored in a memory bit mask which can allow multiple
pending operations to be set and serviced at a time. This is mostly
borrowed from the alpha IPI implementation.

Reviewed-by: Marc Zyngier <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Stefan Kristiansson <[email protected]>
[[email protected]: converted ops to bitmask, wrote commit message]
Signed-off-by: Stafford Horne <[email protected]>
This commit is contained in:
Stafford Horne 2017-10-30 21:38:35 +09:00
commit 9b54470afd
6 changed files with 230 additions and 0 deletions
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1
arch/openrisc/Kconfig
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@ -30,6 +30,7 @@ config OPENRISC
select NO_BOOTMEM
select ARCH_USE_QUEUED_SPINLOCKS
select ARCH_USE_QUEUED_RWLOCKS
select OMPIC if SMP
config CPU_BIG_ENDIAN
def_bool y