From 2c4ee1b366fa81ec21bacab70eb008a32adcbff1 Mon Sep 17 00:00:00 2001
From: Raghavendra Kakarla <rkakarla@qti.qualcomm.com>
Date: Sun, 26 Apr 2020 11:42:09 +0530
Subject: [PATCH 1/2] dt-bindings: Add documentation for mpm irqchip

Add documentation for mpm interrupt controller.

Change-Id: I00a6435f0402b5fb0c5c4c0c54c37edd8d7dfd74
---
 bindings/interrupt-controller/qcom,mpm.txt | 72 ++++++++++++++++++++++
 1 file changed, 72 insertions(+)
 create mode 100644 bindings/interrupt-controller/qcom,mpm.txt

diff --git a/bindings/interrupt-controller/qcom,mpm.txt b/bindings/interrupt-controller/qcom,mpm.txt
new file mode 100644
index 000000000000..1d5997bfb61c
--- /dev/null
+++ b/bindings/interrupt-controller/qcom,mpm.txt
@@ -0,0 +1,72 @@
+QTI MPM interrupt controller
+MPM (MSM sleep Power Manager) is QTI's platform parent
+interrupt controller. It manages subsystem wakeups and
+resources during sleep. This driver marks the wakeup
+interrupts in APSS such that it monitors the interrupts
+when the system is asleep, wakes up the APSS when one
+of these interrupts occur and replays it to the subsystem
+interrupt controller after it becomes operational.
+
+Platform interrupt controller MPM is next in hierarchy,
+followed by others.
+
+This defines 2 interrupt controllers to monitor the
+interrupts when system is asleep:
+
+One to monitor the wakeup capable gic interrupts called
+wakegic.
+
+Properties:
+
+- compatible:
+	Usage: required
+	Value type: <string>
+	Definition: Should contain "qcom,mpm-gic" and the respective
+	target compatible flag from below ones.
+		"qcom,mpm-gic-holi"
+
+- interrupts:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: should specify the IRQ used by remote processor to
+	wakeup APSS.
+
+- interrupt-parent:
+	Usage: required
+	Value type: <phandle>
+	Definition: Specifies the interrupt parent necessary for
+	hierarchical domain to operate.
+
+- interrupt-controller:
+	Usage: required
+	Value type: <bool>
+	Definition: Identifies the node as an interrupt controller.
+
+- reg:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: Specifies the base physical address to trigger an
+	interrupt into remote processor.
+
+-reg-names:
+	Usage: required
+	Value type: <string>, <string>
+	Definition: Specifies the address field names.
+
+- qcom,num-mpm-irqs:
+	Usage: optional
+	Value type: <value>
+	Defination: Specifies the number of interrupts supported.
+
+Example:
+
+wakegic: wake-gic@7781b8 {
+	compatible = "qcom,mpm", "qcom,mpm-gic-holi";
+	interrupts = <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>;
+	reg = <0x601d4 0x1000>,
+	    <0xb011008 0x4>;  /* MSM_APCS_GCC_BASE 4K */
+	reg-names = "vmpm", "ipc";
+	interrupt-controller;
+	interrupt-parent = <&intc>;
+	#interrupt-cells = <3>;
+};

From c8a4bef689312fd02890fa05676e7e9ee9d208b2 Mon Sep 17 00:00:00 2001
From: Raghavendra Kakarla <rkakarla@qti.qualcomm.com>
Date: Wed, 1 Apr 2020 03:53:54 +0530
Subject: [PATCH 2/2] ARM: dts: msm: Add MPM interrupt controller for holi

Add mpm interrupt controller node to program the wakeup
capable interrupts to RPM MSG RAM.

Change-Id: I930620443e0abef6bc39feee33496a45a9552d1e
---
 qcom/holi.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi
index 26664fdf4208..87718cf390b6 100644
--- a/qcom/holi.dtsi
+++ b/qcom/holi.dtsi
@@ -498,6 +498,18 @@
 		qcom,wakeup-enable;
 	};
 
+	wakegic: wake-gic {
+		compatible = "qcom,mpm-gic-holi", "qcom,mpm";
+		interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
+		reg = <0x45f01b8 0x1000>,
+			<0x0f40000c 0x4>;  /* MSM_APCS_GCC_BASE 4K */
+		reg-names = "vmpm", "ipc";
+		qcom,num-mpm-irqs = <96>;
+		interrupt-controller;
+		interrupt-parent = <&intc>;
+		#interrupt-cells = <2>;
+	};
+
 	rpm_bus: qcom,rpm-smd {
 		compatible = "qcom,rpm-smd";
 		rpm-channel-name = "rpm_requests";