From c4c41afbad7261344e9ae57323d30cbcc4569bf2 Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Fri, 16 Oct 2020 10:13:43 +0800 Subject: [PATCH] ARM: dts: msm: Add initial devicetrees for SDXNIGHTJAR target Add initial devicetree files for supporing SDXNIGHTJAR target. Change-Id: I78a27e41723c3ff3a90955285ab5508dc6187855 --- bindings/arm/msm/msm.txt | 6 + bindings/interrupt-controller/arm,gic.txt | 171 +++ qcom/Makefile | 4 + qcom/sdxnightjar-cdp.dts | 11 + qcom/sdxnightjar-cdp.dtsi | 6 + qcom/sdxnightjar-mtp.dts | 11 + qcom/sdxnightjar-mtp.dtsi | 6 + qcom/sdxnightjar-pinctrl.dtsi | 1335 +++++++++++++++++++++ qcom/sdxnightjar-qrd.dts | 11 + qcom/sdxnightjar-qrd.dtsi | 6 + qcom/sdxnightjar.dtsi | 429 +++++++ 11 files changed, 1996 insertions(+) create mode 100644 bindings/interrupt-controller/arm,gic.txt create mode 100644 qcom/sdxnightjar-cdp.dts create mode 100644 qcom/sdxnightjar-cdp.dtsi create mode 100644 qcom/sdxnightjar-mtp.dts create mode 100644 qcom/sdxnightjar-mtp.dtsi create mode 100644 qcom/sdxnightjar-pinctrl.dtsi create mode 100644 qcom/sdxnightjar-qrd.dts create mode 100644 qcom/sdxnightjar-qrd.dtsi create mode 100644 qcom/sdxnightjar.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 0107b952f4b5..339b6c9b59f5 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -95,6 +95,9 @@ SoCs: - MONACO compatible = "qcom,monaco" +- SDXNIGHTJAR + compatible = "qcom,sdxnightjar" + Generic board variants: - CDP device: @@ -255,3 +258,6 @@ compatible = "qcom,holi-qrd" compatible = "qcom,holi-atp" compatible = "qcom,scuba-idp" compatible = "qcom,monaco-rumi" +compatible = "qcom,sdxnightjar-mtp" +compatible = "qcom,sdxnightjar-cdp" +compatible = "qcom,sdxnightjar-qrd" diff --git a/bindings/interrupt-controller/arm,gic.txt b/bindings/interrupt-controller/arm,gic.txt new file mode 100644 index 000000000000..7ac781f6efe9 --- /dev/null +++ b/bindings/interrupt-controller/arm,gic.txt @@ -0,0 +1,171 @@ +* ARM Generic Interrupt Controller + +ARM SMP cores are often associated with a GIC, providing per processor +interrupts (PPI), shared processor interrupts (SPI) and software +generated interrupts (SGI). + +Primary GIC is attached directly to the CPU and typically has PPIs and SGIs. +Secondary GICs are cascaded into the upward interrupt controller and do not +have PPIs or SGIs. + +Main node required properties: + +- compatible : should be one of: + "arm,arm1176jzf-devchip-gic" + "arm,arm11mp-gic" + "arm,cortex-a15-gic" + "arm,cortex-a7-gic" + "arm,cortex-a9-gic" + "arm,eb11mp-gic" + "arm,gic-400" + "arm,pl390" + "arm,tc11mp-gic" + "brcm,brahma-b15-gic" + "nvidia,tegra210-agic" + "qcom,msm-8660-qgic" + "qcom,msm-qgic2" +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The type shall be a and the value shall be 3. + + The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI + interrupts. + + The 2nd cell contains the interrupt number for the interrupt type. + SPI interrupts are in the range [0-987]. PPI interrupts are in the + range [0-15]. + + The 3rd cell is the flags, encoded as follows: + bits[3:0] trigger type and level flags. + 1 = low-to-high edge triggered + 2 = high-to-low edge triggered (invalid for SPIs) + 4 = active high level-sensitive + 8 = active low level-sensitive (invalid for SPIs). + bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of + the 8 possible cpus attached to the GIC. A bit set to '1' indicated + the interrupt is wired to that CPU. Only valid for PPI interrupts. + Also note that the configurability of PPI interrupts is IMPLEMENTATION + DEFINED and as such not guaranteed to be present (most SoC available + in 2014 seem to ignore the setting of this flag and use the hardware + default value). + +- reg : Specifies base physical address(s) and size of the GIC registers. The + first region is the GIC distributor register base and size. The 2nd region is + the GIC cpu interface register base and size. + +Optional +- interrupts : Interrupt source of the parent interrupt controller on + secondary GICs, or VGIC maintenance interrupt on primary GIC (see + below). + +- cpu-offset : per-cpu offset within the distributor and cpu interface + regions, used when the GIC doesn't have banked registers. The offset is + cpu-offset * cpu-nr. + +- clocks : List of phandle and clock-specific pairs, one for each entry + in clock-names. +- clock-names : List of names for the GIC clock input(s). Valid clock names + depend on the GIC variant: + "ic_clk" (for "arm,arm11mp-gic") + "PERIPHCLKEN" (for "arm,cortex-a15-gic") + "PERIPHCLK", "PERIPHCLKEN" (for "arm,cortex-a9-gic") + "clk" (for "arm,gic-400" and "nvidia,tegra210") + "gclk" (for "arm,pl390") + +- power-domains : A phandle and PM domain specifier as defined by bindings of + the power controller specified by phandle, used when the GIC + is part of a Power or Clock Domain. + + +Example: + + intc: interrupt-controller@fff11000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0xfff11000 0x1000>, + <0xfff10100 0x100>; + }; + + +* GIC virtualization extensions (VGIC) + +For ARM cores that support the virtualization extensions, additional +properties must be described (they only exist if the GIC is the +primary interrupt controller). + +Required properties: + +- reg : Additional regions specifying the base physical address and + size of the VGIC registers. The first additional region is the GIC + virtual interface control register base and size. The 2nd additional + region is the GIC virtual cpu interface register base and size. + +- interrupts : VGIC maintenance interrupt. + +Example: + + interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x2c001000 0x1000>, + <0x2c002000 0x1000>, + <0x2c004000 0x2000>, + <0x2c006000 0x2000>; + interrupts = <1 9 0xf04>; + }; + + +* GICv2m extension for MSI/MSI-x support (Optional) + +Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s). +This is enabled by specifying v2m sub-node(s). + +Required properties: + +- compatible : The value here should contain "arm,gic-v2m-frame". + +- msi-controller : Identifies the node as an MSI controller. + +- reg : GICv2m MSI interface register base and size + +Optional properties: + +- arm,msi-base-spi : When the MSI_TYPER register contains an incorrect + value, this property should contain the SPI base of + the MSI frame, overriding the HW value. + +- arm,msi-num-spis : When the MSI_TYPER register contains an incorrect + value, this property should contain the number of + SPIs assigned to the frame, overriding the HW value. + +Example: + + interrupt-controller@e1101000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + interrupt-controller; + interrupts = <1 8 0xf04>; + ranges = <0 0 0 0xe1100000 0 0x100000>; + reg = <0x0 0xe1110000 0 0x01000>, + <0x0 0xe112f000 0 0x02000>, + <0x0 0xe1140000 0 0x10000>, + <0x0 0xe1160000 0 0x10000>; + v2m0: v2m@0x8000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x80000 0 0x1000>; + }; + + .... + + v2mN: v2m@0x9000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x90000 0 0x1000>; + }; + }; diff --git a/qcom/Makefile b/qcom/Makefile index 555a1bcb5460..ab69f402e2f2 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -217,6 +217,10 @@ dtb-$(CONFIG_ARCH_QTI_VM) += shima-vm-rumi.dtb \ endif endif +dtb-$(CONFIG_ARCH_SDXNIGHTJAR) += sdxnightjar-mtp.dtb \ + sdxnightjar-cdp.dtb \ + sdxnightjar-qrd.dtb + always := $(dtb-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/qcom/sdxnightjar-cdp.dts b/qcom/sdxnightjar-cdp.dts new file mode 100644 index 000000000000..58a5bf7cdc99 --- /dev/null +++ b/qcom/sdxnightjar-cdp.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdxnightjar.dtsi" +#include "sdxnightjar-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDX NIGHTJAR CDP"; + compatible = "qcom,sdxnightjar-cdp", + "qcom,sdxnightjar", "qcom,cdp"; + qcom,board-id = <0x01 0>; +}; diff --git a/qcom/sdxnightjar-cdp.dtsi b/qcom/sdxnightjar-cdp.dtsi new file mode 100644 index 000000000000..084e2aec6ca1 --- /dev/null +++ b/qcom/sdxnightjar-cdp.dtsi @@ -0,0 +1,6 @@ +&blsp1_uart3 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_console_active>; +}; + diff --git a/qcom/sdxnightjar-mtp.dts b/qcom/sdxnightjar-mtp.dts new file mode 100644 index 000000000000..65e7fcd1c964 --- /dev/null +++ b/qcom/sdxnightjar-mtp.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdxnightjar.dtsi" +#include "sdxnightjar-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDX NIGHTJAR MTP"; + compatible = "qcom,sdxnightjar-mtp", + "qcom,sdxnightjar", "qcom,mtp"; + qcom,board-id = <8 0>; +}; diff --git a/qcom/sdxnightjar-mtp.dtsi b/qcom/sdxnightjar-mtp.dtsi new file mode 100644 index 000000000000..084e2aec6ca1 --- /dev/null +++ b/qcom/sdxnightjar-mtp.dtsi @@ -0,0 +1,6 @@ +&blsp1_uart3 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_console_active>; +}; + diff --git a/qcom/sdxnightjar-pinctrl.dtsi b/qcom/sdxnightjar-pinctrl.dtsi new file mode 100644 index 000000000000..410f4f9b0700 --- /dev/null +++ b/qcom/sdxnightjar-pinctrl.dtsi @@ -0,0 +1,1335 @@ +&soc { + tlmm_pinmux: pinctrl@1000000 { + compatible = "qcom,sdxnightjar-pinctrl"; + reg = <0x1000000 0x300000>; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + uart1_console_active: uart1_console_active { + mux { + pins = "gpio0", "gpio1"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + + trigout_a: trigout_a { + mux { + pins = "gpio92"; + function = "qdss_cti"; + }; + + config { + pins = "gpio92"; + drive-strength = <2>; + bias-disable; + }; + }; + + uart2_console_active: uart2_console_active { + mux { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + + uart3_console_active: uart3_console_active { + mux { + pins = "gpio8", "gpio9"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + + uart3_console_sleep: uart3_console_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* I2C CONFIGURATION */ + i2c_1 { + i2c_1_active: i2c_1_active { + mux { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_1_sleep: i2c_1_sleep { + mux { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_2 { + i2c_2_active: i2c_2_active { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_2_sleep: i2c_2_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_3 { + i2c_3_active: i2c_3_active { + mux { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_3_sleep: i2c_3_sleep { + mux { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_4 { + i2c_4_active: i2c_4_active { + mux { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_4_sleep: i2c_4_sleep { + mux { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + bmi160_int1_default: bmi160_int1_default { + mux { + pins = "gpio0"; + function = "gpio"; + }; + + config { + pins = "gpio0"; + drive-strength = <12>; + bias-pull-down; + }; + }; + + bmi160_int2_default: bmi160_int2_default { + mux { + pins = "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio1"; + drive-strength = <12>; + bias-pull-down; + }; + }; + + cnss_pins { + cnss_wlan_en_active: cnss_wlan_en_active { + mux { + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + + cnss_wlan_en_sleep: cnss_wlan_en_sleep { + mux { + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + + cnss_sdio_active: cnss_sdio_active { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + + cnss_sdio_sleep: cnss_sdio_sleep { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + }; + + /* SPI CONFIGURATION */ + spi_1 { + spi_1_active: spi_1_active { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "blsp_spi1"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_1_sleep: spi_1_sleep { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "blsp_spi1"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_2 { + spi_2_active: spi_2_active { + mux { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_2_sleep: spi_2_sleep { + mux { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_3 { + spi_3_active: spi_3_active { + mux { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_3_sleep: spi_3_sleep { + mux { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_4 { + spi_4_active: spi_4_active { + mux { + pins = "gpio16", "gpio17", "gpio18", + "gpio19"; + function = "blsp_spi4"; + }; + + config { + pins = "gpio16", "gpio17", "gpio18", + "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_4_sleep: spi_4_sleep { + mux { + pins = "gpio16", "gpio17", "gpio18", + "gpio19"; + function = "blsp_spi4"; + }; + + config { + pins = "gpio16", "gpio17", "gpio18", + "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SMB CONFIGURATION */ + pmx_smb_stat { + smb_stat_active: smb_stat_active { + mux { + pins = "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio83"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + pcie0 { + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio64"; + function = "pcie_clkreq"; + }; + + config { + pins = "gpio64"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio60"; + function = "gpio"; + }; + + config { + pins = "gpio60"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio61"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie0_mdm2apstatus_default: pcie0_mdm2apstatus_default { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_perst_default: pcie_ep_perst_default { + mux { + pins = "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio65"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_wake_default: pcie_ep_wake_default { + mux { + pins = "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio61"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + /* UART HS CONFIGURATION */ + blsp1_uart1_active: blsp1_uart1_active { + mux { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1_sleep: blsp1_uart1_sleep { + mux { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2_active: blsp1_uart2_active { + mux { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2_sleep: blsp1_uart2_sleep { + mux { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_active: blsp1_uart3_active { + mux { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_sleep: blsp1_uart3_sleep { + mux { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4_active: blsp1_uart4_active { + mux { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4_sleep: blsp1_uart4_sleep { + mux { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4b_active: blsp1_uart4b_active { + mux { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4b_sleep: blsp1_uart4b_sleep { + mux { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + mdss_cs_active: mdss_cs_active { + mux { + pins = "gpio21"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio21"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_cs_sleep: mdss_cs_sleep { + mux { + pins = "gpio21"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_te_active: mdss_te_active { + mux { + pins = "gpio22"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio22"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_te_sleep: mdss_te_sleep { + mux { + pins = "gpio22"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio22"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_rs_active: mdss_rs_active { + mux { + pins = "gpio23"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio23"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_rs_sleep: mdss_rs_sleep { + mux { + pins = "gpio23"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_ad_active: mdss_ad_active { + mux { + pins = "gpio20"; + function = "ebi2_a"; + }; + + config { + pins = "gpio20"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_ad_sleep: mdss_ad_sleep { + mux { + pins = "gpio20"; + function = "ebi2_a"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_bl_active: mdss_bl_active { + mux { + pins = "gpio68"; + function = "gpio"; + }; + + config { + pins = "gpio68"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + output-high; + }; + }; + + mdss_bl_sleep: mdss_bl_sleep { + mux { + pins = "gpio68"; + function = "gpio"; + }; + + config { + pins = "gpio68"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + output-low; + }; + }; + + i2s_mclk { + i2s_mclk_sleep: i2s_mclk_sleep { + mux { + pins = "gpio71"; + function = "i2s_mclk"; + }; + + config { + pins = "gpio71"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + i2s_mclk_active: i2s_mclk_active { + mux { + pins = "gpio71"; + function = "i2s_mclk"; + }; + + config { + pins = "gpio71"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + }; + + pmx_pri_mi2s_aux { + pri_ws_sleep: pri_ws_sleep { + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_sck_sleep: pri_sck_sleep { + mux { + pins = "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio15"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_dout_sleep: pri_dout_sleep { + mux { + pins = "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_ws_active_master: pri_ws_active_master { + mux { + pins = "gpio12"; + function = "pri_mi2s_ws_a"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + pri_sck_active_master: pri_sck_active_master { + mux { + pins = "gpio15"; + function = "pri_mi2s_sck_a"; + }; + + config { + pins = "gpio15"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + pri_ws_active_slave: pri_ws_active_slave { + mux { + pins = "gpio12"; + function = "pri_mi2s_ws_a"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + pri_sck_active_slave: pri_sck_active_slave { + mux { + pins = "gpio15"; + function = "pri_mi2s_sck_a"; + }; + + config { + pins = "gpio15"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + pri_dout_active: pri_dout_active { + mux { + pins = "gpio14"; + function = "pri_mi2s_data1_a"; + }; + + config { + pins = "gpio14"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + }; + + pmx_pri_mi2s_aux_din { + pri_din_sleep: pri_din_sleep { + mux { + pins = "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_din_active: pri_din_active { + mux { + pins = "gpio13"; + function = "pri_mi2s_data0_a"; + }; + + config { + pins = "gpio13"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pmx_sec_mi2s_aux { + sec_ws_sleep: sec_ws_sleep { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_sck_sleep: sec_sck_sleep { + mux { + pins = "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio19"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_dout_sleep: sec_dout_sleep { + mux { + pins = "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_ws_active_master: sec_ws_active_master { + mux { + pins = "gpio16"; + function = "sec_mi2s_ws_a"; + }; + + config { + pins = "gpio16"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + sec_sck_active_master: sec_sck_active_master { + mux { + pins = "gpio19"; + function = "sec_mi2s_sck_a"; + }; + + config { + pins = "gpio19"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + sec_ws_active_slave: sec_ws_active_slave { + mux { + pins = "gpio16"; + function = "sec_mi2s_ws_a"; + }; + + config { + pins = "gpio16"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + sec_sck_active_slave: sec_sck_active_slave { + mux { + pins = "gpio19"; + function = "sec_mi2s_sck_a"; + }; + + config { + pins = "gpio19"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + sec_dout_active: sec_dout_active { + mux { + pins = "gpio18"; + function = "sec_mi2s_data1_a"; + }; + + config { + pins = "gpio18"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + }; + + pmx_sec_mi2s_aux_din { + sec_din_sleep: sec_din_sleep { + mux { + pins = "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_din_active: sec_din_active { + mux { + pins = "gpio17"; + function = "sec_mi2s_data0_a"; + }; + + config { + pins = "gpio17"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pmx_sec_mi2s_b_aux { + sec_ws_b_sleep: sec_ws_b_sleep { + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_sck_b_sleep: sec_sck_b_sleep { + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_dout_b_sleep: sec_dout_b_sleep { + mux { + pins = "gpio22"; + function = "gpio"; + }; + + config { + pins = "gpio22"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_ws_b_active_master: sec_ws_b_active_master { + mux { + pins = "gpio20"; + function = "sec_mi2s_ws_b"; + }; + + config { + pins = "gpio20"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + sec_sck_b_active_master: sec_sck_b_active_master { + mux { + pins = "gpio23"; + function = "sec_mi2s_sck_b"; + }; + + config { + pins = "gpio23"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + sec_ws_b_active_slave: sec_ws_b_active_slave { + mux { + pins = "gpio20"; + function = "sec_mi2s_ws_b"; + }; + + config { + pins = "gpio20"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + sec_sck_b_active_slave: sec_sck_b_active_slave { + mux { + pins = "gpio23"; + function = "sec_mi2s_sck_b"; + }; + + config { + pins = "gpio23"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + sec_dout_b_active: sec_dout_b_active { + mux { + pins = "gpio22"; + function = "sec_mi2s_data1_b"; + }; + + config { + pins = "gpio22"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + }; + + pmx_sec_mi2s_b_aux_din { + sec_din_b_sleep: sec_din_b_sleep { + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_din_b_active: sec_din_b_active { + mux { + pins = "gpio21"; + function = "sec_mi2s_data0_b"; + }; + + config { + pins = "gpio21"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sdc1_clk_on: sdc1_clk_on { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc1_clk_off: sdc1_clk_off { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_cmd_on: sdc1_cmd_on { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_cmd_off: sdc1_cmd_off { + config { + pins = "sdc1_cmd"; + num-grp-pins = <1>; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_data_on: sdc1_data_on { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_data_off: sdc1_data_off { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_wlan_gpio { + sdc1_wlan_gpio_active: sdc1_wlan_gpio_active { + mux { + pins = "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio80"; + output-high; + drive-strength = <8>; + bias-pull-up; + }; + }; + + sdc1_wlan_gpio_sleep: sdc1_wlan_gpio_sleep { + mux { + pins = "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio80"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + }; + + pinctrl_pps: ppsgrp { + mux { + pins = "gpio39"; + function = "nav_dr"; + }; + + config { + pins = "gpio39"; + bias-pull-down; + }; + }; + + can_reset { + can_rst_on: rst_on { + mux { + pins = "gpio68"; + function = "gpio"; + }; + + + config { + pins = "gpio68"; + drive-strength = <2>; /* 2 mA */ + bias-pull-up; + }; + }; + + can_rst_off: rst_off { + mux { + pins = "gpio68"; + function = "gpio"; + }; + + config { + pins = "gpio68"; + drive-strength = <2>; /* 2 mA */ + bias-pull-up; + output-high; + }; + }; + }; + }; +}; diff --git a/qcom/sdxnightjar-qrd.dts b/qcom/sdxnightjar-qrd.dts new file mode 100644 index 000000000000..287997958419 --- /dev/null +++ b/qcom/sdxnightjar-qrd.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdxnightjar.dtsi" +#include "sdxnightjar-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDX NIGHTJAR QRD"; + compatible = "qcom,sdxnightjar-qrd", + "qcom,sdxnightjar", "qcom,qrd"; + qcom,board-id = <0xB 0>; +}; diff --git a/qcom/sdxnightjar-qrd.dtsi b/qcom/sdxnightjar-qrd.dtsi new file mode 100644 index 000000000000..084e2aec6ca1 --- /dev/null +++ b/qcom/sdxnightjar-qrd.dtsi @@ -0,0 +1,6 @@ +&blsp1_uart3 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_console_active>; +}; + diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi new file mode 100644 index 000000000000..ad15a0902055 --- /dev/null +++ b/qcom/sdxnightjar.dtsi @@ -0,0 +1,429 @@ +#include + +/ { + model = "Qualcomm Technologies, Inc. SDXNIGHTJAR"; + compatible = "qcom,sdxnightjar"; + qcom,msm-id = <484 0x10000>; + interrupt-parent = <&intc>; + #address-cells = <0x1>; + #size-cells = <0x1>; + + chosen { }; + + memory { + device_type = "memory"; + reg = <0 0>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + peripheral1_mem: peripheral1_region@0x87800000 { + no-map; + reg = <0x87800000 0x400000>; + label = "peripheral1_mem"; + }; + + peripheral2_mem: peripheral2_region@0x87d00000 { + no-map; + reg = <0x87d00000 0x300000>; + label = "peripheral2_mem"; + }; + }; + + aliases { }; + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + }; + + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + qcom,mpm2-sleep-counter@4a3000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0x004a3000 0x1000>; + clock-frequency = <32768>; + }; + + qcom,msm-imem@8600000 { + compatible = "qcom,msm-imem"; + reg = <0x8600000 0x1000>; /* Address and size of IMEM */ + ranges = <0x0 0x8600000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + }; + + clock_gcc: qcom,gcc@1800000 { + ompatible = "qcom,dummycc"; + #clock-cells = <1>; + }; + + clock_debug: qcom,cc-debug@1874000 { + compatible = "qcom,dummycc"; + #clock-cells = <1>; + }; + + clock_cpu: qcom,clock-a7@0b010008 { + compatible = "qcom,dummycc"; + #clock-cells = <1>; + }; + + qcom,msm-cpufreq { + compatible = "qcom,msm-cpufreq"; + /*TODO: Fix the clock when tree is available*/ + clock-names = "cpu0_clk", "cpu1_clk", + "cpu2_clk", "cpu3_clk"; + qcom,cpufreq-table = + < 200000 >, + < 300000 >, + < 384000 >, + < 600000 >, + < 787200 >, + < 998400 >, + < 1190400 >, + < 1286400 >; + }; + + ahb_clk: qcom,ahb-clk-src { + compatible = "devfreq-simple-dev"; + clock-names = "devfreq_clk"; + /*TODO: Fix the clock when tree is available*/ + governor = "powersave"; + freq-tbl-khz = + < 19200 >, + < 50000 >, + < 100000 >, + < 133330 >; + }; + + restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x4ab000 0x4>, + <0x0193d100 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + timer@b020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xb020000 0x1000>; + clock-frequency = <19200000>; + + frame@b021000 { + frame-number = <0>; + interrupts = <0 7 0x4>, + <0 6 0x4>; + reg = <0xb021000 0x1000>, + <0xb022000 0x1000>; + }; + + frame@b023000 { + frame-number = <1>; + interrupts = <0 8 0x4>; + reg = <0xb023000 0x1000>; + status = "disabled"; + }; + + frame@b024000 { + frame-number = <2>; + interrupts = <0 9 0x4>; + reg = <0xb024000 0x1000>; + status = "disabled"; + }; + + frame@b025000 { + frame-number = <3>; + interrupts = <0 10 0x4>; + reg = <0xb025000 0x1000>; + status = "disabled"; + }; + + frame@b026000 { + frame-number = <4>; + interrupts = <0 11 0x4>; + reg = <0xb026000 0x1000>; + status = "disabled"; + }; + + frame@b027000 { + frame-number = <5>; + interrupts = <0 12 0x4>; + reg = <0xb027000 0x1000>; + status = "disabled"; + }; + + frame@b028000 { + frame-number = <6>; + interrupts = <0 13 0x4>; + reg = <0xb028000 0x1000>; + status = "disabled"; + }; + + frame@b029000 { + frame-number = <7>; + interrupts = <0 14 0x4>; + reg = <0xb029000 0x1000>; + status = "disabled"; + }; + }; + + + + + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + qcom_rng: qrng@e3000 { + compatible = "qcom,msm-rng"; + reg = <0xe3000 0x1000>; + qcom,msm-rng-iface-clk; + qcom,no-qrng-config; + qcom,msm-bus,name = "msm-rng-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 618 0 0>, /* No vote */ + <1 618 0 800>; /* 100 MB/s */ + /*TODO: Fix the clock when tree is available*/ + clock-names = "iface_clk"; + }; + + qcom_tzlog: tz-log@08600720 { + compatible = "qcom,tz-log"; + reg = <0x08600720 0x2000>; + }; + + qcom,qcedev@720000 { + compatible = "qcom,qcedev"; + reg = <0x720000 0x20000>, + <0x704000 0x20000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 0>; + qcom,bam-pipe-pair = <1>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <47 512 0 0>, + <47 512 393600 393600>; + /*TODO: Fix the clock when tree is available*/ + clock-names = "core_clk", "iface_clk", + "bus_clk","core_clk_src"; + qcom,ce-opp-freq = <171430000>; + }; + + qcom,qcrypto@720000 { + compatible = "qcom,qcrypto"; + reg = <0x720000 0x20000>, + <0x704000 0x20000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 0>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <47 512 0 0>, + <47 512 393600 393600>; + /*TODO: Fix the clock when tree is available*/ + clock-names = "core_clk", "iface_clk", + "bus_clk","core_clk_src"; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-hmac-algo; + qcom,use-sw-aead-algo; + qcom,ce-opp-freq = <171430000>; + }; + + qcom_seecom: qseecom@87800000 { + compatible = "qcom,qseecom"; + reg = <0x87800000 0x200000>; + reg-names = "secapp-region"; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <47 512 0 0>, + <47 512 200000 400000>, + <47 512 300000 800000>, + <47 512 400000 1000000>; + /*TODO: Fix the clock when tree is available*/ + clock-names = "core_clk", "iface_clk", + "bus_clk","core_clk_src"; + qcom,ce-opp-freq = <100000000>; + }; + + qcom,rmnet-ipa { + compatible = "qcom,rmnet-ipa3"; + qcom,rmnet-ipa-ssr; + }; + + blsp1_uart1: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78af000 0x200>; + interrupts = <0 107 0>; + /*TODO: Fix the clock when tree is available*/ + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_uart2: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78b0000 0x200>; + interrupts = <0 108 0>; + /*TODO: Fix the clock when tree is available*/ + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_uart3: serial@78b1000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78b1000 0x200>; + interrupts = <0 109 0>; + /*TODO: Fix the clock when tree is available*/ + clock-names = "core", "iface"; + status = "disabled"; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; + + qcom,wdt@b017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xb017000 0x1000>; + reg-names = "wdt-base"; + interrupts = <1 3 0>, <1 2 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <10000>; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + jtag_mm0: jtagmm@842000 { + compatible = "qcom,jtag-mm"; + reg = <0x842000 0x1000>, + <0x840000 0x1000>; + reg-names = "etm-base","debug-base"; + + qcom,coresight-jtagmm-cpu = <&CPU0>; + + /*TODO: Fix the clock when tree is available*/ + clock-names = "core_clk", "core_a_clk"; + }; + + qcom,smem@87e80000 { + compatible = "qcom,smem"; + reg = <0x87e80000 0xc0000>, + <0xb011008 0x4>, + <0x60000 0x6000>, + <0x193d000 0x8>; + reg-names = "smem", "irq-reg-base", "aux-mem1", + "smem_targ_info_reg"; + qcom,mpu-enabled; + + qcom,smd-modem { + compatible = "qcom,smd"; + qcom,smd-edge = <0>; + qcom,smd-irq-offset = <0x0>; + qcom,smd-irq-bitmask = <0x1000>; + interrupts = <0 25 1>; + label = "modem"; + }; + + qcom,smd-rpm { + compatible = "qcom,smd"; + qcom,smd-edge = <15>; + qcom,smd-irq-offset = <0x0>; + qcom,smd-irq-bitmask = <0x1>; + interrupts = <0 168 1>; + label = "rpm"; + qcom,irq-no-suspend; + qcom,not-loadable; + }; + }; + + + spmi_bus: qcom,spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x200f000 0x1000>, + <0x2400000 0x800000>, + <0x2c00000 0x800000>, + <0x3800000 0x200000>, + <0x200a000 0x2100>; /* includes SPMI_CFG and GENI_CFG */ + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupts = <0 190 0>; + qcom,pmic-arb-channel = <0>; + qcom,pmic-arb-ee = <0>; + qcom,pmic-arb-max-peripherals = <256>; + qcom,pmic-arb-max-periph-interrupts = <256>; + #interrupt-cells = <3>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + }; +}; + +#include "sdxnightjar-pinctrl.dtsi"