From 0be02529f92069e16b4c4caa450830b9b751467a Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Tue, 20 Sep 2022 06:01:06 -0700
Subject: [PATCH 01/21] fw-api: CL 19643763 - update fw common interface files

add WMI_VENDOR_OUI_ACTION_ALLOW_11BE def

Change-Id: Ie9299297e1eb2463a564822cac9652e18d199444
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 6 ++++++
 fw/wmi_version.h | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index a973e05aeccb..81c7326c79ef 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -21230,6 +21230,12 @@ typedef enum
     /* Extend ITO under WOW mode if vendor OUI is received in beacon */
     WMI_VENDOR_OUI_ACTION_EXTEND_WOW_ITO = 8,
 
+    /*
+     * Turn on station 80211BE feature if AP's vendor OUI is in the list
+     * for specific customer
+     */
+    WMI_VENDOR_OUI_ACTION_ALLOW_11BE = 9,
+
     /* Add any action before this line */
     WMI_VENDOR_OUI_ACTION_MAX_ACTION_ID
 } wmi_vendor_oui_action_id;
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 72738680e292..434b5351cc1c 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1214
+#define __WMI_REVISION_ 1215
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From f81b8a46d311f209af92ae7517985e5aa4988486 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Tue, 20 Sep 2022 18:00:57 -0700
Subject: [PATCH 02/21] fw-api: CL 19652973 - update fw common interface files

Change-Id: I3f61031a46478d719124de651795dec4937fd5dd
WMI: add wfa_config_ofdma to wfa_config_cmd msg
CRs-Fixed: 2262693
---
 fw/wmi_tlv_defs.h |  4 +++-
 fw/wmi_unified.h  | 12 ++++++++++++
 fw/wmi_version.h  |  2 +-
 3 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 668f97e8ca80..547e03ef3cf2 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1299,6 +1299,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_xgap_enable_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_xgap_enable_complete_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_pdev_mesh_rx_filter_enable_fixed_param,
+    WMITLV_TAG_STRUC_wmi_wfa_config_ofdma,
 } WMITLV_TAG_ID;
 
 /*
@@ -4912,7 +4913,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SIMULATION_TEST_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_rsnxe, wfa_config_rsnxe, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_csa, wfa_config_csa, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_ocv, wfa_config_ocv, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_saquery, wfa_config_saquery, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_saquery, wfa_config_saquery, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_ofdma, wfa_config_ofdma, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_WFA_CONFIG_CMDID);
 
 /* SRG OBSS color Enable Bitmap */
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 81c7326c79ef..79145789c5b9 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -39227,6 +39227,17 @@ typedef struct {
     A_UINT32 remain_connect_on_saquery_timeout;
 } wmi_wfa_config_saquery;
 
+typedef struct {
+    /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wfa_config_ofdma */
+    A_UINT32 tlv_header;
+    /* force_he_trigger_to_eht_sta
+     *   Possible values from host are:
+     *   0  default behavior
+     *   1  instead of sending EHT triggers to EHT stations, send HE triggers
+     */
+    A_UINT32 force_he_trigger_to_eht_sta;
+} wmi_wfa_config_ofdma;
+
 typedef struct {
     /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wfa_config_cmd_fixed_param */
     A_UINT32 tlv_header;
@@ -39237,6 +39248,7 @@ typedef struct {
      * wmi_wfa_config_csa     wfa_config_csa[];     (0 or 1 elements)
      * wmi_wfa_config_ocv     wfa_config_ocv[];     (0 or 1 elements)
      * wmi_wfa_config_saquery wfa_config_saquery[]; (0 or 1 elements)
+     * wmi_wfa_config_ofdma   wfa_config_ofdma[];   (0 or 1 elements)
      */
 } wmi_wfa_config_cmd_fixed_param;
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 434b5351cc1c..730058b1499d 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1215
+#define __WMI_REVISION_ 1216
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From e616099e4fec171d33f1a8721a58a0d3fd2bc800 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 28 Sep 2022 06:01:04 -0700
Subject: [PATCH 03/21] fw-api: CL 19741763 - update fw common interface files

Change-Id: Ic4af0eb5c43cecec7e04c9a2ca69e26ccfec85b7
WMI: add extd KEK,KCK to GTK_OFFLOAD_CMD msg, define new SHA384 auth types
CRs-Fixed: 2262693
---
 fw/wmi_services.h |  1 +
 fw/wmi_tlv_defs.h |  4 +++-
 fw/wmi_unified.h  | 14 ++++++++++++++
 fw/wmi_version.h  |  2 +-
 4 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index c348d821d56c..16753f676985 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -600,6 +600,7 @@ typedef  enum  {
     WMI_SERVICE_XGAP_SUPPORT = 347, /* FW support for XGAP */
     WMI_SERVICE_OBSS_PER_PACKET_SR_SUPPORT = 348, /* Spatial Reuse support for per PPDU setting */
     WMI_SERVICE_MULTIPLE_VDEV_RESTART_BITMAP_SUPPORT = 349, /* Extended Multiple VDEV Restart with Bitmap Support */
+    WMI_SERVICE_WMI_SERVICE_WPA3_SHA384_ROAM_SUPPORT = 350, /* Indicates FW supports WPA3 SHA384 roaming */
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 547e03ef3cf2..c5f8a960fb3e 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -2508,7 +2508,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_P2P_GO_SET_BEACON_IE);
 /* GTK offload Cmd */
 #define WMITLV_TABLE_WMI_GTK_OFFLOAD_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_GTK_OFFLOAD_CMD_fixed_param, WMI_GTK_OFFLOAD_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_gtk_offload_fils_tlv_param, wmi_fils_gtk_info, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_gtk_offload_fils_tlv_param, wmi_fils_gtk_info, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, kek_ext, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, kck_ext, WMITLV_SIZE_VAR)
 
 WMITLV_CREATE_PARAM_STRUC(WMI_GTK_OFFLOAD_CMDID);
 
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 79145789c5b9..465ed92119ca 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -17834,6 +17834,9 @@ enum {
     WMI_AUTH_WPA3_SAE,
     WMI_AUTH_WPA3_OWE,
     WMI_AUTH_PASN,
+    WMI_AUTH_RSNA_8021X_SHA384,
+    WMI_AUTH_WPA3_SAE_SHA384,
+    WMI_AUTH_FT_RSNA_SAE_SHA384,
 };
 
 typedef enum {
@@ -21054,6 +21057,17 @@ typedef struct {
     A_UINT8 KEK[GTK_OFFLOAD_KEK_BYTES]; /* key encryption key */
     A_UINT8 KCK[GTK_OFFLOAD_KCK_BYTES]; /* key confirmation key */
     A_UINT8 replay_counter[GTK_REPLAY_COUNTER_BYTES]; /* replay counter for re-key */
+
+    /*
+     * Following structure will be appended when fils:
+     *     wmi_gtk_offload_fils_tlv_param wmi_fils_gtk_info;
+     * Following structure will be appended to the above KEK[] when kek length
+     * is larger than GTK_OFFLOAD_KEK_BYTES:
+     *     A_UINT8 kek_ext[];
+     * Following structure will be appended to the above KCK[] when kck length
+     * is larger than GTK_OFFLOAD_KCK_BYTES:
+     *     A_UINT8 kck_ext[];
+     */
 } WMI_GTK_OFFLOAD_CMD_fixed_param;
 
 typedef struct {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 730058b1499d..8f968e68319e 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1216
+#define __WMI_REVISION_ 1217
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 642fab3cd0925e09b654e7d87b610d9b3f3714e8 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 28 Sep 2022 18:00:58 -0700
Subject: [PATCH 04/21] fw-api: CL 19752762 - update fw common interface files

HTT stats: add pdev_up_time field in tx_pdev_ppdu_dur_stats TLV

Change-Id: I037f0d2afafe4cdea4984c317e0adc4be8664cba
CRs-Fixed: 2262693
---
 fw/htt_stats.h | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 3297d37191f6..9d8fe4d7e3bb 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -901,7 +901,8 @@ typedef struct {
     /** Num of times su bf sequences are denylisted */
     A_UINT32 num_su_txbf_denylisted;
     /** pdev uptime in microseconds **/
-    A_UINT32 pdev_up_time_us;
+    A_UINT32 pdev_up_time_us_low;
+    A_UINT32 pdev_up_time_us_high;
 } htt_tx_pdev_stats_cmn_tlv;
 
 #define HTT_TX_PDEV_STATS_URRN_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
@@ -4944,8 +4945,12 @@ typedef struct {
     htt_tlv_hdr_t tlv_hdr;
     /** Tx PPDU duration histogram **/
     A_UINT32 tx_ppdu_dur_hist[HTT_PDEV_STATS_PPDU_DUR_HIST_BINS];
-    A_UINT32 tx_success_time_us;
-    A_UINT32 tx_fail_time_us;
+    A_UINT32 tx_success_time_us_low;
+    A_UINT32 tx_success_time_us_high;
+    A_UINT32 tx_fail_time_us_low;
+    A_UINT32 tx_fail_time_us_high;
+    A_UINT32 pdev_up_time_us_low;
+    A_UINT32 pdev_up_time_us_high;
 } htt_tx_pdev_ppdu_dur_stats_tlv;
 
 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_RATE

From bedbf533fcb788d7eb7643abf3400af80c193747 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 29 Sep 2022 18:00:57 -0700
Subject: [PATCH 05/21] fw-api: CL 19770426 - update fw common interface files

HTT stats: add txbf_flags counters to tx_pdev_txbf_rate_stats TLV

Change-Id: I4eecc316d72ad434050f978dd0d1dcc4484d2cd8
CRs-Fixed: 2262693
---
 fw/htt_stats.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 9d8fe4d7e3bb..20285594ef86 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -6820,6 +6820,15 @@ typedef struct {
     A_UINT32 reduced_tx_su_ibf_bw[HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS];
     /** Open loop TX BW stats */
     A_UINT32 reduced_tx_su_ol_bw[HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS];
+    /** Txbf flag reason stats */
+    A_UINT32 txbf_flag_set_mu_mode;
+    A_UINT32 txbf_flag_set_final_status;
+    A_UINT32 txbf_flag_not_set_verified_txbf_mode;
+    A_UINT32 txbf_flag_not_set_disable_p2p_access;
+    A_UINT32 txbf_flag_not_set_max_nss_reached_in_he160;
+    A_UINT32 txbf_flag_not_set_disable_ul_dl_ofdma;
+    A_UINT32 txbf_flag_not_set_mcs_threshold_value;
+    A_UINT32 txbf_flag_not_set_final_status;
 } htt_tx_pdev_txbf_rate_stats_tlv;
 
 typedef enum {

From ad6b018fce71a2a082bed3af1f2980836e6cff64 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 1 Oct 2022 06:00:51 -0700
Subject: [PATCH 06/21] fw-api: CL 19790556 - update fw common interface files

HTT stats: add MU MIMO+OFDMA EDCA aggressiveness counters

Change-Id: I41f9b70f3f250616fac9d88dc1a7f2573039db79
CRs-Fixed: 2262693
---
 fw/htt.h       |  1 +
 fw/htt_stats.h | 12 ++++++++++++
 2 files changed, 13 insertions(+)

diff --git a/fw/htt.h b/fw/htt.h
index caf26cec514a..3b8519400eb1 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -760,6 +760,7 @@ typedef enum {
     HTT_STATS_LATENCY_PROF_CAL_STATS_TAG           = 168, /* htt_latency_prof_cal_stats_tlv */
     HTT_STATS_TX_PDEV_MUEDCA_PARAMS_STATS_TAG      = 169, /* htt_tx_pdev_muedca_params_stats_tlv_v */
     HTT_STATS_PDEV_BW_MGR_STATS_TAG                = 170, /* htt_pdev_bw_mgr_stats_tlv */
+    HTT_STATS_TX_PDEV_AP_EDCA_PARAMS_STATS_TAG     = 171, /* htt_tx_pdev_ap_edca_params_stats_tlv_v */
 
 
     HTT_STATS_MAX_TAG,
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 20285594ef86..cb8707f1558e 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -947,6 +947,18 @@ typedef struct {
     A_UINT32 cw_max[HTT_NUM_AC_WMM][HTT_STATS_MUEDCA_VALUE_MAX];
 } htt_tx_pdev_muedca_params_stats_tlv_v;
 
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    A_UINT32 ul_mumimo_less_aggressive[HTT_NUM_AC_WMM];
+    A_UINT32 ul_mumimo_medium_aggressive[HTT_NUM_AC_WMM];
+    A_UINT32 ul_mumimo_highly_aggressive[HTT_NUM_AC_WMM];
+    A_UINT32 ul_mumimo_default_relaxed[HTT_NUM_AC_WMM];
+    A_UINT32 ul_muofdma_less_aggressive[HTT_NUM_AC_WMM];
+    A_UINT32 ul_muofdma_medium_aggressive[HTT_NUM_AC_WMM];
+    A_UINT32 ul_muofdma_highly_aggressive[HTT_NUM_AC_WMM];
+    A_UINT32 ul_muofdma_default_relaxed[HTT_NUM_AC_WMM];
+} htt_tx_pdev_ap_edca_params_stats_tlv_v;
+
 #define HTT_TX_PDEV_SIFS_BURST_HIST_STATS 10
 #define HTT_TX_PDEV_STATS_SIFS_HIST_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
 /* NOTE: Variable length TLV, use length spec to infer array size */

From c18f9c54e0413df7db31a13ba9fd5de6b2634a68 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 1 Oct 2022 06:01:43 -0700
Subject: [PATCH 07/21] fw-api: CL 19791172 - update fw common interface files

Change-Id: Ib89e9f306ac73c47ca84c50d163ceabfc7a0b965
WMI: add event_cause flag to OEM_DATA_EVENT msg
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 19 +++++++++++++++----
 fw/wmi_version.h |  2 +-
 2 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 465ed92119ca..1066e154a234 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -33118,10 +33118,13 @@ typedef enum {
      *    specified time then FW will indicate host to stop TX since
      *    there are no lower power mode available.
      */
-    WMI_AFC_EXPIRY_EVENT_START         = 1,
-    WMI_AFC_EXPIRY_EVENT_RENEW         = 2,
-    WMI_AFC_EXPIRY_EVENT_SWITCH_TO_LPI = 3,
-    WMI_AFC_EXPIRY_EVENT_STOP_TX       = 4,
+    WMI_AFC_EXPIRY_EVENT_START                    = 1,
+    WMI_AFC_EXPIRY_EVENT_RENEW                    = 2,
+    WMI_AFC_EXPIRY_EVENT_SWITCH_TO_LOW_POWER_MODE = 3,
+        /* retain the deprecated old name as an alias for the new name */
+        WMI_AFC_EXPIRY_EVENT_SWITCH_TO_LPI =
+            WMI_AFC_EXPIRY_EVENT_SWITCH_TO_LOW_POWER_MODE,
+    WMI_AFC_EXPIRY_EVENT_STOP_TX                  = 4,
 } WMI_AFC_EXPIRY_EVENT_SUBTYPE;
 
 typedef enum {
@@ -38680,9 +38683,17 @@ typedef struct {
  */
 } wmi_cfr_capture_filter_cmd_fixed_param;
 
+enum wmi_oem_data_evt_cause {
+    WMI_OEM_DATA_EVT_CAUSE_UNSPECIFIED = 0,
+    WMI_OEM_DATA_EVT_CAUSE_CMD_REQ = 1,
+    WMI_OEM_DATA_EVT_CAUSE_ASYNC = 2,
+};
+
 typedef struct {
     A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_oem_data_event_fixed_param */
     A_UINT32 data_len; /** length in byte of data[]. */
+    /* Event Cause reason from enum wmi_oem_data_evt_cause */
+    A_UINT32 event_cause;
 /* Following this structure is the TLV:
  *      A_UINT8 data[]; <-- length in byte given by field data_len.
  * This data array contains OEM data, the payload begins with a field to tell the HOST regarding the kind of the OEM data.
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 8f968e68319e..f3b0cc70c71d 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1217
+#define __WMI_REVISION_ 1218
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 38752d37399939598db09f5940181bd6aa630734 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 5 Oct 2022 06:00:50 -0700
Subject: [PATCH 08/21] fw-api: CL 19822308 - update fw common interface files

Change-Id: If655723bf9619809492e88b35b2d551e48254f00
HTT: add more word_mask fields in htt_tx_monitor_cfg_t
CRs-Fixed: 2262693
---
 fw/htt.h | 65 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 64 insertions(+), 1 deletion(-)

diff --git a/fw/htt.h b/fw/htt.h
index 3b8519400eb1..55ceb9cb8c5e 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -234,9 +234,10 @@
  * 3.107 Add traffic_end_indication bitfield in htt_tx_msdu_desc_ext2_t.
  * 3.108 Add HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP def.
  * 3.109 Add HTT_T2H RX_ADDBA_EXTN,RX_DELBA_EXTN defs.
+ * 3.110 Add more word_mask fields in htt_tx_monitor_cfg_t.
  */
 #define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 109
+#define HTT_CURRENT_VERSION_MINOR 110
 
 #define HTT_NUM_TX_FRAG_DESC  1024
 
@@ -6962,6 +6963,13 @@ PREPACK struct htt_tx_monitor_cfg_t {
              dma_mpdu_ctrl:                          1,
              dma_mpdu_data:                          1,
              rsvd4:                                 10;
+    A_UINT32 tx_queue_ext_v2_word_mask:             12,
+             tx_peer_entry_v2_word_mask:            12,
+             rsvd5:                                 10;
+    A_UINT32 fes_status_end_word_mask:              16,
+             response_end_status_word_mask:         16;
+    A_UINT32 fes_status_prot_word_mask:             11,
+             rsvd6:                                 21;
 } POSTPACK;
 
 #define HTT_TX_MONITOR_CFG_SZ    (sizeof(struct htt_tx_monitor_cfg_t))
@@ -7340,6 +7348,61 @@ PREPACK struct htt_tx_monitor_cfg_t {
                 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_S)); \
             } while (0)
 
+#define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_M          0x00000fff
+#define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_S          0
+#define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_GET(_var) \
+            (((_var) & HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_M) >> \
+                    HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_S)
+#define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK, _val); \
+                ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_S)); \
+            } while (0)
+
+#define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_M         0x00fff000
+#define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_S         12
+#define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_GET(_var) \
+            (((_var) & HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_M) >> \
+                    HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_S)
+#define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK, _val); \
+                ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_S)); \
+            } while (0)
+
+#define HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_M           0x0000ffff
+#define HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_S           0
+#define HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_GET(_var) \
+            (((_var) & HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_M) >> \
+                    HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_S)
+#define HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK, _val); \
+                ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_S)); \
+            } while (0)
+
+#define HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_M      0xffff0000
+#define HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_S      16
+#define HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_GET(_var) \
+            (((_var) & HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_M) >> \
+                    HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_S)
+#define HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK, _val); \
+                ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_S)); \
+            } while (0)
+
+#define HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_M          0x000007ff
+#define HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_S          0
+#define HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_GET(_var) \
+            (((_var) & HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_M) >> \
+                    HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_S)
+#define HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK, _val); \
+                ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_S)); \
+            } while (0)
+
 /*
  * pkt_type_enable_flags
  */

From 324cb3d0bd4ff6ce5b4c26b8ca0209e8ad2ec3b8 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 7 Oct 2022 06:00:55 -0700
Subject: [PATCH 09/21] fw-api: CL 19854370 - update fw common interface files

Change-Id: I5b94a0cf4fd20c8be3d24b1d588af7e791300ae3
WMI: define ODD_LIVEDUMP _REQUEST_CMD,_RESPONSE_EVENT msgs
CRs-Fixed: 2262693
---
 fw/wmi_services.h |  1 +
 fw/wmi_tlv_defs.h | 15 +++++++++++++++
 fw/wmi_unified.h  | 46 ++++++++++++++++++++++++++++++++++++++++++++++
 fw/wmi_version.h  |  2 +-
 4 files changed, 63 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 16753f676985..e066b1955614 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -601,6 +601,7 @@ typedef  enum  {
     WMI_SERVICE_OBSS_PER_PACKET_SR_SUPPORT = 348, /* Spatial Reuse support for per PPDU setting */
     WMI_SERVICE_MULTIPLE_VDEV_RESTART_BITMAP_SUPPORT = 349, /* Extended Multiple VDEV Restart with Bitmap Support */
     WMI_SERVICE_WMI_SERVICE_WPA3_SHA384_ROAM_SUPPORT = 350, /* Indicates FW supports WPA3 SHA384 roaming */
+    WMI_SERVICE_ODD_LIVEDUMP_SUPPORT = 351, /* Support for ODD Livedump from the FW */
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index c5f8a960fb3e..8d6dab6903ad 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1300,6 +1300,8 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_xgap_enable_complete_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_pdev_mesh_rx_filter_enable_fixed_param,
     WMITLV_TAG_STRUC_wmi_wfa_config_ofdma,
+    WMITLV_TAG_STRUC_wmi_livedump_request_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_livedump_response_event_fixed_param,
 } WMITLV_TAG_ID;
 
 /*
@@ -1809,6 +1811,7 @@ typedef enum {
     OP(WMI_VDEV_PARAM_ENABLE_SR_PROHIBIT_CMDID) \
     OP(WMI_XGAP_ENABLE_CMDID) \
     OP(WMI_PDEV_MESH_RX_FILTER_ENABLE_CMDID) \
+    OP(WMI_ODD_LIVEDUMP_REQUEST_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2103,6 +2106,7 @@ typedef enum {
     OP(WMI_IPA_LINK_STATS_EVENTID) \
     OP(WMI_PDEV_SCHED_TIDQ_SUSP_INFO_EVENTID) \
     OP(WMI_XGAP_ENABLE_COMPLETE_EVENTID) \
+    OP(WMI_ODD_LIVEDUMP_RESPONSE_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -5164,6 +5168,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_PARAM_ENABLE_SR_PROHIBIT_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_xgap_enable_cmd_fixed_param, wmi_xgap_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_XGAP_ENABLE_CMDID);
 
+#define WMITLV_TABLE_WMI_ODD_LIVEDUMP_REQUEST_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_livedump_request_cmd_fixed_param, wmi_livedump_request_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, odd_livedump_id_list, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_ODD_LIVEDUMP_REQUEST_CMDID);
+
 
 
 /************************** TLV definitions of WMI events *******************************/
@@ -7006,6 +7015,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_HEALTH_MON_INIT_DONE_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_xgap_enable_complete_event_fixed_param, wmi_xgap_enable_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_XGAP_ENABLE_COMPLETE_EVENTID);
 
+/* ODD Livedump */
+#define  WMITLV_TABLE_WMI_ODD_LIVEDUMP_RESPONSE_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_livedump_response_event_fixed_param, wmi_livedump_response_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_ODD_LIVEDUMP_RESPONSE_EVENTID);
+
+
 
 
 #ifdef __cplusplus
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 1066e154a234..f5cb9e760d5e 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -314,6 +314,7 @@ typedef enum {
     WMI_GRP_MLO,            /* 0x48 MLO(Multiple Link Operation) management */
     WMI_GRP_SAWF,           /* 0x49 SAWF (Service Aware WiFi) */
     WMI_GRP_QUIET_OFL,      /* 0x4a Quiet offloads */
+    WMI_GRP_ODD,            /* 0x4b ODD */
 } WMI_GRP_ID;
 
 #define WMI_CMD_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1)
@@ -1537,6 +1538,9 @@ typedef enum {
     /** disable a service class */
     WMI_SAWF_SVC_CLASS_DISABLE_CMDID,
 
+    /* WMI commands specific to ODD */
+    WMI_ODD_LIVEDUMP_REQUEST_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_ODD),
+
 } WMI_CMD_ID;
 
 typedef enum {
@@ -2330,6 +2334,9 @@ typedef enum {
 
     /* WMI event specific to Quiet handling */
     WMI_QUIET_HANDLING_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_QUIET_OFL),
+
+    /* ODD events */
+    WMI_ODD_LIVEDUMP_RESPONSE_EVENTID = WMI_CMD_GRP_START_ID(WMI_GRP_ODD),
 } WMI_EVT_ID;
 
 /* defines for OEM message sub-types */
@@ -40076,6 +40083,45 @@ typedef struct {
     A_UINT32 initial_upload_period_ms;
 } wmi_health_mon_init_done_fixed_param;
 
+/** ODD **/
+
+/* Livedump Data structures */
+#define WMI_ODD_LIVEDUMP_RESP_SET_STATUS(status, val) \
+    WMI_SET_BITS(status, 0, 4, val)
+#define WMI_ODD_LIVEDUMP_RESP_GET_STATUS(status) \
+    WMI_GET_BITS(status, 0, 4)
+
+typedef enum {
+    ODD_LIVEDUMP_STATUS_SUCCESS = 0,
+    ODD_LIVEDUMP_STATUS_FAILURE,
+    ODD_MAX_LIVEDUMP_STATUS,
+} odd_livedump_resp_status;
+
+typedef struct {
+    A_UINT32 tlv_header;
+    A_UINT32 odd_livedump_request_id;
+    /* Following this structure is the TLV:
+     *    A_UINT32 odd_livedump_id_list[]; <-- array livedump_id list
+     */
+} wmi_livedump_request_cmd_fixed_param;
+
+typedef struct {
+    A_UINT32 tlv_header;
+    /* odd_livedump_request_id:
+     * this echoes the request id that was sent in the wmi_livedump_cmd_param
+     */
+    A_UINT32 odd_livedump_request_id;
+    /*
+     * 4 LSB's to indicate status of the odd_livedump_request_id processed
+     * by the FW, the other 28bits to kept for future enhancements.
+     * The status will be defined in the enum odd_livedump_resp_status
+     * 0 - SUCCESS
+     * 1 - FAILURE
+     * Refer to the WMI_ODD_LIVEDUMP_RESP_SET,_GET_STATUS macros.
+     */
+    A_UINT32 status;
+} wmi_livedump_response_event_fixed_param;
+
 
 
 /* ADD NEW DEFS HERE */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index f3b0cc70c71d..0dd0787878e1 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1218
+#define __WMI_REVISION_ 1219
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 2dcfea06ae371b42c46fe9d26b361c16edef8d4b Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 8 Oct 2022 06:00:54 -0700
Subject: [PATCH 10/21] fw-api: CL 19868767 - update fw common interface files

add WMI_VENDOR1_REQ1_VERSION_3_30 def

Change-Id: I1db06cc8228d5a1962df48d5dfda8253b407a856
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 1 +
 fw/wmi_version.h | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index f5cb9e760d5e..29a893577472 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -4893,6 +4893,7 @@ typedef enum {
     WMI_VENDOR1_REQ1_VERSION_3_00   = 0,
     WMI_VENDOR1_REQ1_VERSION_3_01   = 1,
     WMI_VENDOR1_REQ1_VERSION_3_20   = 2,
+    WMI_VENDOR1_REQ1_VERSION_3_30   = 3,
 } WMI_VENDOR1_REQ1_VERSION;
 
 typedef enum {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 0dd0787878e1..1910cde93cf9 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1219
+#define __WMI_REVISION_ 1220
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From c9b1e51da1f66f7de1c1ba6d4703b07ce57d87c1 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Mon, 17 Oct 2022 18:00:55 -0700
Subject: [PATCH 11/21] fw-api: CL 19912349 - update fw common interface files

Change-Id: Ie3bcf21dbdfa557b4d7ac550a9b6079463d84bba
WMI: add BDF compatibility result to service_ready_ext2 msg
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 21 ++++++++++++++++++++-
 fw/wmi_version.h |  2 +-
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 29a893577472..9f36d96293b6 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -2336,7 +2336,7 @@ typedef enum {
     WMI_QUIET_HANDLING_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_QUIET_OFL),
 
     /* ODD events */
-    WMI_ODD_LIVEDUMP_RESPONSE_EVENTID = WMI_CMD_GRP_START_ID(WMI_GRP_ODD),
+    WMI_ODD_LIVEDUMP_RESPONSE_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_ODD),
 } WMI_EVT_ID;
 
 /* defines for OEM message sub-types */
@@ -3282,6 +3282,20 @@ typedef enum {
     WMI_AFC_FEATURE_6G_DEPLOYMENT_OUTDOOR_ONLY = 2,
 } WMI_AFC_FEATURE_6G_DEPLOYMENT_TYPE;
 
+typedef enum {
+    WMI_BDF_VERSION_OK = 0,
+
+    /* WMI_BDF_VERSION_TOO_OLD:
+     * BDF version is older than the oldest version supported by FW.
+     */
+    WMI_BDF_VERSION_TOO_OLD = 1,
+
+    /* WMI_BDF_VERSION_TOO_NEW:
+     * BDF version is newer than the newest version supported by FW.
+     */
+    WMI_BDF_VERSION_TOO_NEW = 2,
+} wmi_hw_bd_status_type;
+
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_service_ready_ext2_event_fixed_param.*/
 
@@ -3401,6 +3415,11 @@ typedef struct {
      */
     A_UINT32 afc_deployment_type;
 
+    /*
+     * Board data check report. Please see wmi_hw_bd_status_type enum values.
+     */
+    A_UINT32 hw_bd_status;
+
     /* Followed by next TLVs:
      *     WMI_DMA_RING_CAPABILITIES          dma_ring_caps[];
      *     wmi_spectral_bin_scaling_params    wmi_bin_scaling_params[];
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 1910cde93cf9..fa9fcc897a5e 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1220
+#define __WMI_REVISION_ 1221
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From a23fccec8fb39af8771004005e0bebd85d180621 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Mon, 17 Oct 2022 18:01:33 -0700
Subject: [PATCH 12/21] fw-api: CL 19971866 - update fw common interface files

HTT stats: add AX,BE OFDMA RBO,SIFS steer counters

Change-Id: I230f4dd06cc08456c1f3a4afe22f8174e421d738
CRs-Fixed: 2262693
---
 fw/htt.h       |  2 ++
 fw/htt_stats.h | 26 ++++++++++++++++++++++++++
 2 files changed, 28 insertions(+)

diff --git a/fw/htt.h b/fw/htt.h
index 55ceb9cb8c5e..67c187debdcc 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -762,6 +762,8 @@ typedef enum {
     HTT_STATS_TX_PDEV_MUEDCA_PARAMS_STATS_TAG      = 169, /* htt_tx_pdev_muedca_params_stats_tlv_v */
     HTT_STATS_PDEV_BW_MGR_STATS_TAG                = 170, /* htt_pdev_bw_mgr_stats_tlv */
     HTT_STATS_TX_PDEV_AP_EDCA_PARAMS_STATS_TAG     = 171, /* htt_tx_pdev_ap_edca_params_stats_tlv_v */
+    HTT_STATS_TXBF_OFDMA_AX_STEER_MPDU_STATS_TAG   = 172, /* htt_txbf_ofdma_ax_steer_mpdu_stats_tlv */
+    HTT_STATS_TXBF_OFDMA_BE_STEER_MPDU_STATS_TAG   = 173, /* htt_txbf_ofdma_be_steer_mpdu_stats_tlv */
 
 
     HTT_STATS_MAX_TAG,
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index cb8707f1558e..1c48ab8b2796 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -2672,6 +2672,18 @@ typedef struct {
     htt_txbf_ofdma_ax_steer_stats_elem_t ax_steer[1]; /* variable length */
 } htt_txbf_ofdma_ax_steer_stats_tlv;
 
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /* 11AX HE OFDMA MPDUs tried in rbo steering */
+    A_UINT32 ax_ofdma_rbo_steer_mpdus_tried;
+    /* 11AX HE OFDMA MPDUs failed in rbo steering */
+    A_UINT32 ax_ofdma_rbo_steer_mpdus_failed;
+    /* 11AX HE OFDMA MPDUs tried in sifs steering */
+    A_UINT32 ax_ofdma_sifs_steer_mpdus_tried;
+    /* 11AX HE OFDMA MPDUs failed in sifs steering */
+    A_UINT32 ax_ofdma_sifs_steer_mpdus_failed;
+} htt_txbf_ofdma_ax_steer_mpdu_stats_tlv;
+
 typedef struct {
     /** 11BE EHT OFDMA NDPA frame queued to the HW */
     A_UINT32 be_ofdma_ndpa_queued;
@@ -2806,16 +2818,30 @@ typedef struct {
     htt_txbf_ofdma_be_steer_stats_elem_t be_steer[1]; /* variable length */
 } htt_txbf_ofdma_be_steer_stats_tlv;
 
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /* 11BE EHT OFDMA MPDUs tried in rbo steering */
+    A_UINT32 be_ofdma_rbo_steer_mpdus_tried;
+    /* 11BE EHT OFDMA MPDUs failed in rbo steering */
+    A_UINT32 be_ofdma_rbo_steer_mpdus_failed;
+    /* 11BE EHT OFDMA MPDUs tried in sifs steering */
+    A_UINT32 be_ofdma_sifs_steer_mpdus_tried;
+    /* 11BE EHT OFDMA MPDUs failed in sifs steering */
+    A_UINT32 be_ofdma_sifs_steer_mpdus_failed;
+} htt_txbf_ofdma_be_steer_mpdu_stats_tlv;
+
 /* STATS_TYPE : HTT_DBG_EXT_STATS_TXBF_OFDMA
  * TLV_TAGS:
  *      - HTT_STATS_TXBF_OFDMA_NDPA_STATS_TAG
  *      - HTT_STATS_TXBF_OFDMA_NDP_STATS_TAG
  *      - HTT_STATS_TXBF_OFDMA_BRP_STATS_TAG
  *      - HTT_STATS_TXBF_OFDMA_STEER_STATS_TAG
+ *      - HTT_STATS_TXBF_OFDMA_AX_STEER_MPDU_STATS_TAG
  *      - HTT_STATS_TXBF_OFDMA_BE_NDPA_STATS_TAG
  *      - HTT_STATS_TXBF_OFDMA_BE_NDP_STATS_TAG
  *      - HTT_STATS_TXBF_OFDMA_BE_BRP_STATS_TAG
  *      - HTT_STATS_TXBF_OFDMA_BE_STEER_STATS_TAG
+ *      - HTT_STATS_TXBF_OFDMA_BE_STEER_MPDU_STATS_TAG
  */
 
 typedef struct {

From 96838b6a84fb336ebcadc3a210f0c630446cf191 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Mon, 17 Oct 2022 18:02:18 -0700
Subject: [PATCH 13/21] fw-api: CL 19972886 - update fw common interface files

Change-Id: I4b47327f740ad16ecc9678bc25187bd60dfbafe8
WMI: add prb_resp_tmpl_ml_info in PRB_TMPL_CMD msg
CRs-Fixed: 2262693
---
 fw/wmi_tlv_defs.h |  4 +++-
 fw/wmi_unified.h  | 20 ++++++++++++++++++++
 fw/wmi_version.h  |  2 +-
 3 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 8d6dab6903ad..662fe53da422 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1302,6 +1302,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_wfa_config_ofdma,
     WMITLV_TAG_STRUC_wmi_livedump_request_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_livedump_response_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_prb_resp_tmpl_ml_info,
 } WMITLV_TAG_ID;
 
 /*
@@ -2542,7 +2543,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_STA_UAPSD_AUTO_TRIG_CMDID);
 #define WMITLV_TABLE_WMI_PRB_TMPL_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_prb_tmpl_cmd_fixed_param, wmi_prb_tmpl_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_bcn_prb_info, wmi_bcn_prb_info, bcn_prb_info, WMITLV_SIZE_FIX) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_prb_resp_tmpl_ml_info, ml_prb_resp_info, WMITLV_SIZE_VAR)
 
 WMITLV_CREATE_PARAM_STRUC(WMI_PRB_TMPL_CMDID);
 
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 9f36d96293b6..c8b1a662fa5e 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -15499,6 +15499,26 @@ typedef struct {
 #define WMI_BEACON_PROTECTION_EN_GET(param) \
     WMI_GET_BITS(param, WMI_BEACON_PROTECTION_BIT_POS, 1)
 
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_prb_resp_tmpl_ml_info */
+    /** hw_link_id:
+     * Unique link id across SOCs, got as part of QMI handshake
+     */
+    A_UINT32 hw_link_id;
+    /**
+     * CU vdev map for the Critical update category-1
+     * (Inclusion of CU IES)
+     */
+    A_UINT32 cu_vdev_map_cat1_lo; /* bits 31:0 */
+    A_UINT32 cu_vdev_map_cat1_hi; /* bits 63:32 */
+    /**
+     * CU vdev map for the Critical update category-2
+     * (modification of CU IES)
+     */
+    A_UINT32 cu_vdev_map_cat2_lo; /* bits 31:0 */
+    A_UINT32 cu_vdev_map_cat2_hi; /* bits 63:32 */
+} wmi_prb_resp_tmpl_ml_info;
+
 typedef struct {
     A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_prb_tmpl_cmd_fixed_param */
     /** unique id identifying the VDEV, generated by the caller */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index fa9fcc897a5e..5693cb244a67 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1221
+#define __WMI_REVISION_ 1222
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From c706b8af2d4bbd733fa16e8fc073b478550bff58 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 20 Oct 2022 06:00:59 -0700
Subject: [PATCH 14/21] fw-api: CL 20018278 - update fw common interface files

Add WLAN_MODULE_MLO_OWNERSHIP_UPDATE module ID def

Change-Id: Id3eda50a246068f0bc544d1051b47d8ffcda3093
CRs-Fixed: 2262693
---
 fw/wlan_module_ids.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/fw/wlan_module_ids.h b/fw/wlan_module_ids.h
index 13fc6b8fba44..97ec58fd0624 100644
--- a/fw/wlan_module_ids.h
+++ b/fw/wlan_module_ids.h
@@ -139,6 +139,7 @@ typedef enum {
   WLAN_MODULE_T2LM,                     /* 0x64 */
   WLAN_MODULE_HEALTH_MON,               /* 0x65 */
   WLAN_MODULE_XGAP,                     /* 0x66 */
+  WLAN_MODULE_MLO_OWNERSHIP_UPDATE,     /* 0x67 */
 
 
   WLAN_MODULE_ID_MAX,

From 32170befc628c6c653e9957e2c3b9852ebc916bc Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 21 Oct 2022 12:00:52 -0700
Subject: [PATCH 15/21] fw-api: CL 20040821 - update fw common interface files

add WMI_SERVICE_EIRP_PREFERRED_SUPPORT def

Change-Id: I050b7a04f2ed17f6e9425c3c80150ef5fc710233
CRs-Fixed: 2262693
---
 fw/wmi_services.h | 1 +
 fw/wmi_version.h  | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index e066b1955614..fc2b7539c3c9 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -602,6 +602,7 @@ typedef  enum  {
     WMI_SERVICE_MULTIPLE_VDEV_RESTART_BITMAP_SUPPORT = 349, /* Extended Multiple VDEV Restart with Bitmap Support */
     WMI_SERVICE_WMI_SERVICE_WPA3_SHA384_ROAM_SUPPORT = 350, /* Indicates FW supports WPA3 SHA384 roaming */
     WMI_SERVICE_ODD_LIVEDUMP_SUPPORT = 351, /* Support for ODD Livedump from the FW */
+    WMI_SERVICE_EIRP_PREFERRED_SUPPORT = 352, /* Support for OOBE feature where only EIRP powers will be sent in 6G TPC WMI */
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 5693cb244a67..8d5e34213b8d 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1222
+#define __WMI_REVISION_ 1223
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 9af1257ebb1557b4bfe205d8044b98c9befe9cc4 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 26 Oct 2022 12:00:58 -0700
Subject: [PATCH 16/21] fw-api: CL 20071754 - update fw common interface files

wlanfw_cmn: fix spelling errors in code comments
Fix spelling errors in code comments within the .h files that define the host/target interface.

Change-Id: I98c7b607238adacf7b8615b60ffb3bcef482815a
CRs-Fixed: 2262693
---
 fw/htt.h            |  45 +++---
 fw/htt_common.h     |   3 +-
 fw/htt_isoc.h       |   3 +-
 fw/htt_ppdu_stats.h |   4 +-
 fw/htt_stats.h      |  56 +++----
 fw/wdi_ipa.h        |   3 +-
 fw/wlan_defs.h      |  20 +--
 fw/wmi.h            |   5 +-
 fw/wmi_services.h   |  10 +-
 fw/wmi_tlv_defs.h   |   8 +-
 fw/wmi_unified.h    | 378 ++++++++++++++++++++++----------------------
 11 files changed, 270 insertions(+), 265 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index 67c187debdcc..f94aad50ab84 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -421,7 +421,7 @@ PREPACK struct htt_option_tlv_ll_bus_addr_size_t {
  * downloads over the host --> target bus are as slow as or slower than
  * the transmissions over the WLAN PHY.  For cases where the bus is faster
  * than the WLAN PHY, the target will transmit relatively large A-MPDUs,
- * and consquently will send one TX_COMPL_IND message that covers several
+ * and consequently will send one TX_COMPL_IND message that covers several
  * tx frames.  For cases where the WLAN PHY is faster than the bus,
  * the target will end up transmitting very short A-MPDUs, and consequently
  * sending many TX_COMPL_IND messages, which each cover a very small number
@@ -464,7 +464,7 @@ PREPACK struct htt_option_tlv_hl_suppress_tx_compl_ind_t {
  * The MAX_TX_QUEUE_GROUPS TLV can be sent from the target to the host as
  * a suffix to the VERSION_CONF message.  If the host has specified in the
  * VER_REQ message a limit on the number of tx queue groups the host can
- * supprt, the target shall limit its specification of the maximum tx groups
+ * support, the target shall limit its specification of the maximum tx groups
  * to be no larger than this host-specified limit.
  *
  * If the target does not provide a MAX_TX_QUEUE_GROUPS TLV, then the host
@@ -1135,7 +1135,7 @@ PREPACK struct htt_tx_msdu_desc ## _paddr_bits_ ## _t                          \
         A_UINT16 chanfreq;                                                     \
                                                                                \
         /* Reason reserved is commented is increasing the htt structure size   \
-         * leads to some wierd issues. Contact Raj/Kyeyoon for more info       \
+         * leads to some weird issues.                                         \
          * A_UINT32 reserved_dword3_bits0_31;                                  \
          */                                                                    \
 } POSTPACK
@@ -2720,7 +2720,7 @@ typedef enum {
 /**
  * @brief HTT TX WBM Completion from firmware to host
  * @details
- *  This structure is passed from firmware to host overlayed on wbm_release_ring
+ *  This structure is passed from firmware to host overlaid on wbm_release_ring
  *  DWORD 3 and 4 for software based completions (Exception frames and
  *  TQM bypass frames)
  *  For software based completions, wbm_release_ring->release_source_module will
@@ -2813,7 +2813,7 @@ PREPACK struct htt_tx_wbm_completion {
  * @details
  *  This structure applies only to WLAN chips that contain WLAN Buffer Mgmt
  *  (WBM) offload HW.
- *  This structure is passed from firmware to host overlayed on wbm_release_ring
+ *  This structure is passed from firmware to host overlaid on wbm_release_ring
  *  For software based completions, release_source_module will
  *  be set to WIFIRELEASE_SOURCE_FW_E. Host SW is expected to inspect using
  *  struct wbm_release_ring and then switch to this after looking at
@@ -2892,7 +2892,7 @@ PREPACK struct htt_tx_wbm_completion_v2 {
  * @details
  *  This structure applies only to WLAN chips that contain WLAN Buffer Mgmt
  *  (WBM) offload HW.
- *  This structure is passed from firmware to host overlayed on wbm_release_ring
+ *  This structure is passed from firmware to host overlaid on wbm_release_ring
  *  For software based completions, release_source_module will
  *  be set to WIFIRELEASE_SOURCE_FW_E. Host SW is expected to inspect using
  *  struct wbm_release_ring and then switch to this after looking at
@@ -2979,7 +2979,7 @@ typedef enum {
  * @details
  *  This structure applies only to WLAN chips that contain WLAN Buffer Mgmt
  *  (WBM) offload HW.
- *  This structure is passed from firmware to host overlayed on wbm_release_ring.
+ *  This structure is passed from firmware to host overlaid on wbm_release_ring.
  *  used only if tx_status is HTT_TX_FW2WBM_TX_STATUS_OK or HTT_TX_FW2WBM_TX_STATUS_DROP
  *  or HTT_TX_FW2WBM_TX_STATUS_TTL
  */
@@ -3110,7 +3110,7 @@ PREPACK struct htt_tx_wbm_transmit_status {
  * @details
  *  This structure applies only to WLAN chips that contain WLAN Buffer Mgmt
  *  (WBM) offload HW.
- *  This structure is passed from firmware to host overlayed on wbm_release_ring.
+ *  This structure is passed from firmware to host overlaid on wbm_release_ring.
  *  used only if tx_status is HTT_TX_FW2WBM_TX_STATUS_REINJECT.
  */
 PREPACK struct htt_tx_wbm_reinject_status {
@@ -3127,7 +3127,7 @@ PREPACK struct htt_tx_wbm_reinject_status {
  * @details
  *  This structure applies only to WLAN chips that contain WLAN Buffer Mgmt
  *  (WBM) offload HW.
- *  This structure is passed from firmware to host overlayed on wbm_release_ring.
+ *  This structure is passed from firmware to host overlaid on wbm_release_ring.
  *  used only if tx_status is HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY.
  *  FW sends SA addresses to host for all multicast/broadcast packets received on
  *  STA side.
@@ -5134,7 +5134,7 @@ enum htt_msi_setup_type {
  *                     3'b010: 4 usec
  *                     3'b011: 8 usec (default)
  *                     3'b100: 16 usec
- *                     Others: Reserverd
+ *                     Others: Reserved
  *           b'19    - response_required:
  *                     Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response
  *           b'20    - ipa_drop_flag:
@@ -8317,7 +8317,7 @@ enum htt_ip_da_sa_prefix {
  *          b'9     - DISABLE_TA_CHECK: 1- Disable TA check for MPDU Sequence
  *                    num jump
  *          b'10    - DISABLE_QOS_CHECK: 1- Disable checking if qos/nonqos
- *            data type switch has happend for MPDU Sequence num jump
+ *            data type switch has happened for MPDU Sequence num jump
  *          b'11    - DISABLE_RAW_CHECK: 1- Disable checking for raw packet type
  *            for MPDU Sequence num jump
  *          b'12    - DISABLE_DECRYPT_ERR_CHECK: 1- Disable fisa cache commands
@@ -12112,7 +12112,7 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
  * In certain generations of chips, the peer map message also contains
  * a HW peer ID.  This HW peer ID is used during rx --> tx frame forwarding
  * to identify which peer the frame needs to be forwarded to (i.e. the
- * peer assocated with the Destination MAC Address within the packet),
+ * peer associated with the Destination MAC Address within the packet),
  * and particularly which vdev needs to transmit the frame (for cases
  * of inter-vdev rx --> tx forwarding). The HW peer id here is the same
  * meaning as AST_INDEX_0.
@@ -12255,7 +12255,7 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
  *
  * The peer map v2 message also contains a HW peer ID.  This HW peer ID
  * is used during rx --> tx frame forwarding to identify which peer the
- * frame needs to be forwarded to (i.e. the peer assocated with the
+ * frame needs to be forwarded to (i.e. the peer associated with the
  * Destination MAC Address within the packet), and particularly which vdev
  * needs to transmit the frame (for cases of inter-vdev rx --> tx forwarding).
  * This DA-based peer ID that is provided for certain rx frames
@@ -13891,7 +13891,7 @@ PREPACK struct htt_txq_group {
  *   Purpose: Indicate whether data ACK RSSI is appended for each MSDU in
  *            TX_COMP_IND message.  The order of the per-MSDU ACK RSSI report
  *            matches the order of the MSDU IDs.  Although the ACK RSSI is the
- *            same for all MSDUs witin a single PPDU, the RSSI is duplicated
+ *            same for all MSDUs within a single PPDU, the RSSI is duplicated
  *            for each MSDU, for convenience.
  *            The ACK RSSI values are valid when status is COMPLETE_OK (and
  *            this append2 bit is set).
@@ -14526,7 +14526,7 @@ typedef struct {
  *     Purpose: indicate how many 32-bit integers follow the message header
  *   - NUM_CHARS
  *     Bits 31:16
- *     Purpose: indicate how many 8-bit charaters follow the series of integers
+ *     Purpose: indicate how many 8-bit characters follow the series of integers
  */
 #define HTT_RX_TEST_NUM_INTS_M   0xff00
 #define HTT_RX_TEST_NUM_INTS_S   8
@@ -14729,7 +14729,7 @@ struct rx_reorder_stats {
     A_UINT32 rxdesc_bmc_msdus_inv_peer;
     /* Number of MSDUs dropped due to no first MSDU flag */
     A_UINT32 rxdesc_no_1st_msdu;
-    /* Number of MSDUs droped due to ring overflow */
+    /* Number of MSDUs dropped due to ring overflow */
     A_UINT32 msdu_drop_ring_ov;
     /* Number of MSDUs dropped due to FC mismatch */
     A_UINT32 msdu_drop_fc_mismatch;
@@ -16678,7 +16678,7 @@ typedef enum {
  *
  *  b'0:15  - flow pool ID: Existing flow pool ID
  *
- *  b'16:31 - flow pool new size: new pool size for exisiting flow pool ID
+ *  b'16:31 - flow pool new size: new pool size for existing flow pool ID
  *
  */
 
@@ -17307,7 +17307,7 @@ PREPACK struct htt_cfr_dump_compl_ind {
  *  subsequent period (100 ms) as long as the backpressure remains unabated.
  *  This message indicates the ring id along with current head and tail index
  *  locations (i.e. write and read indices).
- *  The backpressure time indicates the time in ms for which continous
+ *  The backpressure time indicates the time in ms for which continuous
  *  backpressure has been observed in the ring.
  *
  *  The message format is as follows:
@@ -17326,11 +17326,12 @@ PREPACK struct htt_cfr_dump_compl_ind {
  *                               (HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND)
  *           b'8:15  - pdev_id:  0 indicates msg is for UMAC ring.
  *                               1, 2, 3 indicates pdev_id 0,1,2 and
-                                 the msg is for LMAC ring.
+ *                               the msg is for LMAC ring.
  *           b'16:23 - ring_type: Refer to enum htt_backpressure_ring_type.
  *           b'24:31 - ring_id:  Refer enum htt_backpressure_umac_ring_id/
  *                               htt_backpressure_lmac_ring_id. This represents
- *                               the ring id for which continous backpressure is seen
+ *                               the ring id for which continuous backpressure
+ *                               is seen
  *
  *  dword1 - b'0:15  - head_idx: This indicates the current head index of
  *                               the ring indicated by the ring_id
@@ -17338,7 +17339,7 @@ PREPACK struct htt_cfr_dump_compl_ind {
  *  dword1 - b'16:31 - tail_idx: This indicates the current tail index of
  *                               the ring indicated by the ring id
  *
- *  dword2 - b'0:31  - backpressure_time_ms: Indicates how long continous
+ *  dword2 - b'0:31  - backpressure_time_ms: Indicates how long continuous
  *                               backpressure has been seen in the ring
  *                               indicated by the ring_id.
  *                               Units = milliseconds
@@ -17846,7 +17847,7 @@ enum HTT_UL_OFDMA_TRIG_TYPE {
  *     Bits 31:16
  *     Purpose: indicates the secondary channel center frequency,
  *              only for 11acvht 80plus80 mode
- *     Value:  secondary channel center frequeny, in MHz units, if applicable
+ *     Value:  secondary channel center frequency, in MHz units, if applicable
  *
  * checksum field
  *   - CHECK_SUM
diff --git a/fw/htt_common.h b/fw/htt_common.h
index aa7c87c41f32..0a6c4ed1a2c5 100644
--- a/fw/htt_common.h
+++ b/fw/htt_common.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2012-2016, 2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  *
  * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
  *
@@ -62,7 +63,7 @@ enum htt_rx_ind_mpdu_status {
     HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER,
     HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, /* only accept EAPOL frames */
     HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC,
-    HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, /* Non-data in promiscous mode */
+    HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, /* Non-data in promiscuous mode */
     HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR,
     HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR,
     HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR,
diff --git a/fw/htt_isoc.h b/fw/htt_isoc.h
index f478935626ac..175d55f77b54 100644
--- a/fw/htt_isoc.h
+++ b/fw/htt_isoc.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2012-2014 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  *
  * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
  *
@@ -237,7 +238,7 @@ enum {
  *   - RMF_ENABLED (R)
  *     Bit 6
  *     Purpose: specify whether the peer in question has enable robust
- *         management frames, to encrypt certain managment frames
+ *         management frames, to encrypt certain management frames
  *     Value: HTT_ISOC_RMF enum
  *     Value: HTT_ISOC_NON_QOS or HTT_ISOC_QOS
  *   - VDEV_ID
diff --git a/fw/htt_ppdu_stats.h b/fw/htt_ppdu_stats.h
index 50f5f8f26207..d5555a12955d 100644
--- a/fw/htt_ppdu_stats.h
+++ b/fw/htt_ppdu_stats.h
@@ -2732,7 +2732,7 @@ typedef struct {
      * The size of the actual mgmt payload (in bytes) can be obtained from
      * the frame_length field.
      * The size of entire payload including the padding for alignment
-     * (in bytes) can be derived from the length in tlv parametes,
+     * (in bytes) can be derived from the length in tlv parameters,
      * minus the 12 bytes of the above fields.
      */
     A_UINT32 payload[1];
@@ -2774,7 +2774,7 @@ typedef struct {
      * The size of the actual mgmt payload (in bytes) can be obtained from
      * the frame_length field.
      * The size of entire payload including the padding for alignment
-     * (in bytes) can be derived from the length in tlv parametes,
+     * (in bytes) can be derived from the length in tlv parameters,
      * minus the 12 bytes of the above fields.
      */
     A_UINT32 payload[1];
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 1c48ab8b2796..1c237bede021 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -1954,7 +1954,7 @@ typedef struct {
     A_UINT32      mu_mimo_mpdus_failed_usr;
     /** 11AC DL MU MIMO number of mpdus re-queued to HW, per user */
     A_UINT32      mu_mimo_mpdus_requeued_usr;
-    /** 11AC DL MU MIMO BA not receieved, per user */
+    /** 11AC DL MU MIMO BA not received, per user */
     A_UINT32      mu_mimo_err_no_ba_usr;
     /** 11AC DL MU MIMO mpdu underrun encountered, per user */
     A_UINT32      mu_mimo_mpdu_underrun_usr;
@@ -2097,7 +2097,7 @@ typedef struct {
     A_UINT32 mpdu_ack_fail_cnt;
     /** This will include sched cmd flush and time based discard */
     A_UINT32 mpdu_filt_cnt;
-    /** Number of MPDUs for which ACK was sucessful but no Tx happened */
+    /** Number of MPDUs for which ACK was successful but no Tx happened */
     A_UINT32 false_mpdu_ack_count;
 
     /** Number of times txq timeout happened */
@@ -2169,7 +2169,7 @@ typedef struct {
  * completing the burst, we identify the txop used in the burst and
  * incr the corresponding bin.
  * Each bin represents 1ms & we have 10 bins in this histogram.
- * they are deined in FW using the following macros
+ * they are defined in FW using the following macros
  * #define WAL_MAX_TXOP_USED_CNT_HISTOGRAM 10
  * #define WAL_TXOP_USED_HISTOGRAM_INTERVAL 1000 ( 1 ms )
  *
@@ -3336,7 +3336,7 @@ typedef struct {
     A_UINT32 mu_mimo_mpdus_failed_usr;
     /** 11AC DL MU MIMO number of mpdus re-queued to HW, per user */
     A_UINT32 mu_mimo_mpdus_requeued_usr;
-    /** 11AC DL MU MIMO BA not receieved, per user */
+    /** 11AC DL MU MIMO BA not received, per user */
     A_UINT32 mu_mimo_err_no_ba_usr;
     /** 11AC DL MU MIMO mpdu underrun encountered, per user */
     A_UINT32 mu_mimo_mpdu_underrun_usr;
@@ -3351,7 +3351,7 @@ typedef struct {
     A_UINT32 ax_mu_mimo_mpdus_failed_usr;
     /** 11AX DL MU MIMO number of mpdus re-queued to HW, per user */
     A_UINT32 ax_mu_mimo_mpdus_requeued_usr;
-    /** 11AX DL MU MIMO BA not receieved, per user */
+    /** 11AX DL MU MIMO BA not received, per user */
     A_UINT32 ax_mu_mimo_err_no_ba_usr;
     /** 11AX DL MU MIMO mpdu underrun encountered, per user */
     A_UINT32 ax_mu_mimo_mpdu_underrun_usr;
@@ -3366,7 +3366,7 @@ typedef struct {
     A_UINT32 ax_ofdma_mpdus_failed_usr;
     /** 11AX MU OFDMA number of mpdus re-queued to HW, per user */
     A_UINT32 ax_ofdma_mpdus_requeued_usr;
-    /** 11AX MU OFDMA BA not receieved, per user */
+    /** 11AX MU OFDMA BA not received, per user */
     A_UINT32 ax_ofdma_err_no_ba_usr;
     /** 11AX MU OFDMA mpdu underrun encountered, per user */
     A_UINT32 ax_ofdma_mpdu_underrun_usr;
@@ -3498,7 +3498,7 @@ typedef enum {
     HTT_SCHED_TID_SKIP_UL_TWT_PAUSED,           /* Skip ul tid if twt txq is paused                                                              */
     HTT_SCHED_TID_SKIP_PEER_UL_RX_NOT_ACTIVE,   /* Skip ul tid if peer ul rx is not active                                                       */
     HTT_SCHED_TID_SKIP_NO_FORCE_TRIGGER,        /* Skip ul tid if there is no force triggers                                                     */
-    HTT_SCHED_TID_SKIP_SMART_BASIC_TRIGGER,     /* Skip ul tid if smart basic trigger doesnot have enough data                                   */
+    HTT_SCHED_TID_SKIP_SMART_BASIC_TRIGGER,     /* Skip ul tid if smart basic trigger doesn't have enough data                                   */
 
 
     HTT_SCHED_INELIGIBILITY_MAX,
@@ -3520,7 +3520,7 @@ typedef struct {
 } htt_sched_txq_sched_ineligibility_tlv_v;
 
 typedef enum {
-    HTT_SCHED_SUPERCYCLE_TRIGGER_NONE = 0,                 /* Supercycle not triggerd */
+    HTT_SCHED_SUPERCYCLE_TRIGGER_NONE = 0,                 /* Supercycle not triggered */
     HTT_SCHED_SUPERCYCLE_TRIGGER_FORCED,                   /* forced supercycle trigger */
     HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_TIDQ_ENTRIES,    /* Num tidq entries is less than max_client threshold */
     HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_ACTIVE_TIDS,     /* Num active tids is less than max_client threshold */
@@ -6314,7 +6314,7 @@ typedef enum {
     HTT_EXPLICIT_TXBF_MU_SIFS_STEER_STATS = 3,
     /* Multi user random back off steer stats */
     HTT_EXPLICIT_TXBF_MU_RBO_STEER_STATS  = 4,
-    /* For backward compatability new modes cannot be added */
+    /* For backward compatibility new modes cannot be added */
     HTT_TXBF_MAX_NUM_OF_MODES = 5
 } htt_txbf_sound_steer_modes;
 
@@ -6486,7 +6486,7 @@ typedef struct {
      * opportunities created. Incoming OBSS frame RSSI is compared with per
      * PPDU non-SRG RSSI threshold configured in each PPDU. If incoming OBSS
      * RSSI < non-SRG RSSI threshold configured in each PPDU, then non-SRG
-     * tranmission happens.
+     * transmission happens.
      */
     A_UINT32 num_non_srg_ppdu_tried;
     /**
@@ -6507,7 +6507,7 @@ typedef struct {
      * Incoming OBSS frame RSSI is compared with per PPDU SRG RSSI
      * threshold configured in each PPDU.
      * If incoming OBSS RSSI < SRG RSSI threshold configured in each PPDU,
-     * then SRG tranmission happens.
+     * then SRG transmission happens.
      */
     A_UINT32 num_srg_ppdu_tried;
     /**
@@ -6585,15 +6585,15 @@ typedef struct {
      * histogram showing how many times different degrees of backpressure
      * duration occurred:
      * Index 0 indicates the number of times ring was
-     * continously in backpressure state for 100 - 200ms.
+     * continuously in backpressure state for 100 - 200ms.
      * Index 1 indicates the number of times ring was
-     * continously in backpressure state for 200 - 300ms.
+     * continuously in backpressure state for 200 - 300ms.
      * Index 2 indicates the number of times ring was
-     * continously in backpressure state for 300 - 400ms.
+     * continuously in backpressure state for 300 - 400ms.
      * Index 3 indicates the number of times ring was
-     * continously in backpressure state for 400 - 500ms.
+     * continuously in backpressure state for 400 - 500ms.
      * Index 4 indicates the number of times ring was
-     * continously in backpressure state beyond 500ms.
+     * continuously in backpressure state beyond 500ms.
      */
     A_UINT32 backpressure_hist[5];
 } htt_ring_backpressure_stats_tlv;
@@ -7323,27 +7323,27 @@ typedef enum {
 
 typedef enum {
     HTT_STATS_RESET_CAUSE_FIRST_RESET      = 0x00000001, /* First reset by application */
-    HTT_STATS_RESET_CAUSE_ERROR            = 0x00000002, /* Trigered due to error */
+    HTT_STATS_RESET_CAUSE_ERROR            = 0x00000002, /* Triggered due to error */
     HTT_STATS_RESET_CAUSE_DEEP_SLEEP       = 0x00000004, /* Reset after deep sleep */
     HTT_STATS_RESET_CAUSE_FULL_RESET       = 0x00000008, /* Full reset without any optimizations */
     HTT_STATS_RESET_CAUSE_CHANNEL_CHANGE   = 0x00000010, /* For normal channel change */
-    HTT_STATS_RESET_CAUSE_BAND_CHANGE      = 0x00000020, /* Trigered due to band change */
-    HTT_STATS_RESET_CAUSE_DO_CAL           = 0x00000040, /* Trigered due to calibrations */
+    HTT_STATS_RESET_CAUSE_BAND_CHANGE      = 0x00000020, /* Triggered due to band change */
+    HTT_STATS_RESET_CAUSE_DO_CAL           = 0x00000040, /* Triggered due to calibrations */
     HTT_STATS_RESET_CAUSE_MCI_ERROR        = 0x00000080, /* Triggered due to MCI ERROR */
-    HTT_STATS_RESET_CAUSE_CHWIDTH_CHANGE   = 0x00000100, /* Trigered due to channel width change */
-    HTT_STATS_RESET_CAUSE_WARM_RESTORE_CAL = 0x00000200, /* Trigered due to warm reset we want to just restore calibrations */
-    HTT_STATS_RESET_CAUSE_COLD_RESTORE_CAL = 0x00000400, /* Trigered due to cold reset we want to just restore calibrations */
-    HTT_STATS_RESET_CAUSE_PHY_WARM_RESET   = 0x00000800, /* Trigered due to phy warm reset we want to just restore calibrations */
-    HTT_STATS_RESET_CAUSE_M3_SSR           = 0x00001000, /* Trigered due to SSR Restart */
+    HTT_STATS_RESET_CAUSE_CHWIDTH_CHANGE   = 0x00000100, /* Triggered due to channel width change */
+    HTT_STATS_RESET_CAUSE_WARM_RESTORE_CAL = 0x00000200, /* Triggered due to warm reset we want to just restore calibrations */
+    HTT_STATS_RESET_CAUSE_COLD_RESTORE_CAL = 0x00000400, /* Triggered due to cold reset we want to just restore calibrations */
+    HTT_STATS_RESET_CAUSE_PHY_WARM_RESET   = 0x00000800, /* Triggered due to phy warm reset we want to just restore calibrations */
+    HTT_STATS_RESET_CAUSE_M3_SSR           = 0x00001000, /* Triggered due to SSR Restart */
     HTT_STATS_RESET_CAUSE_FORCE_CAL        = 0x00002000, /* Reset to force the calibration */
     /* 0x00004000, 0x00008000 reserved */
     HTT_STATS_NO_RESET_CHANNEL_CHANGE      = 0x00010000, /* No reset, normal channel change */
     HTT_STATS_NO_RESET_BAND_CHANGE         = 0x00020000, /* No reset, channel change across band */
     HTT_STATS_NO_RESET_CHWIDTH_CHANGE      = 0x00040000, /* No reset, channel change across channel width */
     HTT_STATS_NO_RESET_CHAINMASK_CHANGE    = 0x00080000, /* No reset, chainmask change */
-    HTT_STATS_RESET_CAUSE_PHY_WARM_RESET_UCODE_TRIG = 0x00100000, /* Trigered due to phy warm reset we want to just restore calibrations */
+    HTT_STATS_RESET_CAUSE_PHY_WARM_RESET_UCODE_TRIG = 0x00100000, /* Triggered due to phy warm reset we want to just restore calibrations */
     HTT_STATS_RESET_CAUSE_PHY_OFF_TIMEOUT_RESET  = 0x00200000, /* Reset ucode because phy off ack timeout*/
-    HTT_STATS_RESET_CAUSE_LMAC_RESET_UMAC_NOC_ERR = 0x00400000, /* LMAC reset trigered due to NOC Address/Slave error originating at LMAC */
+    HTT_STATS_RESET_CAUSE_LMAC_RESET_UMAC_NOC_ERR = 0x00400000, /* LMAC reset triggered due to NOC Address/Slave error originating at LMAC */
     HTT_STATS_NO_RESET_SCAN_BACK_TO_SAME_HOME_CHANNEL_CHANGE = 0x00800000, /* No reset, scan to home channel change */
 } HTT_STATS_RESET_CAUSE;
 
@@ -7395,7 +7395,7 @@ typedef struct {
     A_UINT32 phytx_abort_cnt;
     /** number of times rx abort initiated by phy */
     A_UINT32 phyrx_abort_cnt;
-    /** number of rx defered count initiated by phy */
+    /** number of rx deferred count initiated by phy */
     A_UINT32 phyrx_defer_abort_cnt;
     /** number of sizing events generated at LSTF */
     A_UINT32 rx_gain_adj_lstf_event_cnt; /* a.k.a sizing1 */
@@ -8337,7 +8337,7 @@ typedef struct _htt_ml_peer_stats {
 } htt_ml_peer_stats_t;
 
 /*
- * ODD Mandatory Stats are grouped together from all the exisitng different
+ * ODD Mandatory Stats are grouped together from all the existing different
  * stats, to form a set of stats that will be used by the ODD application to
  * post the stats to the cloud instead of polling for the individual stats.
  * This is done to avoid non-mandatory stats to be polled as the data will not
diff --git a/fw/wdi_ipa.h b/fw/wdi_ipa.h
index 9870426ce414..c6e6d50be5d0 100644
--- a/fw/wdi_ipa.h
+++ b/fw/wdi_ipa.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2011-2017 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  *
  * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
  *
@@ -408,7 +409,7 @@ A_COMPILE_TIME_ASSERT(verify_Pkt_pool_sz,
  *     Purpose: Specify length Ethernet Packet
  *   - VDEV_ID
  *     Bits 23:16
- *     Purpose: Specify the VDEV ID corrsponding the the packet
+ *     Purpose: Specify the VDEV ID corresponding to the packet
  */
 
 
diff --git a/fw/wlan_defs.h b/fw/wlan_defs.h
index b2f5bcb5dc68..abb978c19516 100755
--- a/fw/wlan_defs.h
+++ b/fw/wlan_defs.h
@@ -106,7 +106,7 @@
  */
 #define MAX_SPATIAL_STREAM_ANY MAX_SPATIAL_STREAM_ANY_V2 /* DEPRECATED */
 
-/* defines to set Packet extension values whic can be 0 us, 8 usec or 16 usec */
+/* defines to set Packet extension values which can be 0, 8, or 16 usec */
 /* NOTE: Below values cannot be changed without breaking WMI Compatibility */
 #define MAX_HE_NSS               8
 #define MAX_HE_MODULATION        8
@@ -477,8 +477,8 @@ typedef struct {
 
 /*
  * Used to update rate-control logic with the status of the tx-completion.
- * In host-based implementation of the rate-control feature, this struture is used to
- * create the payload for HTT message/s from target to host.
+ * In host-based implementation of the rate-control feature, this structure
+ * is used to create the payload for HTT message/s from target to host.
  */
 #ifndef CONFIG_MOVE_RC_STRUCT_TO_MACCORE
   #if (NUM_SPATIAL_STREAM > 3)
@@ -680,7 +680,7 @@ typedef struct {
 #endif
 
 /**
- * strucutre describing host memory chunk.
+ * structure describing host memory chunk.
  */
 typedef struct {
    A_UINT32   tlv_header;     /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wlan_host_memory_chunk */
@@ -809,9 +809,9 @@ struct wlan_dbg_tx_stats_v1 {
     A_UINT32 sw_retry_failure;
     /* illegal rate phy errors  */
     A_UINT32 illgl_rate_phy_err;
-    /* wal pdev continous xretry */
+    /* wal pdev continuous xretry */
     A_UINT32 pdev_cont_xretry;
-    /* wal pdev continous xretry */
+    /* wal pdev continuous xretry */
     A_UINT32 pdev_tx_timeout;
     /* wal pdev resets  */
     A_UINT32 pdev_resets;
@@ -861,9 +861,9 @@ struct wlan_dbg_tx_stats_v2 {
     A_UINT32 sw_retry_failure;
     /* illegal rate phy errors  */
     A_UINT32 illgl_rate_phy_err;
-    /* wal pdev continous xretry */
+    /* wal pdev continuous xretry */
     A_UINT32 pdev_cont_xretry;
-    /* wal pdev continous xretry */
+    /* wal pdev continuous xretry */
     A_UINT32 pdev_tx_timeout;
     /* wal pdev resets  */
     A_UINT32 pdev_resets;
@@ -1733,7 +1733,7 @@ typedef struct {
      */
     A_UINT32 link_info;
 /*  This TLV is followed by array of mlo_glb_link:
- *  mlo_glb_link will have mutiple instances equal to num of hw links
+ *  mlo_glb_link will have multiple instances equal to num of hw links
  *  received by no_of_link
  *      mlo_glb_link glb_link_info[];
  */
@@ -1779,7 +1779,7 @@ typedef struct {
      */
     A_UINT32 chip_info;
     /*  This TLV is followed by array of mlo_glb_per_chip_crash_info:
-     *  mlo_glb_per_chip_crash_info will have mutiple instances equal to num of partner chips
+     *  mlo_glb_per_chip_crash_info will have multiple instances equal to num of partner chips
      *  received by no_of_chips
      *  mlo_glb_per_chip_crash_info per_chip_crash_info[];
      */
diff --git a/fw/wmi.h b/fw/wmi.h
index bf99cd6dfd2d..b3623809d0f8 100644
--- a/fw/wmi.h
+++ b/fw/wmi.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2010-2017 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  *
  * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
  *
@@ -111,7 +112,7 @@ typedef PREPACK struct {
 #define WMI_CMD_HDR_PLT_PRIV_OFFSET            0x00000000
 
 /*
- * List of Commnands
+ * List of Commands
  */
 typedef enum {
     WMI_EXTENSION_CMDID,                     //used in wmi_svc.c   /* Non-wireless extensions */
@@ -168,7 +169,7 @@ typedef enum {
 } WMI_PHY_CAPABILITY;
 
 
-/* Deprectated, need clean up */
+/* Deprecated, need clean up */
 #define WMI_MAX_RX_META_SZ  (12)
 
 typedef PREPACK struct {
diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index fc2b7539c3c9..692bf026d1c5 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -65,10 +65,10 @@ typedef  enum  {
     WMI_SERVICE_GPIO=25,                    /* GPIO service */
     WMI_SERVICE_STA_DTIM_PS_MODULATED_DTIM=26, /* Modulated DTIM support */
     WMI_STA_UAPSD_BASIC_AUTO_TRIG=27,       /* Basic version of station UAPSD AC Trigger Generation Method with
-                                             * variable tigger periods (service, delay, and suspend intervals) */
+                                             * variable trigger periods (service, delay, and suspend intervals) */
     WMI_STA_UAPSD_VAR_AUTO_TRIG=28,         /* Station UAPSD AC Trigger Generation Method with variable
                                              * trigger periods (service, delay, and suspend intervals) */
-    WMI_SERVICE_STA_KEEP_ALIVE=29,          /* Serivce to support the STA KEEP ALIVE mechanism */
+    WMI_SERVICE_STA_KEEP_ALIVE=29,          /* Service to support the STA KEEP ALIVE mechanism */
     WMI_SERVICE_TX_ENCAP=30,                /* Packet type for TX encapsulation */
     WMI_SERVICE_AP_PS_DETECT_OUT_OF_SYNC=31, /* detect out-of-sync sleeping stations */
     WMI_SERVICE_EARLY_RX=32,                /* adaptive early-rx feature */
@@ -523,8 +523,8 @@ typedef  enum  {
     WMI_SERVICE_WAPI_CONCURRENCY_SUPPORTED = 277, /* Indicates FW support for WAPI concurrency */
     WMI_SERVICE_SAP_CONNECTED_D3WOW = 278,  /* Indicates FW support for D3WoW for SAP connected case */
     WMI_SERVICE_GO_CONNECTED_D3WOW = 279,   /* Indicates FW support for D3WoW for P2P GO connected case */
-    WMI_SERVICE_EXT_TPC_REG_SUPPORT = 280, /* Support for new 6G TPC power limits */
-    WMI_SERVICE_REG_CC_EXT_EVENT_SUPPORT = 281, /* Support for Extended REG_CC Event with additional params for 6G */
+    WMI_SERVICE_EXT_TPC_REG_SUPPORT = 280, /* Support for new 6 GHz TPC power limits */
+    WMI_SERVICE_REG_CC_EXT_EVENT_SUPPORT = 281, /* Support for Extended REG_CC Event with additional params for 6 GHz */
     WMI_SERVICE_NDI_TXBF_SUPPORT = 282, /* Indicates FW support for Tx beamforming with NDI VDEV */
     WMI_SERVICE_ENABLE_LOWER_6G_EDGE_CH_SUPP = 283, /* Indicates FW support for enabling lower 6 GHz edge channel 5935 */
     WMI_SERVICE_DISABLE_UPPER_6G_EDGE_CH_SUPP = 284, /* Indicates FW support for disabling upper 6 GHz edge channel 7115 */
@@ -602,7 +602,7 @@ typedef  enum  {
     WMI_SERVICE_MULTIPLE_VDEV_RESTART_BITMAP_SUPPORT = 349, /* Extended Multiple VDEV Restart with Bitmap Support */
     WMI_SERVICE_WMI_SERVICE_WPA3_SHA384_ROAM_SUPPORT = 350, /* Indicates FW supports WPA3 SHA384 roaming */
     WMI_SERVICE_ODD_LIVEDUMP_SUPPORT = 351, /* Support for ODD Livedump from the FW */
-    WMI_SERVICE_EIRP_PREFERRED_SUPPORT = 352, /* Support for OOBE feature where only EIRP powers will be sent in 6G TPC WMI */
+    WMI_SERVICE_EIRP_PREFERRED_SUPPORT = 352, /* Support for OOBE feature where only EIRP powers will be sent in 6 GHz TPC WMI */
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 662fe53da422..0e04384905eb 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -3208,7 +3208,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_DFS_PHYERR_FILTER_DIS_CMDID);
 
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMDID);
 
-/* DFS phyerr processing offload disble cmd */
+/* DFS phyerr processing offload disable cmd */
 #define WMITLV_TABLE_WMI_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_dfs_phyerr_offload_disable_cmd_fixed_param, wmi_pdev_dfs_phyerr_offload_disable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 
@@ -4419,7 +4419,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_REORDER_QUEUE_SETUP_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_reorder_queue_remove_cmd_fixed_param, wmi_peer_reorder_queue_remove_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_PEER_REORDER_QUEUE_REMOVE_CMDID);
 
-/* Filter in monitor mode paramters Cmd */
+/* Filter in monitor mode parameters Cmd */
 #define WMITLV_TABLE_WMI_MNT_FILTER_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mnt_filter_cmd_fixed_param, wmi_mnt_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_MNT_FILTER_CMDID);
@@ -5637,7 +5637,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_DIAG_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_GTK_OFFLOAD_STATUS_EVENT_fixed_param, WMI_GTK_OFFLOAD_STATUS_EVENT_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_GTK_OFFLOAD_STATUS_EVENTID);
 
-/* DCA interferance Event */
+/* DCA interference Event */
 #define WMITLV_TABLE_WMI_DCS_INTERFERENCE_EVENTID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dcs_interference_event_fixed_param, wmi_dcs_interference_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wlan_dcs_cw_int, cw_int, WMITLV_SIZE_VAR) \
@@ -6066,7 +6066,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_NDP_CONFIRM_EVENTID);
 WMITLV_CREATE_PARAM_STRUC(WMI_NDP_END_INDICATION_EVENTID);
 
 /** NDL schedule update event
- * TLV (tag lenght value ) parameters follow the ndl_schedule_update
+ * TLV (tag length value) parameters follow the ndl_schedule_update
  * structure. The TLV's are:
  * A_UINT32 ndp_instance_list[];
  * wmi_channel ndl_channel_list[];
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index c8b1a662fa5e..1b269a572119 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -56,7 +56,7 @@
  * 5. Do not use PACK/UNPACK attributes for the structures as each member variable is
  *    already 4-byte aligned by virtue of being a A_UINT32 type.
  * 6. Comment each parameter part of the WMI command/event structure by using the
- *    2 stars at the begining of C comment instead of one star to enable HTML document
+ *    2 stars at the beginning of C comment instead of one star to enable HTML document
  *    generation using Doxygen.
  *
  */
@@ -137,7 +137,7 @@ extern "C" {
 
 /*
  * Below GET/SET BITS_ARRAY_LEN32_BYTES macros can be used when
- * reading/writting bits which are spread across array_len32 entries.
+ * reading/writing bits which are spread across array_len32 entries.
  * These can be used to GET/SET maximum of 32 bits only,
  * also array_len32 length should be limited to maximum of 32.
  */
@@ -385,7 +385,7 @@ typedef enum {
     WMI_PDEV_DUMP_CMDID,
     /* set LED configuration  */
     WMI_PDEV_SET_LED_CONFIG_CMDID,
-    /* Get Current temprature of chip in Celcius degree*/
+    /* Get Current temperature of chip in Celcius degree*/
     WMI_PDEV_GET_TEMPERATURE_CMDID,
     /* Set LED flashing behavior  */
     WMI_PDEV_SET_LED_FLASHING_CMDID,
@@ -637,7 +637,7 @@ typedef enum {
     WMI_PEER_ADD_WDS_ENTRY_CMDID,
     /**remove wds  (4 address) entry. used only for testing WDS feature on AP products */
     WMI_PEER_REMOVE_WDS_ENTRY_CMDID,
-    /** set up mcast group infor for multicast to unicast conversion */
+    /** set up mcast group info for multicast to unicast conversion */
     WMI_PEER_MCAST_GROUP_CMDID,
     /** request peer info from FW. FW shall respond with PEER_INFO_EVENTID */
     WMI_PEER_INFO_REQ_CMDID,
@@ -1002,7 +1002,7 @@ typedef enum {
 
     /*
      * Add a CoAP keepalive pattern to send a CoAP broadcast packet
-     * when configured timeout occured.
+     * when configured timeout occurred.
      */
     WMI_WOW_COAP_ADD_KEEPALIVE_PATTERN_CMDID,
 
@@ -1273,7 +1273,7 @@ typedef enum {
     WMI_STA_SMPS_PARAM_CMDID,
 
     /* Wlan HB commands*/
-    /* enalbe/disable wlan HB */
+    /* enable/disable wlan HB */
     WMI_HB_SET_ENABLE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_WLAN_HB),
     /* set tcp parameters for wlan HB */
     WMI_HB_SET_TCP_PARAMS_CMDID,
@@ -1593,7 +1593,7 @@ typedef enum {
     /** track L1SS entry and residency event */
     WMI_PDEV_L1SS_TRACK_EVENTID,
 
-    /** Report current temprature of the chip in Celcius degree */
+    /** Report current temperature of the chip in Celcius degree */
     WMI_PDEV_TEMPERATURE_EVENTID,
 
     /** Extension of WMI_SERVICE_READY msg with extra target capability info */
@@ -2874,7 +2874,7 @@ typedef struct _wmi_abi_version {
 } wmi_abi_version;
 
 /*
- * maximum number of memroy requests allowed from FW.
+ * maximum number of memory requests allowed from FW.
  */
 #define WMI_MAX_MEM_REQS 16
 
@@ -2973,7 +2973,7 @@ typedef struct {
     A_UINT32 max_num_scan_channels;
 
     /* Hardware board specific ID. Values defined in enum WMI_HWBOARD_ID.
-     * Default 0 means tha hw_bd_info[] is invalid(legacy board).
+     * Default 0 means that hw_bd_info[] is invalid (legacy board).
      */
     A_UINT32 hw_bd_id;
     A_UINT32 hw_bd_info[HW_BD_INFO_SIZE]; /* Board specific information. Invalid if hw_hd_id is zero. */
@@ -3387,7 +3387,7 @@ typedef struct {
     /* Following this struct are the TLV's:
      *     WMI_DMA_RING_CAPABILITIES;
      *     wmi_spectral_bin_scaling_params;
-     *     WMI_MAC_PHY_CAPABILITIES_EXT;  <-- EHT mac capabilites and phy capabilites info
+     *     WMI_MAC_PHY_CAPABILITIES_EXT;  <-- EHT mac capabilities and phy capabilities info
      *     WMI_HAL_REG_CAPABILITIES_EXT2;
      *     wmi_nan_capabilities;
      *     WMI_SCAN_RADIO_CAPABILITIES_EXT2;
@@ -3456,7 +3456,7 @@ typedef enum {
     WMI_FW_NAN_RTT_RESPR =     0x00000200,
     WMI_FW_SCAN_DBS_POLICY =   0x00000400,
     /*
-     * New fw sub feature capabilites before
+     * New fw sub feature capabilities before
      * WMI_FW_MAX_SUB_FEAT_CAP
      */
     WMI_FW_MAX_SUB_FEAT_CAP =  0x80000000,
@@ -3519,7 +3519,7 @@ typedef struct {
 } wmi_wlan_avoid_freq_ranges_event;
 #endif
 
-/** status consists of  upper 16 bits fo A_STATUS status and lower 16 bits of module ID that retuned status */
+/** status consists of  upper 16 bits fo A_STATUS status and lower 16 bits of module ID that returned status */
 #define WLAN_INIT_STATUS_SUCCESS   0x0
 #define WLAN_INIT_STATUS_GEN_FAILED   0x1
 #define WLAN_GET_INIT_STATUS_REASON(status)    ((status) & 0xffff)
@@ -3631,7 +3631,7 @@ typedef struct {
      * @brief In offload mode target supports features like WOW, chatter and other
      * protocol offloads. In order to support them some functionalities like
      * reorder buffering, PN checking need to be done in target. This determines
-     * maximum number of peers suported by target in offload mode
+     * maximum number of peers supported by target in offload mode
      */
     A_UINT32 num_offload_peers;
     /* @brief Number of reorder buffers available for doing target based reorder
@@ -3819,7 +3819,7 @@ typedef struct {
      * @details
      *     This parameter controls the max number of Tx fragments per MSDU.
      *     This is sent by the target as part of the WMI_SERVICE_READY event
-     *     and is overriden by the OS shim as required.
+     *     and is overridden by the OS shim as required.
      */
     A_UINT32 max_frag_entries;
 
@@ -4078,7 +4078,7 @@ typedef struct {
      * @details
      *        1 - Smart antenna is enabled.
      *        0 - Smart antenna is disabled.
-     * In future this can contain smart antenna specifc capabilities.
+     * In future this can contain smart antenna specific capabilities.
      */
     A_UINT32 smart_ant_cap;
 
@@ -4266,7 +4266,7 @@ typedef struct {
      *      macros.
      *  Bits 5:4
      *      HTT rx peer metadata version number that host supports.
-     *      Firmware intially sends the target supported version number
+     *      Firmware initially sends the target supported version number
      *      as part of service_ready_ext2 message.
      *      Host can ack the version number that it is using as part of
      *      this message.
@@ -4337,7 +4337,7 @@ typedef struct {
      *
      *  @details
      *  Bit 0
-     *      The bit will be set when Host HDD supports seperate iface creation
+     *      The bit will be set when Host HDD supports separate iface creation
      *      for NAN.  More specifically Host can support creation of NAN vdev
      *      in firmware.
      *
@@ -4435,7 +4435,7 @@ typedef struct {
     /** @brief max_rnr_neighbours -
      * The Maximum number of neighbour RNR's from other SoC.
      * This limits the field @num_bss in @wmi_pdev_tbtt_offset_sync_cmd_fixed_param.
-     * Value of 0 means crosss SoC TBTT offset syncronization not required and
+     * Value of 0 means cross SoC TBTT offset synchronization not required and
      * @PDEV_TBTT_OFFSET_SYNC_CMD wouldn't be used.
      */
     A_UINT32 max_rnr_neighbours;
@@ -5010,7 +5010,7 @@ typedef enum {
 #define WMI_SET_MHS_WPA3_SUPPORT(feature_bitmap, val)                   \
         WMI_SET_BITS_ARRAY_LEN32_BYTES(feature_bitmap, 31, 1, val)
 
-/* Vendor requirement1 supported verison info */
+/* Vendor requirement1 supported version info */
 /* enum's WMI_VENDORxx_REQxx_VERSION are the possible vaues for below bitfield*/
 #define WMI_GET_VENDOR_REQ_1_VERSION(var, feature_bitmap)          \
         WMI_GET_BITS_ARRAY_LEN32_BYTES(var, feature_bitmap, 32, 8)
@@ -5067,7 +5067,7 @@ typedef enum {
 #define WMI_SET_ROAMING_CTRL_GET_CU(feature_bitmap, val)                   \
         WMI_SET_BITS_ARRAY_LEN32_BYTES(feature_bitmap, 51, 1, val)
 
-/* Vendor requirement2 supported verison info */
+/* Vendor requirement2 supported version info */
 /* enum's WMI_VENDORxx_REQxx_VERSION are the possible vaues for below bitfield*/
 #define WMI_GET_VENDOR_REQ_2_VERSION(var, feature_bitmap)          \
         WMI_GET_BITS_ARRAY_LEN32_BYTES(var, feature_bitmap, 52, 8)
@@ -5255,7 +5255,7 @@ typedef struct {
 } wmi_tlv_buf_len_param;
 
 /**
- * TLV used for specifying the demensions of a multi-dimensional array
+ * TLV used for specifying the dimensions of a multi-dimensional array
  * that has been stored in a flat buffer
  */
 typedef struct {
@@ -5427,7 +5427,7 @@ typedef struct {
      *   The number of probe requests specified depends on the ssid_list and bssid_list
      */
     A_UINT32 repeat_probe_time;
-    /** time in msec between 2 consequetive probe requests with in a set. */
+    /** time in msec between 2 consecutive probe requests with in a set. */
     A_UINT32 probe_spacing_time;
     /** data inactivity time in msec on bss channel that will be used by scanner for measuring the inactivity  */
     A_UINT32 idle_time;
@@ -5536,7 +5536,7 @@ typedef struct {
 /**When set, certain errors are ignored and scan continues.
  * Different FW scan engine may use its own logic to decide what errors to ignore*/
 #define WMI_SCAN_CONTINUE_ON_ERROR   0x80
-/** Enable promiscous mode for CCXv4 */
+/** Enable promiscuous mode for CCXv4 */
 #define WMI_SCAN_FILTER_PROMISCOUS   0x100
 /** allow to send probe req on DFS channel */
 #define WMI_SCAN_FLAG_FORCE_ACTIVE_ON_DFS 0x200
@@ -5552,7 +5552,7 @@ typedef struct {
 #define WMI_SCAN_OFFCHAN_MGMT_TX    0x2000
 /** allow data transmission during off channel scan */
 #define WMI_SCAN_OFFCHAN_DATA_TX    0x4000
-/** allow capture ppdu with phy errrors */
+/** allow capture ppdu with phy errors */
 #define WMI_SCAN_CAPTURE_PHY_ERROR  0x8000
 /** always do passive scan on passive channels */
 #define WMI_SCAN_FLAG_STRICT_PASSIVE_ON_PCHN 0x10000
@@ -8097,7 +8097,7 @@ typedef enum {
     /** Set 5G positive and negative Tx power in 0.5dBm
      *  units */
     WMI_PDEV_PARAM_SIGNED_TXPOWER_5G,                 /* 0x70 */
-    /** Enable/disble AMSDU for tids */
+    /** Enable/disable AMSDU for tids */
     WMI_PDEV_PARAM_ENABLE_PER_TID_AMSDU,              /* 0x71 */
     /** Enable/disable AMPDU for tids */
     WMI_PDEV_PARAM_ENABLE_PER_TID_AMPDU,              /* 0x72 */
@@ -8127,7 +8127,7 @@ typedef enum {
      * If this factor is 3, the power is scaled down by 2^3, i.e. 9 dB
      */
     WMI_PDEV_PARAM_CUST_TXPOWER_SCALE,                /* 0x7b */
-    /** ATF enabe/disabe dynamically */
+    /** ATF enabe/disable dynamically */
     WMI_PDEV_PARAM_ATF_DYNAMIC_ENABLE,                /* 0x7c */
     /** Set tx retry limit for control frames. 0 = disable, 31 = max */
     WMI_PDEV_PARAM_CTRL_RETRY_LIMIT,                  /* 0x7d */
@@ -8362,7 +8362,7 @@ typedef enum {
     /*
      * Set the base timer for the periodic CFR capture. By default this is 10ms.
      * The period ('periodicity' param in wmi_peer_cfr_capture_cmd) of
-     * CFR measurment of other peers will be in multiples of this base timer.
+     * CFR measurement of other peers will be in multiples of this base timer.
      * The unit is in milliseconds.
      */
     WMI_PDEV_PARAM_PERIODIC_CFR_BASE_TIMER,
@@ -8502,7 +8502,7 @@ typedef enum {
      *         | If not set: The value in lower bits is the duration (in ms),
      *         |   from which the UL len is derived.
      *         |   Example: if host sets 2000 (2ms), then UL Len in trigger
-     *         |   will be derived to accomodate the given duration.
+     *         |   will be derived to accommodate the given duration.
      */
     WMI_PDEV_PARAM_SET_TEST_CMD_UL_TRIGGER_LSIG_LEN,
 
@@ -8528,7 +8528,7 @@ typedef enum {
 
     /*
      * Configure test command to set the fc duration in BSR trigger frame.
-     *  value 0 - FW calulates the duration(default).
+     *  value 0 - FW calculates the duration (default).
      *  Non zero Value: Duration to be configured.
      */
     WMI_PDEV_PARAM_SET_TEST_CMD_UL_BSR_FC_DURATION,
@@ -8549,7 +8549,7 @@ typedef enum {
      * (SRG = Spatial Reuse Group)
      * The accepted values are in between 0x00 and 0xFF, inclusive.
      * The parameter value is programmed into the appropriate spatial reuse
-     * regsiter, to specify how low the background signal strength from
+     * register, to specify how low the background signal strength from
      * neighboring BSS cells must be, for this AP to employ spatial reuse.
      *
      * The value of the parameter is compared against the OBSS RSSI in dB.
@@ -8563,7 +8563,7 @@ typedef enum {
      * BSS cells is no more than 10 dB.
      *
      * If Bit 29 is set, then input value will be in dBm. This is used
-     * for chipsets that uses dBm for comparision across MAC/Phy blocks.
+     * for chipsets that uses dBm for comparison across MAC/Phy blocks.
      * Older chipsets support input in dB units. For newer chipsets, dBm
      * units will be used.
      * The host will use the WMI_SERVICE_SRG_SRP_SPATIAL_REUSE_SUPPORT
@@ -8821,7 +8821,7 @@ typedef enum {
      * max probe interval.
      * units = milliseconds
      *  bits | config_mode
-     *  0-15 | mimimum probe time for MCS
+     *  0-15 | minimum probe time for MCS
      *  16-31| maximum probe time for MCS
      */
     WMI_PDEV_PARAM_MIN_MAX_MCS_PROBE_INTERVAL,
@@ -9289,7 +9289,7 @@ typedef struct {
      *        1 | enable/disable SLOW diversity
      *      5:2 | chain0 slow-diversity weighting factor
      *      9:6 | chain1 slow-diversity weighting factor
-     *     31:10| currenty unused (set to 0x0)
+     *     31:10| currently unused (set to 0x0)
      * Refer to the above WMI_[FAST/SLOW]_DIVERSITY constants.
      */
     A_UINT32 value;
@@ -9735,8 +9735,8 @@ typedef struct {
  * Implementation details of the API to send the map to the target are as described-
  *
  * 1. The function will have 2 arguments- struct ieee80211com, DSCP-to-TID map.
- *    DSCP-to-TID map is a one dimensional u_int32_t array of length 64 to accomodate
- *    64 TID values for 2^6 (64) DSCP ids.
+ *    DSCP-to-TID map is a one dimensional u_int32_t array of length 64 to
+ *    accommodate 64 TID values for 2^6 (64) DSCP ids.
  *    Example:
  *      A_UINT32 dscp_tid_map[WMI_DSCP_MAP_MAX] = {
  *                                  0, 0, 0, 0, 0, 0, 0, 0,
@@ -9987,7 +9987,7 @@ typedef struct {
 /* The TLVs will follow.
  *    A_UINT32 diag_events_logs_list[]; 0-15 Bits Diag EVENT/LOG ID,
  *                                      Bit 16 - DIAG type EVENT/LOG, 0 - Event, 1 - LOG
- *                                      Bit 17 - Frequncy of the DIAG EVENT/LOG High Frequency -1, Low Frequency - 0
+ *                                      Bit 17 - Frequency of the DIAG EVENT/LOG High Frequency -1, Low Frequency - 0
  *                                      Bit 18 - Set if the EVENTS/LOGs are used for EXT DEBUG Framework
  */
 } wmi_diag_event_log_supported_event_fixed_params;
@@ -10432,7 +10432,7 @@ typedef struct {
     A_UINT32 num_peers;
     /** Indicates the fragment number  */
     A_UINT32 peer_event_number;
-    /** Indicates if there are more peers which will be sent as seperate peer_stats event */
+    /** Indicates if there are more peers which will be sent as separate peer_stats event */
     A_UINT32 more_data;
     /** Indicates the vdev id of the stats for MLO stats query */
     wmi_vdev_id_info vdev_id_info;
@@ -10453,7 +10453,7 @@ typedef struct {
     A_UINT32 tx_mpdu;
     /** number of received unicast mpdus */
     A_UINT32 rx_mpdu;
-    /** number of succesfully transmitted multicast data packets */
+    /** number of successfully transmitted multicast data packets */
     /** STA case: implies ACK received from AP for the unicast packet in which mcast pkt was sent */
     A_UINT32 tx_mcast;
     /** number of received multicast data packets */
@@ -11430,7 +11430,7 @@ typedef struct {
     /** number of peers in peer_stats_info[] */
     A_UINT32 num_peers;
     /** flag to indicate if there are more peers which will
-     *  be sent a following seperate peer_stats_info event */
+     *  be sent a following separate peer_stats_info event */
     A_UINT32 more_data;
     /* This TLV is followed by another TLV of array of structs
      * wmi_peer_stats_info peer_stats_info[];
@@ -11925,7 +11925,7 @@ typedef struct {
      * AWGN pkt drop trigger count
      * This shows how many times the presence of interference on the
      * primary BW has been inferred due to pkt drops.
-     * WMI_DCS_INTERFERENCE_EVENTID wil be sent whenever there is
+     * WMI_DCS_INTERFERENCE_EVENTID will be sent whenever there is
      * interference on Primary Channel.
      */
     A_UINT32 awgn_pkt_drop_trigger_cnt;
@@ -11935,7 +11935,7 @@ typedef struct {
      * AWGN bandwidth drop count
      * This is used to inform count for any frame transmitted on lower BW
      * than configured BW.
-     * WMI_DCS_INTERFERENCE_EVENTID wil be sent whenever there is BW drop.
+     * WMI_DCS_INTERFERENCE_EVENTID will be sent whenever there is BW drop.
      */
     A_UINT32 awgn_bw_drop_cnt;
     /* AWGN bandwidth drop reset count */
@@ -11943,7 +11943,7 @@ typedef struct {
     /*
      * AWGN CCA int count
      * This is used to inform the interference based on CCA registers.
-     * WMI_DCS_INTERFERENCE_EVENTID wil be sent whenever there is CCA
+     * WMI_DCS_INTERFERENCE_EVENTID will be sent whenever there is CCA
      * interference.
      */
     A_UINT32 awgn_cca_int_cnt;
@@ -11954,7 +11954,7 @@ typedef struct {
     /* AWGN cca ack blk reset count */
     A_UINT32 awgn_cca_ack_reset_cnt;
     /*
-     * AWGN int BW cnt used to store interference occured at 20/40/80/160MHz
+     * AWGN int BW cnt used to store interference occurred at 20/40/80/160MHz
      * bw_cnt[0] counts interference detections in 20 MHz BW,
      * bw_cnt[1] counts interference detections in 40 MHz BW,
      * bw_cnt[2] counts interference detections in 80 MHz BW,
@@ -12019,7 +12019,7 @@ typedef struct {
 
     A_UINT32 pdev_id;               /* pdev_id for identifying the MAC/PHY */
 
-    /* Count of new request ID everytime it is generated */
+    /* Count of new request ID every time it is generated */
     A_UINT32 request_id_count;
     /* Count of total number of AFC payload received */
     A_UINT32 response_count;
@@ -12106,11 +12106,11 @@ typedef struct {
      * Regulatory Compliance check done on the AFC payload
      * received from server
      */
-    /* Incorrect PSD value recieved in freq Obj */
+    /* Incorrect PSD value received in freq Obj */
     A_UINT32 psd_failure_count;
-    /* Incorrect End freq recieved in freq Obj */
+    /* Incorrect End freq received in freq Obj */
     A_UINT32 psd_end_freq_failure_count;
-    /* Incorrect Start freq recieved in freq Obj */
+    /* Incorrect Start freq received in freq Obj */
     A_UINT32 psd_start_freq_failure_count;
     /* Incorrect EIRP received in channel obj */
     A_UINT32 eirp_failure_count;
@@ -12375,8 +12375,8 @@ typedef struct {
 } wmi_vdev_stats;
 
 /*
- * vdev ext stats with additonal bcn stats
- * (Due to backward compatiblity requirements, these new stats fields cannot be
+ * vdev ext stats with additional bcn stats
+ * (Due to backward compatibility requirements, these new stats fields cannot be
  * added inside wmi_vdev_stats.)
  */
 typedef struct {
@@ -12755,7 +12755,7 @@ typedef struct {
 
 /** VDEV update mac address event response status codes */
 typedef enum {
-    /** VDEV mac address updated sucessfully */
+    /** VDEV mac address updated successfully */
     WMI_VDEV_UPDATE_MAC_ADDR_CONF_STATUS_SUCCESS = 0,
     /** Requested VDEV not found */
     WMI_VDEV_UPDATE_MAC_ADDR_CONF_STATUS_INVALID_VDEVID = 1,
@@ -12832,7 +12832,7 @@ typedef enum {
  */
 #define WMI_UNIFIED_VDEV_SUBTYPE_MESH_11S   0x6
 /* Subtype to indicate that the AP VAP is in smart monitor mode
- * This is needed to differentiate in firmware betweem normal AP mode
+ * This is needed to differentiate in firmware between normal AP mode
  * with smart monitor AP mode
  */
 #define WMI_UNIFIED_VDEV_SUBTYPE_SMART_MON  0x7
@@ -12952,10 +12952,10 @@ typedef enum {
 #define WMI_HECAP_PHY_LDPC_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 13, 1)
 #define WMI_HECAP_PHY_LDPC_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 13, 1, value)
 
-/* Below 2 macros are for maintaining backward compatability - Deprecated use WMI_HECAP_PHY_LDPC instead */
+/* Below 2 macros are for maintaining backward compatibility - Deprecated use WMI_HECAP_PHY_LDPC instead */
 #define WMI_HECAP_PHY_TXLDPC_GET_D2(he_cap_phy) WMI_HECAP_PHY_LDPC_GET_D2(he_cap_phy)
 #define WMI_HECAP_PHY_TXLDPC_SET_D2(he_cap_phy, value) WMI_HECAP_PHY_LDPC_SET_D2(he_cap_phy, value)
-/* Below 2 macros are for maintaining backward compatability - Deprecated use WMI_HECAP_PHY_LDPC instead */
+/* Below 2 macros are for maintaining backward compatibility - Deprecated use WMI_HECAP_PHY_LDPC instead */
 #define WMI_HECAP_PHY_RXLDPC_GET_D2(he_cap_phy) WMI_HECAP_PHY_LDPC_GET_D2(he_cap_phy)
 #define WMI_HECAP_PHY_RXLDPC_SET_D2(he_cap_phy, value) WMI_HECAP_PHY_LDPC_SET_D2(he_cap_phy, value)
 
@@ -13346,13 +13346,13 @@ typedef enum {
 #define WMI_HECAP_MAC_MBSS_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 31, 1, value)
 
 /* BSRP A-MPDU Aggregation
- * maintaining compatability since we dont support this now so not wasting memory
+ * maintaining compatibility since we don't support this now so not wasting memory
  */
 #define WMI_HECAP_MAC_BSRPAMPDU_GET_D2(he_cap) (0)
 #define WMI_HECAP_MAC_BSRPAMPDU_SET_D2(he_cap, value) {;}
 
 /* Quiet Time Period (QTP) operation
- * maintaining compatability since we dont support this now so not wasting memory
+ * maintaining compatibility since we don't support this now so not wasting memory
  */
 #define WMI_HECAP_MAC_QTP_GET_D2(he_cap) (0)
 #define WMI_HECAP_MAC_QTP_SET_D2(he_cap, value) {;}
@@ -13360,7 +13360,7 @@ typedef enum {
 /* support by an AP for receiving an (A-)MPDU that contains a BQR in the
  * A-Control subfield and support by a non-AP STA for generating an (A-)MPDU
  * that contains a BQR in the A-Control subfield
- * maintaining compatability since we dont support this now so not wasting memory
+ * maintaining compatibility since we don't support this now so not wasting memory
  */
 #define WMI_HECAP_MAC_ABQR_GET_D2(he_cap) (0)
 #define WMI_HECAP_MAC_ABQR_SET_D2(he_cap, value) {;}
@@ -13397,7 +13397,7 @@ typedef enum {
 #define WMI_HECAP_PHY_CBMODE_SET_D2(he_cap_phy, value) WMI_HECAP_PHY_CBMODE_SET_D2(he_cap_phy, value)
 
 
-/* Below 2 macros are for maintaining backward compatability - Deprecated use WMI_HECAP_PHY_LTFGIFORHE_GET instead */
+/* Below 2 macros are for maintaining backward compatibility - Deprecated use WMI_HECAP_PHY_LTFGIFORHE_GET instead */
 #define WMI_HECAP_PHY_OLTF_GET_D2(he_cap_phy) WMI_HECAP_PHY_LTFGIFORHE_GET_D2(he_cap_phy)
 #define WMI_HECAP_PHY_OLTF_SET_D2(he_cap_phy, value) WMI_HECAP_PHY_LTFGIFORHE_SET_D2(he_cap_phy, value)
 
@@ -13493,13 +13493,13 @@ typedef struct {
     A_UINT32 flags;
     /** ssid field. Only valid for AP/GO/IBSS/BTAmp VDEV type. */
     wmi_ssid ssid;
-    /** beacon/probe reponse xmit rate. Applicable for SoftAP. */
+    /** beacon/probe response xmit rate. Applicable for SoftAP. */
     /** This field will be invalid and ignored unless the */
     /** flags field has the WMI_UNIFIED_VDEV_START_BCN_TX_RATE_PRESENT bit. */
     /** When valid, this field contains the fixed tx rate for the beacon */
     /** and probe response frames send by the GO or SoftAP */
     A_UINT32 bcn_tx_rate;
-    /** beacon/probe reponse xmit power. Applicable for SoftAP. */
+    /** beacon/probe response xmit power. Applicable for SoftAP. */
     A_UINT32 bcn_txPower;
     /** number of p2p NOA descriptor(s) from scan entry */
     A_UINT32 num_noa_descriptors;
@@ -13533,7 +13533,7 @@ typedef struct {
     A_UINT32 eht_ops;
     A_UINT32 puncture_20mhz_bitmap; /* each bit indicates one 20 MHz BW punctured */
 
-    A_UINT32 mbssid_multi_group_flag; /* Flag to indentify whether multi group mbssid is supported */
+    A_UINT32 mbssid_multi_group_flag; /* Flag to identify whether multi group mbssid is supported */
     A_UINT32 mbssid_multi_group_id; /* Group id of current vdev only valid when multi group mbssid is supported */
 
 /* The TLVs follows this structure:
@@ -13760,7 +13760,7 @@ typedef enum {
     WMI_VDEV_PARAM_BEACON_INTERVAL,                           /* 0x3 */
     /** Listen interval in TUs */
     WMI_VDEV_PARAM_LISTEN_INTERVAL,                           /* 0x4 */
-    /** muticast rate in Mbps */
+    /** multicast rate in Mbps */
     WMI_VDEV_PARAM_MULTICAST_RATE,                            /* 0x5 */
     /** management frame rate in Mbps */
     WMI_VDEV_PARAM_MGMT_TX_RATE,                              /* 0x6 */
@@ -13780,7 +13780,7 @@ typedef enum {
     WMI_VDEV_PARAM_DTIM_PERIOD,                               /* 0xd */
     /** scheduler air time limit for this VDEV. used by off chan scheduler  */
     WMI_VDEV_OC_SCHEDULER_AIR_TIME_LIMIT,                     /* 0xe */
-    /** enable/dsiable WDS for this VDEV  */
+    /** enable/disable WDS for this VDEV  */
     WMI_VDEV_PARAM_WDS,                                       /* 0xf */
     /** ATIM Window */
     WMI_VDEV_PARAM_ATIM_WINDOW,                               /* 0x10 */
@@ -14013,7 +14013,7 @@ typedef enum {
     WMI_VDEV_PARAM_STATS_AVG_FACTOR,                          /* 0x4b */
 
     /** disconnect threshold, once the consecutive error for specific peer
-     * exceed this threhold, FW will send kickout event to host */
+     * exceed this threshold, FW will send kickout event to host */
     WMI_VDEV_PARAM_DISCONNECT_TH,                             /* 0x4c */
 
     /** The rate_code of RTS_CTS changed by host. Now FW can support
@@ -14337,7 +14337,7 @@ typedef enum {
      * resides with default BDF setting) & host wants to disable GTX,
      * the VDEV does not exercise any more TPC changes on the GTX supported
      * rates & goes to a default GTX SM where all PPDU's sent on default TPC.
-     * Whenever, host wants to reenable GTX, the enable command resumes the
+     * Whenever, host wants to re-enable GTX, the enable command resumes the
      * GTX functionality & TPC convergence to lower power levels can be
      * attained as long as PER on GTX supported rates is within the pre-defined
      * PER margin configured through the BDF.
@@ -14491,7 +14491,7 @@ typedef enum {
      * Bits 23:16 - TID_VALID_HI_PRI(8)
      * Bits 31:24 - TID_VALID_LOW_PRI(8)
      *
-     * The below macros can be used to set/get the relevent fields.
+     * The below macros can be used to set/get the relevant fields.
      * WMI_MSDU_FLOW_ASTX_MSDU_FLOW_MASKS_GET(msdu_flow_config1, ast_x)
      * WMI_MSDU_FLOW_ASTX_MSDU_FLOW_MASKS_SET(msdu_flow_config1, ast_x, mask)
      * WMI_MSDU_FLOW_TID_VALID_HI_MASKS_GET(msdu_flow_config1)
@@ -14552,7 +14552,7 @@ typedef enum {
      * (SRG = Spatial Reuse Group)
      * The accepted values are in between 0x00 and 0xFF, inclusive.
      * The parameter value is programmed into the appropriate spatial reuse
-     * regsiter, to specify how low the background signal strength from
+     * register, to specify how low the background signal strength from
      * neighboring BSS cells must be, for this AP to employ spatial reuse.
      *
      * The value of the parameter is compared against the OBSS RSSI in dB.
@@ -14566,7 +14566,7 @@ typedef enum {
      * BSS cells is no more than 10 dB.
      *
      * If Bit 29 is set, then input value will be in dBm. This is used
-     * for chipsets that uses dBm for comparision across MAC/Phy blocks.
+     * for chipsets that use dBm for comparison across MAC/Phy blocks.
      * Older chipsets support input in dB units. For newer chipsets, dBm
      * units will be used.
      * The host will use the WMI_SERVICE_SRG_SRP_SPATIAL_REUSE_SUPPORT
@@ -15134,9 +15134,9 @@ WMI_VDEV_PARAM_ROAM_FW_OFFLOAD WMI_VDEV_PARAM **/
 
 /** the definition of different START/RESTART Event response  */
 typedef enum {
-    /* Event respose of START CMD */
+    /* Event response of START CMD */
     WMI_VDEV_START_RESP_EVENT = 0,
-    /* Event respose of RESTART CMD */
+    /* Event response of RESTART CMD */
     WMI_VDEV_RESTART_RESP_EVENT,
 } WMI_START_EVENT_PARAM;
 
@@ -15214,7 +15214,7 @@ typedef struct {
 } wmi_vdev_bss_max_idle_time_cmd_fixed_param;
 
 /** VDEV start response status codes */
-#define WMI_VDEV_START_RESPONSE_STATUS_SUCCESS 0x0  /** VDEV succesfully started */
+#define WMI_VDEV_START_RESPONSE_STATUS_SUCCESS 0x0  /** VDEV successfully started */
 #define WMI_VDEV_START_RESPONSE_INVALID_VDEVID  0x1  /** requested VDEV not found */
 #define WMI_VDEV_START_RESPONSE_NOT_SUPPORTED  0x2  /** unsupported VDEV combination */
 #define WMI_VDEV_START_RESPONSE_DFS_VIOLATION  0x3  /** DFS_VIOLATION since channel in the NOL is selected */
@@ -15650,7 +15650,7 @@ enum wmi_sta_ps_param_tx_wake_threshold {
  */
 enum wmi_sta_ps_param_pspoll_count {
     WMI_STA_PS_PSPOLL_COUNT_NO_MAX = 0,
-/* Values greater than 0 indicate the maximum numer of PS-Poll frames FW
+/* Values greater than 0 indicate the maximum number of PS-Poll frames FW
  * will send before waking up.
  */
 };
@@ -15869,7 +15869,7 @@ typedef struct {
     A_UINT32 value;
 } wmi_ap_ps_peer_cmd_fixed_param;
 
-/** Configure peer station 11v U-APSD coexistance
+/** Configure peer station 11v U-APSD coexistence
  *
  * Two parameters from uaspd coexistence ie info (as specified in 11v) are
  * sent down to FW along with this command.
@@ -15910,7 +15910,7 @@ typedef struct {
      * 1 -> enabled
      */
     A_UINT32 enabled;
-    /** Duration/Interval as defined by 11v U-ASPD coexistance */
+    /** Duration/Interval as defined by 11v U-ASPD coexistence */
     A_UINT32 duration_interval;
     /** Upper 32 bits of 64-bit TSF offset */
     A_UINT32 tsf_offset_high;
@@ -15975,7 +15975,7 @@ typedef enum {
 } wmi_ap_ps_egap_status_type;
 
 /**
- * send ehanced green ap status to host
+ * send enhanced green ap status to host
  */
 typedef struct
 {
@@ -16237,7 +16237,7 @@ enum peer_rate_report_cond_phy_type {
 };
 
 typedef struct {
-    A_UINT32 tlv_header;                     /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_rate_report_condtion_fixed_param */
+    A_UINT32 tlv_header;                     /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_rate_report_condition_fixed_param */
     A_UINT32 enable_rate_report;             /* 1= enable, 0=disable */
     A_UINT32 report_backoff_time;            /* in unit of msecond */
     A_UINT32 report_timer_period;            /* in unit of msecond */
@@ -16530,7 +16530,7 @@ typedef struct {
     /** Number of AC to specify */
     A_UINT32 num_ac;
 /*
- * Following this struc is the TLV:
+ * Following this struct is the TLV:
  *     wmi_sta_uapsd_auto_trig_param ac_param[]; <-- Variable number of AC parameters (defined by field num_ac)
  */
 
@@ -16753,7 +16753,7 @@ typedef struct {
     wmi_mac_addr peer_macaddr;
     /** parameter id   */
     A_UINT32 param_id;
-    /** parametr value */
+    /** parameter value */
     A_UINT32 param_value;
 } wmi_peer_set_param_cmd_fixed_param;
 
@@ -16789,10 +16789,10 @@ typedef union {
  *   tx_rate = else: invalid
  */
 enum {
-    WMI_MAX_CCK_TX_RATE_1M,       /* up to 1M CCK Rate avaliable */
-    WMI_MAX_CCK_TX_RATE_2M,       /* up to 2M CCK Rate avaliable */
-    WMI_MAX_CCK_TX_RATE_5_5M,     /* up to 5.5M CCK Rate avaliable */
-    WMI_MAX_CCK_TX_RATE_11M,      /* up to 11M CCK Rate avaliable */
+    WMI_MAX_CCK_TX_RATE_1M,       /* up to 1M CCK Rate available */
+    WMI_MAX_CCK_TX_RATE_2M,       /* up to 2M CCK Rate available */
+    WMI_MAX_CCK_TX_RATE_5_5M,     /* up to 5.5M CCK Rate available */
+    WMI_MAX_CCK_TX_RATE_11M,      /* up to 11M CCK Rate available */
     WMI_MAX_CCK_TX_RATE = WMI_MAX_CCK_TX_RATE_11M,
 };
 
@@ -16808,14 +16808,14 @@ enum {
  *   tx_rate = else: invalid
  */
 enum {
-    WMI_MAX_OFDM_TX_RATE_6M,      /* up to 6M OFDM Rate avaliable */
-    WMI_MAX_OFDM_TX_RATE_9M,      /* up to 9M OFDM Rate avaliable */
-    WMI_MAX_OFDM_TX_RATE_12M,     /* up to 12M OFDM Rate avaliable */
-    WMI_MAX_OFDM_TX_RATE_18M,     /* up to 18M OFDM Rate avaliable */
-    WMI_MAX_OFDM_TX_RATE_24M,     /* up to 24M OFDM Rate avaliable */
-    WMI_MAX_OFDM_TX_RATE_36M,     /* up to 36M OFDM Rate avaliable */
-    WMI_MAX_OFDM_TX_RATE_48M,     /* up to 48M OFDM Rate avaliable */
-    WMI_MAX_OFDM_TX_RATE_54M,     /* up to 54M OFDM Rate avaliable */
+    WMI_MAX_OFDM_TX_RATE_6M,      /* up to 6M OFDM Rate available */
+    WMI_MAX_OFDM_TX_RATE_9M,      /* up to 9M OFDM Rate available */
+    WMI_MAX_OFDM_TX_RATE_12M,     /* up to 12M OFDM Rate available */
+    WMI_MAX_OFDM_TX_RATE_18M,     /* up to 18M OFDM Rate available */
+    WMI_MAX_OFDM_TX_RATE_24M,     /* up to 24M OFDM Rate available */
+    WMI_MAX_OFDM_TX_RATE_36M,     /* up to 36M OFDM Rate available */
+    WMI_MAX_OFDM_TX_RATE_48M,     /* up to 48M OFDM Rate available */
+    WMI_MAX_OFDM_TX_RATE_54M,     /* up to 54M OFDM Rate available */
     WMI_MAX_OFDM_TX_RATE = WMI_MAX_OFDM_TX_RATE_54M,
 };
 
@@ -17109,17 +17109,17 @@ typedef struct {
     A_UINT32 peer_caps;
     /** Listen interval */
     A_UINT32 peer_listen_intval;
-    /** HT capabilties of the peer */
+    /** HT capabilities of the peer */
     A_UINT32 peer_ht_caps;
     /** maximum rx A-MPDU length */
     A_UINT32 peer_max_mpdu;
     /** mpdu density of the peer in usec(0 to 16) */
     A_UINT32 peer_mpdu_density;
-    /** peer rate capabilties see flags above */
+    /** peer rate capabilities see flags above */
     A_UINT32 peer_rate_caps;
     /** num spatial streams */
     A_UINT32 peer_nss;
-    /** VHT capabilties of the peer */
+    /** VHT capabilities of the peer */
     A_UINT32 peer_vht_caps;
     /** phy mode */
     A_UINT32 peer_phymode;
@@ -17217,9 +17217,9 @@ typedef struct {
 
     /* 802.11be capabilities and other params */
     A_UINT32 puncture_20mhz_bitmap; /* each bit indicates one 20Mhz bw puntured */
-    /* EHT mac capabilites from BSS beacon EHT cap IE, total WMI_MAX_EHTCAP_MAC_SIZE*A_UINT32 bits */
+    /* EHT mac capabilities from BSS beacon EHT cap IE, total WMI_MAX_EHTCAP_MAC_SIZE*A_UINT32 bits */
     A_UINT32 peer_eht_cap_mac[WMI_MAX_EHTCAP_MAC_SIZE];
-    /* EHT phy capabilites from BSS beacon EHT cap IE, total WMI_MAX_EHTCAP_PHY_SIZE*A_UINT32 bits */
+    /* EHT phy capabilities from BSS beacon EHT cap IE, total WMI_MAX_EHTCAP_PHY_SIZE*A_UINT32 bits */
     A_UINT32 peer_eht_cap_phy[WMI_MAX_EHTCAP_PHY_SIZE];
     A_UINT32 peer_eht_ops;
     wmi_ppe_threshold peer_eht_ppet;
@@ -17227,7 +17227,7 @@ typedef struct {
 /* Following this struct are the TLV's:
  *     A_UINT8 peer_legacy_rates[];
  *     A_UINT8 peer_ht_rates[];
- *     wmi_vht_rate_set peer_vht_rates; <-- VHT capabilties of the peer
+ *     wmi_vht_rate_set peer_vht_rates; <-- VHT capabilities of the peer
  *     WMI_he_rate_set_peer_he_rates; <-- HE capabilities of the peer
  *     wmi_peer_assoc_mlo_params  mlo_params[0,1]; <-- MLO parameters opt. TLV
  *         Only present for MLO peers.
@@ -17433,7 +17433,7 @@ typedef struct _wlan_dcs_im_tgt_stats {
     A_UINT32 reg_tsf32;
 
     /** Known last frame rssi, in case of multiple stations, if
-     *  and at different ranges, this would not gaurantee that
+     *  and at different ranges, this would not guarantee that
      *  this is the least rssi.
      */
     A_UINT32 last_ack_rssi;
@@ -17471,7 +17471,7 @@ typedef struct _wlan_dcs_im_tgt_stats {
     /** total cycle counts MAC_PCU_CYCLE_CNT_ADDRESS */
     A_UINT32 reg_cycle_cnt; /* delta cycle count */
 
-    /** extenstion channel rx clear count  */
+    /** extension channel rx clear count  */
     A_UINT32 reg_rxclr_ext_cnt;
 
     /** OFDM phy error counts, MAC_PCU_PHY_ERR_CNT_1_ADDRESS */
@@ -17540,7 +17540,7 @@ typedef struct {
  * elements (not arrays).     union { wlan_dcs_cw_int cw_int; wlan_dcs_im_tgt_stats_t   wlan_stat; } int_event;
  *
  *       wlan_dcs_cw_int            cw_int[];   <-- cw_interference event
- *       wlan_dcs_im_tgt_stats_t   wlan_stat[]; <-- wlan im interfernce stats
+ *       wlan_dcs_im_tgt_stats_t   wlan_stat[]; <-- wlan im interference stats
  *       wmi_dcs_awgn_int_t        awgn_int[];  <-- Additive white Gaussian noise (awgn) interference
  */
 } wmi_dcs_interference_event_fixed_param;
@@ -17642,7 +17642,7 @@ typedef struct {
 #define WMI_ROAM_SCAN_STOP_CMD 0x1
 
 /**
- * WMI_ROAM_SCAN_RSSI_THRESHOLD : set scan rssi thresold
+ * WMI_ROAM_SCAN_RSSI_THRESHOLD : set scan rssi threshold
  *  scan rssi threshold is the rssi threshold below which the FW will start running Roam scans.
  * Applicable when WMI_ROAM_SCAN_MODE is not set to none.
  */
@@ -17779,7 +17779,7 @@ typedef struct {
     A_UINT32 penalty_algorithm_5g; /** 0 == fixed, 1 == linear, 2 == logarithm ..etc */
     A_UINT32 penalty_factor_5g; /** factor by which 5GHz RSSI is penalized */
     A_UINT32 max_boost_5g; /** maximum boost that can be applied to a 5GHz RSSI */
-    A_UINT32 max_penalty_5g; /** maximum penality that can be applied to a 5GHz RSSI */
+    A_UINT32 max_penalty_5g; /** maximum penalty that can be applied to a 5GHz RSSI */
     A_UINT32 good_rssi_threshold; /**  RSSI below which roam is kicked in by background scan, although rssi is still good */
 } wmi_roam_scan_extended_threshold_param;
 
@@ -18217,7 +18217,7 @@ typedef struct {
      */
     A_UINT32 oce_ap_subnet_id_weightage_pcnt;
     /*
-     * Give weightage to SAE-PK (Simulataneous Authentication of Equals -
+     * Give weightage to SAE-PK (Simultaneous Authentication of Equals -
      * Public Key) enabled network APs.
      * Only used if sae_pk_ap_weightage_pcnt != 0.
      */
@@ -18288,11 +18288,11 @@ typedef struct {
     A_UINT32 flags;
     /**
      * rssi threshold value in dB: the value of the candidate AP should
-     * higher by this threshold than the rssi of the currrently associated AP.
+     * higher by this threshold than the rssi of the currently associated AP.
      */
     A_UINT32 rssi_threshold;
     /**
-     * ssid vlaue to be matched.
+     * ssid value to be matched.
      */
     wmi_ssid ssid;
 
@@ -18317,7 +18317,7 @@ typedef struct {
     /**
      * bg_rssi_threshold value in dB: For background scan the value of
      * the candidate AP should be higher by this threshold than the rssi
-     * of the currrently associated AP.
+     * of the currently associated AP.
      */
     A_UINT32 bg_rssi_threshold;
 } wmi_ap_profile;
@@ -18422,7 +18422,7 @@ typedef struct {
      */
     A_UINT32 flags;
     /**
-     * RSSI threshold in dBm above which roaming scan will be supressed
+     * RSSI threshold in dBm above which roaming scan will be suppressed
      * during some roaming trigger.
      */
     A_INT32 roam_data_rssi_thres;
@@ -18566,7 +18566,7 @@ typedef struct {
 
 /**
  * WMI_OFL_SCAN_PERIOD: period in msec for offload scan.
- *  0 will disable ofload scan and a very low value will perform a continous
+ *  0 will disable ofload scan and a very low value will perform a continuous
  *  scan.
  */
 typedef struct {
@@ -18901,7 +18901,7 @@ typedef enum
 #define WMI_ROAM_NOTIF_SCAN_END          0xc /** indicate roam scan end, notif_params to be sent as WMI_ROAM_TRIGGER_REASON_ID */
 
 /**whenever RIC request information change, host driver should pass all ric related information to firmware (now only support tsepc)
-* Once, 11r roaming happens, firmware can generate RIC request in reassoc request based on these informations
+* Once, 11r roaming happens, firmware can generate RIC request in reassoc request based on this information
 */
 typedef struct
 {
@@ -19287,7 +19287,7 @@ typedef struct {
 } wmi_p2p_go_set_probe_resp_ie;
 
 /** WMI_P2P_SET_VENDOR_IE_DATA_CMDID: Vendor specific P2P IE data, which will
- *  be used by the FW to parse the P2P NoA attribute in beacons, probe resposes
+ *  be used by the FW to parse the P2P NoA attribute in beacons, probe responses
  *  and action frames received by the P2P Client.
  *  Note: This command is currently used only for Apple P2P implementation.
  */
@@ -19304,7 +19304,7 @@ typedef struct {
 typedef struct {
     A_UINT32 pattern_type;
 /**
- * TLV (tag length value)  paramerters follow the pattern structure.
+ * TLV (tag length value) parameters follow the pattern structure.
  * TLV can contain bssid list, ssid list and
  * ie. the TLV tags are defined above;
  */
@@ -19334,7 +19334,7 @@ typedef struct {
     /* p2p find full channel number */
     A_UINT32 num_scan_chans;
 /**
- * TLV (tag length value)  paramerters follow the pattern structure.
+ * TLV (tag length value) parameters follow the pattern structure.
  * TLV  contain channel list in MHz
  */
 } wmi_p2p_disc_offload_config_cmd;
@@ -19721,7 +19721,7 @@ typedef enum {
 } WOW_IFACE_STATUS;
 
 enum {
-    WMI_WOW_FLAG_IGNORE_PCIE_RESET          = 0x00000001, /* some win10 platfrom will not assert pcie_reset for wow.*/
+    WMI_WOW_FLAG_IGNORE_PCIE_RESET          = 0x00000001, /* some win10 platform will not assert pcie_reset for wow.*/
     /* WMI_WOW_FLAG_SEND_PM_PME
      * Some platforms have issues if the PM_PME message is sent after WoW,
      * so don't send PM_PME after WoW unless the host uses this flag
@@ -19736,7 +19736,7 @@ enum {
     WMI_WOW_FLAG_ENABLE_DRV_PCIE_L1SS_SLEEP = 0x00000010,
     /*
      * To differentiate system suspend Vs RTPM BIT set -
-     * Sytem Suspend WOW, BIT Reset- RTPM (DRV)
+     * System Suspend WOW, BIT Reset- RTPM (DRV)
      */
     WMI_WOW_FLAG_SYSTEM_SUSPEND_WOW         = 0x00000020,
     /*
@@ -19976,7 +19976,7 @@ typedef struct {
                           * If init_state is 0, a low --> high transition
                           * causes a host wakeup interrupt.
                           * If init_state is 1, a high --> low transition
-                          * causes a host wakeup interrrupt.
+                          * causes a host wakeup interrupt.
                           */
 } WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMD_fixed_param;
 
@@ -20095,7 +20095,7 @@ typedef struct {
     A_UINT32 coapmsg_len;     /* keeplive CoAP message length */
 /* The below TLV (tag length value) parameters follow this fixed_param TLV:
  *     A_UINT8 coapmsg[];  CoAP keepalive message,
- *          length specifed by coapmsg_len field
+ *          length specified by coapmsg_len field
  */
 } WMI_WOW_COAP_ADD_KEEPALIVE_PATTERN_CMD_fixed_param;
 
@@ -20184,7 +20184,7 @@ typedef struct wow_event_info_section_bitmap_s {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WOW_EVENT_INFO_SECTION_BITMAP  */
     A_UINT32 flag; /*This is current reserved.*/
     A_UINT32 value; /*This could be the pattern id for bitmap pattern.*/
-    A_UINT32 org_len; /*The length of the orginal packet.*/
+    A_UINT32 org_len; /*The length of the original packet.*/
 } WOW_EVENT_INFO_SECTION_BITMAP;
 
 /**
@@ -20314,7 +20314,7 @@ typedef struct {
     A_UINT32 rc4_read_x;
     A_UINT32 rc4_read_y;
 
-    /* used to caculate HMAC hash for transmit packet such as keep-alive */
+    /* used to calculate HMAC hash for transmit packet such as keep-alive */
     A_UINT8  ssl_write_seq[8];
     A_UINT8  ssl_sha1_write_key[64];
     A_UINT32 ssl_sha1_write_key_len;
@@ -20437,7 +20437,7 @@ typedef struct {
     A_UINT32 timeout;
     A_UINT32 length;
     /*Following this would be the pattern
-       A_UINT8 pattern[] of length specifed by length
+       A_UINT8 pattern[] of length specified by length
        field in the structure.*/
 } WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMD_fixed_param;
 
@@ -20533,7 +20533,7 @@ typedef struct {
     A_UINT32 vdev_id;
     /** Number of requested SSN In the TLV wmi_ba_req_ssn[] */
     A_UINT32 num_ba_req_ssn;
-/* Following this struc are the TLV's:
+/* Following this struct are the TLV's:
  *     wmi_ba_req_ssn ba_req_ssn_list; All peer and tidBitMap for which the ssn is requested
  */
 } wmi_ba_req_ssn_cmd_fixed_param;
@@ -20572,7 +20572,7 @@ typedef struct {
     A_UINT32 status;
     /** Number of requested SSN In the TLV wmi_ba_req_ssn[] */
     A_UINT32 num_ba_event_ssn;
-/* Following this struc are the TLV's:
+/* Following this struct are the TLV's:
  *     wmi_ba_event_ssn ba_event_ssn_list; All peer and tidBitMap for which the ssn is requested
  */
 } wmi_ba_rsp_ssn_event_fixed_param;
@@ -20586,7 +20586,7 @@ enum wmi_aggr_state_req_type {
 
 /*
  * This event is generated by the COEX module
- * when esco call is begins the coex module in fw genrated this event to host to
+ * when esco call is begins the coex module in fw generated this event to host to
  * disable the RX aggregation and after completion of the esco call fw will indicate to
  * enable back the Rx aggregation .
 */
@@ -20759,7 +20759,7 @@ typedef struct nlo_channel_prediction_cfg {
     A_UINT32 top_k_num;
     /* Preconfigured stationary threshold.
      * Lesser value means more conservative. Bigger value means more aggressive.
-     * Maximum is 100 and mininum is 0. */
+     * Maximum is 100 and minimum is 0. */
     A_UINT32 stationary_threshold;
     /* Periodic full channel scan in milliseconds unit.
      * After full_scan_period_ms since last full scan, channel prediction
@@ -21012,11 +21012,11 @@ typedef struct _chatter_pkt_coalescing_hdr_test {
 /** packet coalescing filter*/
 typedef struct _chatter_pkt_coalescing_filter {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_chatter_pkt_coalescing_filter */
-    A_UINT32 filter_id; /*unique id assigned by OS*/
-    A_UINT32 max_coalescing_delay; /*max miliseconds 1st pkt can be hold*/
-    A_UINT32 pkt_type; /*unicast/multicast/broadcast*/
-    A_UINT32 num_of_test_field; /*number of field test in table*/
-    chatter_pkt_coalescing_hdr_test test_fields[CHATTER_MAX_FIELD_TEST]; /*field test tbl*/
+    A_UINT32 filter_id; /* unique id assigned by OS */
+    A_UINT32 max_coalescing_delay; /* max milliseconds 1st pkt can be held */
+    A_UINT32 pkt_type; /* unicast/multicast/broadcast */
+    A_UINT32 num_of_test_field; /* number of field test in table */
+    chatter_pkt_coalescing_hdr_test test_fields[CHATTER_MAX_FIELD_TEST]; /* field test tbl */
 } chatter_pkt_coalescing_filter;
 
 /** packet coalescing filter add command*/
@@ -21156,7 +21156,7 @@ typedef struct {
     A_UINT32 method; /* keep alive method */
     A_UINT32 interval; /* time interval in seconds  */
 /*
- * NOTE: following this structure is the TLV for ARP Resonse:
+ * NOTE: following this structure is the TLV for ARP Response:
  *     WMI_STA_KEEPALVE_ARP_RESPONSE arp_resp; <-- ARP response
  */
 } WMI_STA_KEEPALIVE_CMD_fixed_param;
@@ -21425,7 +21425,7 @@ typedef struct {
     /** number of NoA desc. In the TLV noa_descriptor[] */
     A_UINT32 num_noa;
     /**
-     * TLV (tag length value)  paramerters follow the pattern structure.
+     * TLV (tag length value) parameters follow the pattern structure.
      * TLV  contain NoA desc with num of num_noa
      */
 } wmi_p2p_set_noa_cmd_fixed_param;
@@ -22765,7 +22765,7 @@ typedef struct {
      *   The number of probe requests specified depends on the ssid_list and bssid_list
      */
     A_UINT32 repeat_probe_time;
-    /** time in msec between 2 consequetive probe requests with in a set. */
+    /** time in msec between 2 consecutive probe requests with in a set. */
     A_UINT32 probe_spacing_time;
     /** data inactivity time in msec on bss channel that will be used by scanner for measuring the inactivity  */
     A_UINT32 idle_time;
@@ -22904,7 +22904,7 @@ typedef struct {
     A_UINT32 tlv_header;
     /** gpip pin number */
     A_UINT32 gpio_pin_num;
-    /** gpio interupt type */
+    /** gpio interrupt type */
     A_UINT32 int_type;
     /** RF radio status */
     A_UINT32 radio_state;
@@ -23103,7 +23103,7 @@ typedef struct {
      * If number of msdus in a queue excess over qdepth_thresh_value value
      * while queuing msdu's then we drop new msdus.
      * (Though dropping older (stale) data rather than newer data might be
-     * preferable, the dropping is performed by MAC HW, and theres no option
+     * preferable, the dropping is performed by MAC HW, and there's no option
      * to configure the HW to do head dropping rather than tail dropping.)
      */
     A_UINT32 qdepth_thresh_value;
@@ -23449,7 +23449,7 @@ enum wmi_rmc_mode {
 
 /** Enable RMC transmitter functionality. Upon
  *  receiving this, the FW shall mutlicast frames with
- *  reliablity. This is a vendor
+ *  reliability. This is a vendor
  *  proprietary feature. */
 typedef struct {
     /** TLV tag and len; tag equals
@@ -23603,7 +23603,7 @@ typedef struct {
     /** RSSI recorded in the ppdu */
     A_UINT8  rssi;
 
-    /** extened RSSI info */
+    /** extended RSSI info */
     A_UINT8  rssi_ext;
 
     union {
@@ -23726,7 +23726,7 @@ typedef struct {
  *  array of wmi_tpc_chainmask_config structures are passed with the command to specify multiple conditions.
  *
  *  The set of conditions include bt status, stbc status, band, phy_mode, 1stream/2streams, channel, rate. when all these conditions meet,
- *  the output(tpc_offset,chainmask) will be applied on per packet basis. ack_offset is applied based on channel condtion only. When multiple
+ *  the output(tpc_offset,chainmask) will be applied on per packet basis. ack_offset is applied based on channel condition only. When multiple
  *  conditions has the same channel ,then the first ack_offset will be applied. It is better for host driver to make sure the
  *  <channel, ack_offset> pair is unique.
  *
@@ -23845,8 +23845,8 @@ typedef struct {
 typedef struct {
     A_UINT32 tlv_header;
     /** Basic condition defined as bit map above, bitmap is chosen to save memory.
-     * Bit0  ~ Bit4: tpc offset which will be adjusted if condtion matches, the unit is 0.5dB.  bit4 indicates signed
-     * Bit5  ~ Bit9: ack offset which will be adjusted if condtion matches, the unit is 0.5dB.  bit9 indicates signed
+     * Bit0  ~ Bit4: tpc offset which will be adjusted if condition matches, the unit is 0.5dB.  bit4 indicates signed
+     * Bit5  ~ Bit9: ack offset which will be adjusted if condition matches, the unit is 0.5dB.  bit9 indicates signed
      * Bit10 ~ Bit11: chainmask  b'00: don't care, b'01: force to use chain0, b'10: force to use chain1, b'11: force to use chain0&chain1
      * Bit12 ~ Bit13: bt condition  b'00: don't care, b'01: apply only when bt on, b'10: apply only when bt off,  b'11: reserved
      * Bit14 ~ Bit15: stbc condition  b'00: don't care, b'01: apply only when stbc on, b'10: apply only when stbc off, b'11: reserved
@@ -23891,7 +23891,7 @@ typedef struct {
 
 typedef struct {
     A_UINT32 tlv_header;
-    A_UINT32 enable;  /** enable to set tpc & chainmask when condtions meet, 0: disabled,   1: enabled.  */
+    A_UINT32 enable;  /** enable to set tpc & chainmask when conditions meet, 0: disabled,   1: enabled.  */
     A_UINT32 num_tpc_chainmask_configs;
     /** following this structure is num_tpc_chainmask_configs number of wmi_tpc_chainmask_config  */
 } wmi_tpc_chainmask_config_cmd_fixed_param;
@@ -25049,7 +25049,7 @@ typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_frame_event_fixed_param  */
     /** Unique id identifying the VDEV on which roaming is done by firmware */
     A_UINT32 vdev_id;
-    /* Exact frame length without considering 4 byte alignement */
+    /* Exact frame length without considering 4 byte alignment */
     A_UINT32 frame_length;
     A_INT32  rssi; /* Units in dBm */
     /* The frequency on which to transmit. */
@@ -25203,7 +25203,7 @@ enum {
 typedef struct {
     /**
      * TLV tag and len;
-     * tag equals WMITLV_TAG_STRUC_wmi_obss_scan_enalbe_cmd_fixed_param
+     * tag equals WMITLV_TAG_STRUC_wmi_obss_scan_enable_cmd_fixed_param
      */
     A_UINT32 tlv_header;
     A_UINT32 vdev_id;
@@ -25243,7 +25243,7 @@ typedef struct {
     A_UINT32 current_operating_class; /** STA current operating class */
     /** length of 2.4GHz channel list to scan at, channel number list in tlv->channels[] */
     A_UINT32 channel_len;
-    /** length of optional ie data to append to probe reqest when active scan, ie data in tlv->ie_field[] */
+    /** length of optional ie data to append to probe request when active scan, ie data in tlv->ie_field[] */
     A_UINT32 ie_len;
 
 /**
@@ -25469,7 +25469,7 @@ typedef struct {
     A_UINT32     n_probes;
     /** time in msec between 2 sets of probe requests. */
     A_UINT32     repeat_probe_time;
-    /** time in msec between 2 consequetive probe requests with in a set. */
+    /** time in msec between 2 consecutive probe requests with in a set. */
     A_UINT32     probe_spacing_time;
     /** data inactivity time in msec on bss channel that will be used by scanner for measuring the inactivity  */
     A_UINT32     idle_time;
@@ -25896,21 +25896,21 @@ typedef enum {
 
 typedef struct {
     A_UINT32        tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */
-    /**bssid */
+    /** bssid */
     wmi_mac_addr    bssid;
-    /**time stamp in milliseconds */
+    /** time stamp in milliseconds */
     A_UINT32        tstamp;
-    /**upper RSSI limit */
+    /** upper RSSI limit */
     A_UINT32        upper_rssi_limit;
-    /**lower RSSI limit */
+    /** lower RSSI limit */
     A_UINT32        lower_rssi_limit;
     /** channel */
     A_UINT32        channel;    /* in MHz */
-    /**current RSSI average */
+    /** current RSSI average */
     A_UINT32        rssi_average;
-    /**flags - wmi_extscan_wlan_change_flags */
+    /** flags - wmi_extscan_wlan_change_flags */
     A_UINT32        flags;
-    /**legnth of RSSI history to follow (number of values) */
+    /** length of RSSI history to follow (number of values) */
     A_UINT32        num_rssi_samples;
 } wmi_extscan_wlan_change_result_bssid;
 
@@ -26106,7 +26106,7 @@ typedef struct {
 
 /**
   * set a given log level to all the modules specified in the module bitmap.
-  * and set the log levle for all other modules to DBGLOG_ERR.
+  * and set the log level for all other modules to DBGLOG_ERR.
   *  value: log levelt to be set.
   *  module_id_bitmap : identifies the modules for which the log level should be set and
   *                      modules for which the log level should be reset to DBGLOG_ERR.
@@ -26156,7 +26156,7 @@ typedef struct {
 
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_temperature_event_fixed_param */
-    A_INT32  value;     /* temprature value in Celcius degree */
+    A_INT32  value;     /* temperature value in Celcius degree */
     /** pdev_id for identifying the MAC
      * See macros starting with WMI_PDEV_ID_ for values.
      */
@@ -27837,8 +27837,8 @@ typedef struct {
     A_UINT32 vdev_id;
     wmi_mac_addr peer_macaddr; /* peer mac address */
     A_UINT32 tid; /* 0 to 15 = QoS TIDs, 16 = non-qos TID */
-    A_UINT32 queue_ptr_lo; /* lower 32 bits of queue desc adddress */
-    A_UINT32 queue_ptr_hi; /* upper 32 bits of queue desc adddress */
+    A_UINT32 queue_ptr_lo; /* lower 32 bits of queue desc address */
+    A_UINT32 queue_ptr_hi; /* upper 32 bits of queue desc address */
     A_UINT32 queue_no; /* 16-bit number assigned by host for queue,
                           stored in bits 15:0 of queue_no field */
     A_UINT32 ba_window_size_valid; /* Is ba_window_size valid?
@@ -28338,7 +28338,7 @@ typedef struct {
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_transfer_data_to_flash_cmd_fixed_param  */
     A_UINT32 offset; /* flash offset to write, starting from 0 */
-    A_UINT32 length; /* vaild data length in buffer, unit: byte */
+    A_UINT32 length; /* valid data length in buffer, unit: byte */
 } wmi_transfer_data_to_flash_cmd_fixed_param;
 
 typedef struct {
@@ -29756,7 +29756,7 @@ typedef struct {
     * FLAG_RTSENA        0x00001000 - RTS enabled
     * FLAG_CTSENA        0x00002000 - CTS enabled
     * FLAG_LDPC          0x00004000 - LDPC set
-    * FLAG_SGI           0x00008000 - Short gaurd interval
+    * FLAG_SGI           0x00008000 - Short guard interval
     *                   (0x00010000-0x00080000 unused)
     *------------------
     * 0x00100000-0x00700000 used for SU/MU/OFDMA tx mode
@@ -29976,7 +29976,7 @@ typedef struct {
     A_UINT32 vdev_id;
 
     /* LTE-WLAN coexistence scheme bitmap
-     * Indicates the final schemes applied for the currrent Coex scenario.
+     * Indicates the final schemes applied for the current Coex scenario.
      * Bit 0 - TDM policy
      * Bit 1 - Forced TDM policy
      * Bit 2 - Dynamic Power Back-off policy
@@ -30063,7 +30063,7 @@ typedef struct {
     A_UINT32 block_count;
 
     /* WLAN RSSI level
-     * WLAN RSSI is devided in to 3 levels i.e. Good/Moderate/Low (configurable inside f/w)
+     * WLAN RSSI is divided in to 3 levels i.e. Good/Moderate/Low (configurable inside f/w)
      * 0-Good, 1-Moderate, 2-Low
      */
     A_UINT32 wlan_rssi_level;
@@ -30383,7 +30383,7 @@ typedef enum wmi_coex_config_type {
     WMI_COEX_CONFIG_BTC_MODE            = 24, /* config BTC mode, arg1 mode: 0 TDD/1 FDD/2 Hybrid*/
     WMI_COEX_CONFIG_ANTENNA_ISOLATION   = 25, /* config isolation between BT and WLAN chains
                                                * The arguments are interpreted differently
-                                               * depending on whether the target suppports
+                                               * depending on whether the target supports
                                                * WMI_SERVICE_COEX_SUPPORT_UNEQUAL_ISOLATION
                                                * If (not COEX_SUPPORT_UNEQUAL_ISOLATION) or arg2 == 0:
                                                *     arg1 => isolation between BT and WLAN chains,
@@ -30597,7 +30597,7 @@ typedef struct {
  * wlan stats shall be understood as per period.
  * Generally, it is reported periodically based on the period specified by host.
  * But if the variation of one stats of compared to the
- * pervious notification exceeds a threshold,
+ * previous notification exceeds a threshold,
  * FW will report the wlan stats immediately.
  * The values of the stats becomes the new reference to compute variations.
  * This threshold can be a global setting or per category.
@@ -30612,7 +30612,7 @@ typedef struct {
  */
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_stats_threshold_cmd_fixed_param */
-    /** Indicate if threshold mechnism is enabled or disabled.
+    /** Indicate if threshold mechanism is enabled or disabled.
      *  It is disabled by default.
      *  Host can enable and disable it dynamically.
      */
@@ -30899,7 +30899,7 @@ typedef struct {
  * structure. The TLV's are:
  *
  *     A_UINT32 channel_weight[];
- *         values definied by enum 'wmi_pcl_chan_weight'
+ *         values defined by enum 'wmi_pcl_chan_weight'
  *         channel order & size will be as per the list provided in WMI_SCAN_CHAN_LIST_CMDID
  **/
 } wmi_vdev_set_pcl_cmd_fixed_param;
@@ -30967,7 +30967,7 @@ typedef enum wmi_hw_mode_config_type {
                                   */
     WMI_HW_MODE_DBS_OR_SBS  = 5, /* One PHY is on 5G and the other PHY can be in 2G or 5G. */
     WMI_HW_MODE_DBS_2G_5G   = 6, /* Both PHYs are active in different bands. PhyA 2G and PhyB 5G */
-    WMI_HW_MODE_2G_PHYB     = 7, /* Ony PhyB 2G active */
+    WMI_HW_MODE_2G_PHYB     = 7, /* Only PhyB 2G active */
     WMI_HW_MODE_EMLSR       = 8, /* Both PHYs are active in listen mode in 1x1
                                   * and Tx/Rx trigger on any PHY will switch
                                   * from 1x1 to 2x2 on that Phy
@@ -31046,12 +31046,12 @@ typedef enum wmi_hw_mode_config_type {
 
 /*
  * +-----------------------------+------------------------------------+
- * | Transmitted VHT Capablities |         NSS Support of STA         |
- * |       Information Field     |    transmitted VHT Capablites      |
+ * | Transmitted VHT Capabilities|         NSS Support of STA         |
+ * |       Information Field     |    transmitted VHT Capabilites     |
  * +---------------+-------------+------+------+------+------+--------+
  * |   Supported   |   Extended  |      |      |      |      |        |
  * |   Channel     |   NSS BW    |      |      |      |      |        |
- * |   WidthSet    |   Suppport  |20 Mhz|40 Mhz|80 Mhz|160Mhz|80+80Mhz|
+ * |   WidthSet    |   Support   |20 Mhz|40 Mhz|80 Mhz|160Mhz|80+80Mhz|
  * +---------------+-------------+------+------+------+------+--------+
  * |        0      |      0      |  1   |  1   |  1   |      |        |
  * +---------------+-------------+------+------+------+------+--------+
@@ -31556,7 +31556,7 @@ typedef struct {
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_MAC_PHY_CHAINMASK_COMBO */
     A_UINT32 chainmask_table_id;
-    /* Number of vaild Chainmask in the table */
+    /* Number of valid Chainmask in the table */
     A_UINT32 num_valid_chainmask;
 
     /**************************************************************************
@@ -32210,9 +32210,9 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID);
 
         /* RTT measurement related cmd */
-        /* reques to make an RTT measurement */
+        /* request to make an RTT measurement */
         WMI_RETURN_STRING(WMI_RTT_MEASREQ_CMDID);
-        /* reques to report a tsf measurement */
+        /* request to report a tsf measurement */
         WMI_RETURN_STRING(WMI_RTT_TSF_CMDID);
 
         /* spectral scan command */
@@ -32351,7 +32351,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_STA_SMPS_PARAM_CMDID);
 
         /* Wlan HB commands */
-        /* enalbe/disable wlan HB */
+        /* enable/disable wlan HB */
         WMI_RETURN_STRING(WMI_HB_SET_ENABLE_CMDID);
         /* set tcp parameters for wlan HB */
         WMI_RETURN_STRING(WMI_HB_SET_TCP_PARAMS_CMDID);
@@ -33681,7 +33681,7 @@ typedef enum {
 /**
  * WMI_BOARD_MCN_STRING_BUF_SIZE : represents the number of elements in board_mcn_detail.
  * Since board_mcn_detail is of type A_UINT8, the value of WMI_BOARD_MCN_STRING_BUF_SIZE
- * should be multiple of 4 for alignement reason. And the last byte byte is reserved for
+ * should be multiple of 4 for alignment reason. And the last byte byte is reserved for
  * null-terminator
  */
 #define WMI_BOARD_MCN_STRING_BUF_SIZE (WMI_BOARD_MCN_STRING_MAX_SIZE+1) /* null-terminator */
@@ -33986,7 +33986,7 @@ typedef struct {
  * The flags are used both in WMI_TWT_ENABLE_CMDID and WMI_TWT_DISABLE_CMDID.
  *
  * BIT4 represents whether the it is for REQUESTER or RESPONDER.
- * BIT5 represents whether it is invidual or broadcast mode.
+ * BIT5 represents whether it is individual or broadcast mode.
  *
  * For instance, in WMI_TWT_ENABLE_CMDID if BIT4=0 and BIT5=0, then we will
  * enable only Requester, we will not change any configuration of RESPONDER.
@@ -34685,7 +34685,7 @@ typedef struct {
     /**
      * The time taken by target in micro seconds to complete the reset routine
      * and re-initiate the spectral scan.
-     * If the delay is 0, the WAR to bookkeep the timestamp wont be exercised
+     * If the delay is 0, the WAR to bookkeep the timestamp won't be exercised
      * in HOST.
      */
     A_UINT32 reset_delay;
@@ -35365,11 +35365,11 @@ typedef enum {
     WMI_ROAM_FAIL_REASON_REASSOC_INTERNAL_DROP, /* Reassoc request is dropped internally */
     WMI_ROAM_FAIL_REASON_EAPOL_M2_SEND,     /* Unable to send EAPOL M2 frame */
     WMI_ROAM_FAIL_REASON_EAPOL_M2_INTERNAL_DROP,   /* EAPOL M2 frame dropped internally */
-    WMI_ROAM_FAIL_REASON_EAPOL_M2_NO_ACK,   /* No Ack is recieved for EAPOL M2 frame */
+    WMI_ROAM_FAIL_REASON_EAPOL_M2_NO_ACK,   /* No Ack is received for EAPOL M2 frame */
     WMI_ROAM_FAIL_REASON_EAPOL_M3_TIMEOUT,  /* M3 is not received */
     WMI_ROAM_FAIL_REASON_EAPOL_M4_SEND,     /* Unable to send EAPOL M4 frame */
     WMI_ROAM_FAIL_REASON_EAPOL_M4_INTERNAL_DROP,   /* EAPOL M4 frame dropped internally */
-    WMI_ROAM_FAIL_REASON_EAPOL_M4_NO_ACK,   /* No Ack is recieved for EAPOL M4 frame */
+    WMI_ROAM_FAIL_REASON_EAPOL_M4_NO_ACK,   /* No Ack is received for EAPOL M4 frame */
     WMI_ROAM_FAIL_REASON_NO_SCAN_FOR_FINAL_BMISS, /* Roam scan is not started for Final Bmiss case */
     WMI_ROAM_FAIL_REASON_DISCONNECT,        /* Deauth or Disassoc received from AP during roaming handoff */
     WMI_ROAM_FAIL_REASON_SYNC,              /* when host wakes-up during roaming in-progress, abort current roaming if previous sync is pending */
@@ -35547,7 +35547,7 @@ typedef struct {
     /* count of full scan */
     A_UINT32 roam_full_scan_count;
     A_INT32  rssi_th; /* unit: dBm */
-    A_UINT32 cu_th; /* channel utilization threhold: uses units of percent */
+    A_UINT32 cu_th; /* channel utilization threshold: uses units of percent */
     /* timer_canceled:
      * bit0: timer1 canceled
      * bit1: timer2 canceled
@@ -35633,7 +35633,7 @@ typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_capability_report_event_fixed_param */
     /*
      * This event is sent asynchronously during FW init.
-     * It indicates FW roam related capabilites to host.
+     * It indicates FW roam related capabilities to host.
      *
      * scoring_capability_bitmap = Indicates firmware candidate scoring
      *                             capabilities. It's a bitmap of values
@@ -36248,7 +36248,7 @@ typedef struct {
      * In the below fields, "OBSS level" refers to the power of the
      * signals received from "Other BSS".
      * Spatial reuse will only be permitted if the Other BSS's signal power
-     * is witin the min to max range specified by the below fields.
+     * is within the min to max range specified by the below fields.
      */
     /** Minimum OBSS level to use */
     A_INT32 obss_min; /* RSSI in dBm */
@@ -36260,7 +36260,7 @@ typedef struct {
 
 /*
  * Below structure is related to WMI CMD that configures the default
- * mimimum (OBSS_MIN) and maximum (OBSS_MAX) Other BSS levels (RSSI in dbm)
+ * minimum (OBSS_MIN) and maximum (OBSS_MAX) Other BSS levels (RSSI in dbm)
  * for VDEV of a give type (STA or AP). These thresholds are configured
  * within the Host and passed down to the FW. FW will use these
  * default OBSS_MIN and OBSS_MAX values during roaming if the assoc response
@@ -36275,7 +36275,7 @@ typedef struct {
      * In the below fields, "OBSS level" refers to the power of the
      * signals received from "Other BSS".
      * Spatial reuse will only be permitted if the Other BSS's signal power
-     * is witin the min to max range specified by the below fields.
+     * is within the min to max range specified by the below fields.
      */
     /** Minimum OBSS level to use */
     A_INT32 obss_min; /* RSSI in dBm */
@@ -36926,13 +36926,13 @@ typedef struct {
 /* 2nd DWORD of HE MAC Capabilities */
 
 /* BSRP A-MPDU Aggregation
- * maintaining compatability since we dont support this now so not wasting memory
+ * maintaining compatibility since we don't support this now so not wasting memory
  */
 #define WMI_HECAP_MAC_BSRPAMPDU_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 0, 1)
 #define WMI_HECAP_MAC_BSRPAMPDU_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 0, 1, value)
 
 /* Quiet Time Period (QTP) operation
- * maintaining compatability since we dont support this now so not wasting memory
+ * maintaining compatibility since we don't support this now so not wasting memory
  */
 #define WMI_HECAP_MAC_QTP_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 1, 1)
 #define WMI_HECAP_MAC_QTP_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 1, 1, value)
@@ -36940,7 +36940,7 @@ typedef struct {
 /* support by an AP for receiving an (A-)MPDU that contains a BQR in the
  * A-Control subfield and support by a non-AP STA for generating an (A-)MPDU
  * that contains a BQR in the A-Control subfield
- * maintaining compatability since we dont support this now so not wasting memory
+ * maintaining compatibility since we don't support this now so not wasting memory
  */
 #define WMI_HECAP_MAC_ABQR_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 2, 1)
 #define WMI_HECAP_MAC_ABQR_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 2, 1, value)
@@ -37737,7 +37737,7 @@ typedef struct {
        PPM = cfo_measurement(13 bits)/((2^13)/(800e-9)/2/Fc*1e6)
        PPM ranges from -40 to +40
 
-       Bits 0  : 0   Set to 1 to indicate cfo mesurement value is valid
+       Bits 0  : 0   Set to 1 to indicate cfo measurement value is valid
        Bits 1  : 14  14 bits cfo measurement raw data. 14 bit is signed bit.
                      For the above ppm equation , use the first 13 bits to calculate.
      */
@@ -38681,7 +38681,7 @@ typedef struct {
     A_UINT32 filter_group_bitmap;
     /* ul_mu_user_mask_lower:
      * Bitfields indicates which of the users in the current UL MU
-     * tranmission are enabled for CFR capture.
+     * transmission are enabled for CFR capture.
      * Bits 31 to 0 indicates user indexes for 32 users in a UL MU transmission.
      * If bit 0 is set, then the CFR capture will happen for user index 0
      * in the current UL MU Transmission.
@@ -38690,7 +38690,7 @@ typedef struct {
      */
     A_UINT32 ul_mu_user_mask_lower;
     /* ul_mu_user_mask_upper:
-     * This is contiuation of the above lower mask.
+     * This is continuation of the above lower mask.
      * Bits 4:0  Bitfields indicates user indices from 33 to 37 users.
      * Bits 31:5 Reserved for future use
      * If bit 0 is set, then CFR capture is enabled for user index 33
@@ -38744,7 +38744,7 @@ typedef struct {
 /* Following this structure is the TLV:
  *      A_UINT8 data[]; <-- length in byte given by field data_len.
  * This data array contains OEM data, the payload begins with a field to tell the HOST regarding the kind of the OEM data.
- *      A_UINT8 file_name[]; <-- Name of the file to which HOST needs to write this OEM specifc data.
+ *      A_UINT8 file_name[]; <-- Name of the file to which HOST needs to write this OEM specific data.
  */
 } wmi_oem_data_event_fixed_param;
 
@@ -38920,7 +38920,7 @@ typedef struct {
     /** TLV tag and len **/
     A_UINT32 tlv_header;
     A_UINT32 vdev_id; /* ID of the vdev this response belongs to */
-    /** identify which request this resposend to **/
+    /** identify which request this responds to **/
     A_UINT32 response_id;
     /* audio frame statistics part -
      * Use subsequent TLV arrays to list group_stats and peer_stats.
@@ -38952,7 +38952,7 @@ typedef struct {
     A_UINT32 tlv_header;
     /* Group mac_address */
     wmi_mac_addr group_addr;
-    /* Group indentify */
+    /* Group identity */
     A_UINT32 group_id;
     /* Multicast MSDU Data Packets received from Host for this Group */
     A_UINT32 mcast_tx;
@@ -39573,7 +39573,7 @@ typedef struct wmi_mlo_link_set_active_resp_event
 typedef struct {
     /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_setup_cmd_fixed_param; */
     A_UINT32 tlv_header;
-    /** Unique ID reprsenting the hw_links part of the MLD */
+    /** Unique ID representing the hw_links part of the MLD */
     A_UINT32 mld_group_id;
     /** pdev_id for identifying the MAC, See macros starting with WMI_PDEV_ID_ for values. */
     A_UINT32 pdev_id;
@@ -39855,7 +39855,7 @@ typedef struct {
      */
     A_UINT32 min_thruput_kbps;
     /* max_thruput_kbps:
-     * What upper limit on throughput shall be applied to MSDU queues beloning
+     * What upper limit on throughput shall be applied to MSDU queues belonging
      * to this service class, if other peer-TIDs are not meeting their QoS
      * service goals.
      * Units are kilobits per second.

From 079602f266418f459aa9115e7594fa068d32a2a6 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 26 Oct 2022 18:00:55 -0700
Subject: [PATCH 17/21] fw-api: CL 20086295 - update fw common interface files

add WMI_ROAM_PARAM_ROAM_HO_DELAY_RUNTIME_CONFIG def

Change-Id: Idea396b93f341276089f26cb2aba86e295feadc6
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 10 ++++++++++
 fw/wmi_version.h |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 1b269a572119..1ccef9f10b3b 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -35776,6 +35776,16 @@ typedef enum {
      */
     WMI_ROAM_PARAM_ROAM_SCAN_DFS_CONFIG_BITMAP = 3,
 
+    /*
+     * roam param to configure HO_DELAY_RX value at runtime
+     * The configured value of ho_delay_rx will be in milliseconds
+     * Maximum value which user can configure using this Param ID is 1000 msec.
+     *
+     * If any value beyond this Maximum value is provided by user, FW will
+     * configure the ho_delay_rx value to Maximum allowed value i.e. 1000 msec.
+     */
+    WMI_ROAM_PARAM_ROAM_HO_DELAY_RUNTIME_CONFIG = 4,
+
 
     /*=== END ROAM_PARAM_PROTOTYPE SECTION ===*/
 } WMI_ROAM_PARAM;
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 8d5e34213b8d..1c777508761d 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1223
+#define __WMI_REVISION_ 1224
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 842445f4ab9a51441d2ce9964ef15c74e8d9d413 Mon Sep 17 00:00:00 2001
From: Sajini R <quic_sajinir@quicinc.com>
Date: Wed, 19 Oct 2022 12:37:09 +0530
Subject: [PATCH 18/21] fw-api: Update ipq5332 target header files

Update ipq5332 target header files.

Change-Id: I376c5ca12118c10f91c38303f8b6880289aacf2a
---
 hw/qca5332/rx_msdu_link.h              |  37 +-
 hw/qca5332/rx_ppdu_end_user_stats.h    |  35 +-
 hw/qca5332/rx_reo_queue.h              |  36 +-
 hw/qca5332/rx_reo_queue_1k.h           |  36 +-
 hw/qca5332/rx_reo_queue_ext.h          |  36 +-
 hw/qca5332/uniform_descriptor_header.h |  42 ++-
 hw/qca5332/wcss_seq_hwioreg_umac.h     | 497 +++++++++++++++----------
 hw/qca5332/wcss_version.h              |   4 +-
 8 files changed, 453 insertions(+), 270 deletions(-)

diff --git a/hw/qca5332/rx_msdu_link.h b/hw/qca5332/rx_msdu_link.h
index 50b5ffef1612..f6e2161de29f 100644
--- a/hw/qca5332/rx_msdu_link.h
+++ b/hw/qca5332/rx_msdu_link.h
@@ -14,15 +14,6 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
- 
- 
- 
- 
- 
- 
- 
-
-
 #ifndef _RX_MSDU_LINK_H_
 #define _RX_MSDU_LINK_H_
 #if !defined(__ASSEMBLER__)
@@ -141,15 +132,39 @@ struct rx_msdu_link {
 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK                             0x000000f0
 
 
+/* Description		TX_MPDU_QUEUE_NUMBER
+
+			Consumer: TQM/Debug
+			Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere)
+			
+			Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor
+			
+			
+			Indicates the MPDU queue ID to which this MPDU descriptor
+			 belongs
+			Used for tracking and debugging
+			
+			Hamilton and Waikiki used bits [19:0] of word 1 of 'TX_MPDU_LINK,' 
+			word 16 of 'TX_MPDU_QUEUE_HEAD' and word 1 of 'TX_MPDU_QUEUE_EXT' 
+			for this.
+			 <legal all>
+*/
+
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET                  0x00000000
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB                     8
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB                     27
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK                    0x0fffff00
+
+
 /* Description		RESERVED_0A
 
 			<legal 0>
 */
 
 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET                           0x00000000
-#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_LSB                              8
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_LSB                              28
 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MSB                              31
-#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MASK                             0xffffff00
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MASK                             0xf0000000
 
 
 /* Description		NEXT_MSDU_LINK_DESC_ADDR_INFO
diff --git a/hw/qca5332/rx_ppdu_end_user_stats.h b/hw/qca5332/rx_ppdu_end_user_stats.h
index 3a67e786d8fb..651fd7c23514 100644
--- a/hw/qca5332/rx_ppdu_end_user_stats.h
+++ b/hw/qca5332/rx_ppdu_end_user_stats.h
@@ -14,14 +14,6 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
- 
- 
- 
- 
- 
- 
- 
-
 
 #ifndef _RX_PPDU_END_USER_STATS_H_
 #define _RX_PPDU_END_USER_STATS_H_
@@ -123,7 +115,7 @@ struct rx_ppdu_end_user_stats {
                       amsdu_msdu_count                                        : 16; // [31:16]
              uint32_t non_amsdu_msdu_count                                    : 16, // [15:0]
                       ucast_msdu_count                                        : 16; // [31:16]
-             uint32_t mcast_msdu_count                                        : 16, // [15:0]
+             uint32_t bcast_msdu_count                                        : 16, // [15:0]
                       mcast_bcast_msdu_count                                  : 16; // [31:16]
 #else
              struct   rx_rxpcu_classification_overview                          rxpcu_classification_details;
@@ -214,7 +206,7 @@ struct rx_ppdu_end_user_stats {
              uint32_t ucast_msdu_count                                        : 16, // [31:16]
                       non_amsdu_msdu_count                                    : 16; // [15:0]
              uint32_t mcast_bcast_msdu_count                                  : 16, // [31:16]
-                      mcast_msdu_count                                        : 16; // [15:0]
+                      bcast_msdu_count                                        : 16; // [15:0]
 #endif
 };
 
@@ -1801,9 +1793,8 @@ struct rx_ppdu_end_user_stats {
 			Field filled in by RX OLE
 			Set to 0 by RXPCU
 			
-			The number of MSDUs that are part of MPDUs without FCS error
-			
-			TODO: unicast AD1 or DA?
+			The number of MSDUs that are part of MPDUs without FCS error, 
+			that are directed to a unicast destination address
 			<legal all>
 */
 
@@ -1813,21 +1804,21 @@ struct rx_ppdu_end_user_stats {
 #define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MASK                                0x00000000ffff0000
 
 
-/* Description		MCAST_MSDU_COUNT
+/* Description		BCAST_MSDU_COUNT
 
 			Field filled in by RX OLE
 			Set to 0 by RXPCU
 			
-			The number of MSDUs that are part of MPDUs without FCS error
+			The number of MSDUs that are part of MPDUs without FCS error, 
+			whose destination addresses are broadcast (0xFFFF_FFFF_FFFF)
 			
-			TODO: multicast AD1 or DA?
 			<legal all>
 */
 
-#define RX_PPDU_END_USER_STATS_MCAST_MSDU_COUNT_OFFSET                              0x0000000000000070
-#define RX_PPDU_END_USER_STATS_MCAST_MSDU_COUNT_LSB                                 32
-#define RX_PPDU_END_USER_STATS_MCAST_MSDU_COUNT_MSB                                 47
-#define RX_PPDU_END_USER_STATS_MCAST_MSDU_COUNT_MASK                                0x0000ffff00000000
+#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_OFFSET                              0x0000000000000070
+#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_LSB                                 32
+#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MSB                                 47
+#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MASK                                0x0000ffff00000000
 
 
 /* Description		MCAST_BCAST_MSDU_COUNT
@@ -1835,9 +1826,9 @@ struct rx_ppdu_end_user_stats {
 			Field filled in by RX OLE
 			Set to 0 by RXPCU
 			
-			The number of MSDUs that are part of MPDUs without FCS error
+			The number of MSDUs that are part of MPDUs without FCS error, 
+			whose destination addresses are either multicast or broadcast
 			
-			TODO: multicast/broadcast AD1 or DA?
 			<legal all>
 */
 
diff --git a/hw/qca5332/rx_reo_queue.h b/hw/qca5332/rx_reo_queue.h
index db806ca89c86..08738fa000ad 100644
--- a/hw/qca5332/rx_reo_queue.h
+++ b/hw/qca5332/rx_reo_queue.h
@@ -14,14 +14,6 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
- 
- 
- 
- 
- 
- 
- 
-
 
 #ifndef _RX_REO_QUEUE_H_
 #define _RX_REO_QUEUE_H_
@@ -243,15 +235,39 @@ struct rx_reo_queue {
 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK                             0x000000f0
 
 
+/* Description		TX_MPDU_QUEUE_NUMBER
+
+			Consumer: TQM/Debug
+			Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere)
+			
+			Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor
+			
+			
+			Indicates the MPDU queue ID to which this MPDU descriptor
+			 belongs
+			Used for tracking and debugging
+			
+			Hamilton and Waikiki used bits [19:0] of word 1 of 'TX_MPDU_LINK,' 
+			word 16 of 'TX_MPDU_QUEUE_HEAD' and word 1 of 'TX_MPDU_QUEUE_EXT' 
+			for this.
+			 <legal all>
+*/
+
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET                  0x00000000
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB                     8
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB                     27
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK                    0x0fffff00
+
+
 /* Description		RESERVED_0A
 
 			<legal 0>
 */
 
 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET                           0x00000000
-#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_LSB                              8
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_LSB                              28
 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MSB                              31
-#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MASK                             0xffffff00
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MASK                             0xf0000000
 
 
 /* Description		RECEIVE_QUEUE_NUMBER
diff --git a/hw/qca5332/rx_reo_queue_1k.h b/hw/qca5332/rx_reo_queue_1k.h
index 0f4d5a53cfc9..6a8c9c9d8567 100644
--- a/hw/qca5332/rx_reo_queue_1k.h
+++ b/hw/qca5332/rx_reo_queue_1k.h
@@ -14,14 +14,6 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
- 
- 
- 
- 
- 
- 
- 
-
 
 #ifndef _RX_REO_QUEUE_1K_H_
 #define _RX_REO_QUEUE_1K_H_
@@ -173,15 +165,39 @@ struct rx_reo_queue_1k {
 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK                          0x000000f0
 
 
+/* Description		TX_MPDU_QUEUE_NUMBER
+
+			Consumer: TQM/Debug
+			Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere)
+			
+			Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor
+			
+			
+			Indicates the MPDU queue ID to which this MPDU descriptor
+			 belongs
+			Used for tracking and debugging
+			
+			Hamilton and Waikiki used bits [19:0] of word 1 of 'TX_MPDU_LINK,' 
+			word 16 of 'TX_MPDU_QUEUE_HEAD' and word 1 of 'TX_MPDU_QUEUE_EXT' 
+			for this.
+			 <legal all>
+*/
+
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET               0x00000000
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB                  8
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB                  27
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK                 0x0fffff00
+
+
 /* Description		RESERVED_0A
 
 			<legal 0>
 */
 
 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET                        0x00000000
-#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_LSB                           8
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_LSB                           28
 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MSB                           31
-#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MASK                          0xffffff00
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MASK                          0xf0000000
 
 
 /* Description		RX_BITMAP_319_288
diff --git a/hw/qca5332/rx_reo_queue_ext.h b/hw/qca5332/rx_reo_queue_ext.h
index 454d0e060947..d3e8f5e89fa2 100644
--- a/hw/qca5332/rx_reo_queue_ext.h
+++ b/hw/qca5332/rx_reo_queue_ext.h
@@ -14,14 +14,6 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
- 
- 
- 
- 
- 
- 
- 
-
 
 #ifndef _RX_REO_QUEUE_EXT_H_
 #define _RX_REO_QUEUE_EXT_H_
@@ -144,15 +136,39 @@ struct rx_reo_queue_ext {
 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK                         0x000000f0
 
 
+/* Description		TX_MPDU_QUEUE_NUMBER
+
+			Consumer: TQM/Debug
+			Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere)
+			
+			Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor
+			
+			
+			Indicates the MPDU queue ID to which this MPDU descriptor
+			 belongs
+			Used for tracking and debugging
+			
+			Hamilton and Waikiki used bits [19:0] of word 1 of 'TX_MPDU_LINK,' 
+			word 16 of 'TX_MPDU_QUEUE_HEAD' and word 1 of 'TX_MPDU_QUEUE_EXT' 
+			for this.
+			 <legal all>
+*/
+
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET              0x00000000
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB                 8
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB                 27
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK                0x0fffff00
+
+
 /* Description		RESERVED_0A
 
 			<legal 0>
 */
 
 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET                       0x00000000
-#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_LSB                          8
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_LSB                          28
 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MSB                          31
-#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MASK                         0xffffff00
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MASK                         0xf0000000
 
 
 /* Description		RESERVED_1A
diff --git a/hw/qca5332/uniform_descriptor_header.h b/hw/qca5332/uniform_descriptor_header.h
index ffe7562552d6..8fc2fac0bb9d 100644
--- a/hw/qca5332/uniform_descriptor_header.h
+++ b/hw/qca5332/uniform_descriptor_header.h
@@ -14,14 +14,6 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
- 
- 
- 
- 
- 
- 
- 
-
 
 #ifndef _UNIFORM_DESCRIPTOR_HEADER_H_
 #define _UNIFORM_DESCRIPTOR_HEADER_H_
@@ -35,9 +27,11 @@ struct uniform_descriptor_header {
 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
              uint32_t owner                                                   :  4, // [3:0]
                       buffer_type                                             :  4, // [7:4]
-                      reserved_0a                                             : 24; // [31:8]
+                      tx_mpdu_queue_number                                    : 20, // [27:8]
+                      reserved_0a                                             :  4; // [31:28]
 #else
-             uint32_t reserved_0a                                             : 24, // [31:8]
+             uint32_t reserved_0a                                             :  4, // [31:28]
+                      tx_mpdu_queue_number                                    : 20, // [27:8]
                       buffer_type                                             :  4, // [7:4]
                       owner                                                   :  4; // [3:0]
 #endif
@@ -106,15 +100,39 @@ struct uniform_descriptor_header {
 #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK                                  0x000000f0
 
 
+/* Description		TX_MPDU_QUEUE_NUMBER
+
+			Consumer: TQM/Debug
+			Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere)
+			
+			Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor
+			
+			
+			Indicates the MPDU queue ID to which this MPDU descriptor
+			 belongs
+			Used for tracking and debugging
+			
+			Hamilton and Waikiki used bits [19:0] of word 1 of 'TX_MPDU_LINK,' 
+			word 16 of 'TX_MPDU_QUEUE_HEAD' and word 1 of 'TX_MPDU_QUEUE_EXT' 
+			for this.
+			 <legal all>
+*/
+
+#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET                       0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB                          8
+#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB                          27
+#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK                         0x0fffff00
+
+
 /* Description		RESERVED_0A
 
 			<legal 0>
 */
 
 #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET                                0x00000000
-#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB                                   8
+#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB                                   28
 #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB                                   31
-#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK                                  0xffffff00
+#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK                                  0xf0000000
 
 
 
diff --git a/hw/qca5332/wcss_seq_hwioreg_umac.h b/hw/qca5332/wcss_seq_hwioreg_umac.h
index 354fd48679b7..5fab9210f020 100644
--- a/hw/qca5332/wcss_seq_hwioreg_umac.h
+++ b/hw/qca5332/wcss_seq_hwioreg_umac.h
@@ -16,7 +16,6 @@
 
 #ifndef __WCSS_SEQ_HWIOREG_UMAC_H__
 #define __WCSS_SEQ_HWIOREG_UMAC_H__
-
 #include "seq_hwio.h"
 #include "wcss_seq_hwiobase.h"
 #ifdef SCALE_INCLUDES
@@ -767,9 +766,49 @@
 #define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_REMAP_ADDR_BMSK                                                 0x1fffffff
 #define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_REMAP_ADDR_SHFT                                                          0
 
-#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_ADDR(x)                                                        ((x) + 0xa0)
-#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_PHYS(x)                                                        ((x) + 0xa0)
-#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_OFFS                                                           (0xa0)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x)                                                     ((x) + 0xa0)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_PHYS(x)                                                     ((x) + 0xa0)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OFFS                                                        (0xa0)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_RMSK                                                               0x7
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR                                                         0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR_RMSK                                                    0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ATTR                                                                     0x3
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUT(x, v)            \
+                out_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),v)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x))
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_BMSK                                            0x7
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_SHFT                                              0
+
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x)                                        ((x) + 0xa4)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_PHYS(x)                                        ((x) + 0xa4)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OFFS                                           (0xa4)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_RMSK                                            0x1ffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR                                            0x00001ffe
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR_RMSK                                       0xffffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ATTR                                                        0x3
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUT(x, v)            \
+                out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),v)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_BMSK                    0x1ffe000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_SHFT                           13
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_BMSK                       0x1ffe
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_SHFT                            1
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_BMSK                            0x1
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_SHFT                              0
+
+#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_ADDR(x)                                                        ((x) + 0xa8)
+#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_PHYS(x)                                                        ((x) + 0xa8)
+#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_OFFS                                                           (0xa8)
 #define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_RMSK                                                           0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_POR                                                            0x00000000
 #define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_POR_RMSK                                                       0xffffffff
@@ -785,9 +824,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_VAL_BMSK                                                       0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_VAL_SHFT                                                                0
 
-#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_ADDR(x)                                                 ((x) + 0xa4)
-#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_PHYS(x)                                                 ((x) + 0xa4)
-#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_OFFS                                                    (0xa4)
+#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_ADDR(x)                                                 ((x) + 0xac)
+#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_PHYS(x)                                                 ((x) + 0xac)
+#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_OFFS                                                    (0xac)
 #define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_RMSK                                                    0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_POR                                                     0x00000000
 #define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_POR_RMSK                                                0xffffffff
@@ -803,9 +842,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_BASE_ADDR_LSB_BMSK                                      0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_BASE_ADDR_LSB_SHFT                                               0
 
-#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_ADDR(x)                                                 ((x) + 0xa8)
-#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_PHYS(x)                                                 ((x) + 0xa8)
-#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_OFFS                                                    (0xa8)
+#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_ADDR(x)                                                 ((x) + 0xb0)
+#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_PHYS(x)                                                 ((x) + 0xb0)
+#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_OFFS                                                    (0xb0)
 #define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_RMSK                                                          0xff
 #define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_POR                                                     0x00000000
 #define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_POR_RMSK                                                0xffffffff
@@ -821,9 +860,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_BASE_ADDR_MSB_BMSK                                            0xff
 #define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_BASE_ADDR_MSB_SHFT                                               0
 
-#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_ADDR(x)                                                 ((x) + 0xac)
-#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_PHYS(x)                                                 ((x) + 0xac)
-#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_OFFS                                                    (0xac)
+#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_ADDR(x)                                                 ((x) + 0xb4)
+#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_PHYS(x)                                                 ((x) + 0xb4)
+#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_OFFS                                                    (0xb4)
 #define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_RMSK                                                    0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_POR                                                     0x00000000
 #define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_POR_RMSK                                                0xffffffff
@@ -839,9 +878,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_BASE_ADDR_MASK_LSB_BMSK                                 0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_BASE_ADDR_MASK_LSB_SHFT                                          0
 
-#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_ADDR(x)                                                 ((x) + 0xb0)
-#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_PHYS(x)                                                 ((x) + 0xb0)
-#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_OFFS                                                    (0xb0)
+#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_ADDR(x)                                                 ((x) + 0xb8)
+#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_PHYS(x)                                                 ((x) + 0xb8)
+#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_OFFS                                                    (0xb8)
 #define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_RMSK                                                    0xc00000ff
 #define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_POR                                                     0x00000010
 #define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_POR_RMSK                                                0xffffffff
@@ -861,9 +900,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_BASE_ADDR_MASK_MSB_BMSK                                       0xff
 #define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_BASE_ADDR_MASK_MSB_SHFT                                          0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_ADDR(x)                                                     ((x) + 0xb4)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_PHYS(x)                                                     ((x) + 0xb4)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_OFFS                                                        (0xb4)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_ADDR(x)                                                     ((x) + 0xbc)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_PHYS(x)                                                     ((x) + 0xbc)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_OFFS                                                        (0xbc)
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_RMSK                                                        0xffffffff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_POR                                                         0x00000000
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_POR_RMSK                                                    0xffffffff
@@ -875,9 +914,9 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_VALUE_BMSK                                                  0xffffffff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_VALUE_SHFT                                                           0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_ADDR(x)                                                     ((x) + 0xb8)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_PHYS(x)                                                     ((x) + 0xb8)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_OFFS                                                        (0xb8)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_ADDR(x)                                                     ((x) + 0xc0)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_PHYS(x)                                                     ((x) + 0xc0)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_OFFS                                                        (0xc0)
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_RMSK                                                              0xff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_POR                                                         0x00000000
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_POR_RMSK                                                    0xffffffff
@@ -889,9 +928,9 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_VALUE_BMSK                                                        0xff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_VALUE_SHFT                                                           0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_ADDR(x)                                                    ((x) + 0xbc)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_PHYS(x)                                                    ((x) + 0xbc)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_OFFS                                                       (0xbc)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_ADDR(x)                                                    ((x) + 0xc4)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_PHYS(x)                                                    ((x) + 0xc4)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_OFFS                                                       (0xc4)
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_RMSK                                                            0xfff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_POR                                                        0x00000211
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_POR_RMSK                                                   0xffffffff
@@ -907,9 +946,9 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK                                             0xf
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT                                               0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_ADDR(x)                                                 ((x) + 0xc0)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_PHYS(x)                                                 ((x) + 0xc0)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_OFFS                                                    (0xc0)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_ADDR(x)                                                 ((x) + 0xc8)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_PHYS(x)                                                 ((x) + 0xc8)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_OFFS                                                    (0xc8)
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_RMSK                                                           0x1
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_POR                                                     0x00000000
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_POR_RMSK                                                0xffffffff
@@ -925,9 +964,9 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK                                    0x1
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT                                      0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_ADDR(x)                                                ((x) + 0xc4)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_PHYS(x)                                                ((x) + 0xc4)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_OFFS                                                   (0xc4)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_ADDR(x)                                                ((x) + 0xcc)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_PHYS(x)                                                ((x) + 0xcc)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_OFFS                                                   (0xcc)
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RMSK                                                   0x80003fff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_POR                                                    0x00000000
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_POR_RMSK                                               0xffffffff
@@ -971,10 +1010,10 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_CORE_BMSK                                                     0x1
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_CORE_SHFT                                                       0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_ADDR(x)                                                      ((x) + 0xc8)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_PHYS(x)                                                      ((x) + 0xc8)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_OFFS                                                         (0xc8)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_RMSK                                                         0x81010101
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_ADDR(x)                                                      ((x) + 0xd0)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_PHYS(x)                                                      ((x) + 0xd0)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_OFFS                                                         (0xd0)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_RMSK                                                         0x81011f01
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_POR                                                          0x00000000
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_POR_RMSK                                                     0xffffffff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_ATTR                                                                      0x1
@@ -988,14 +1027,22 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT                                              24
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK                                         0x10000
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT                                              16
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_BMSK                                    0x1000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_SHFT                                        12
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_BMSK                                     0x800
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_SHFT                                        11
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_BMSK                                     0x400
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_SHFT                                        10
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_BMSK                                     0x200
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_SHFT                                         9
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_HW_ERR_INT_BMSK                                     0x100
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_HW_ERR_INT_SHFT                                         8
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_WARN_INT_BMSK                                         0x1
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_WARN_INT_SHFT                                           0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_ADDR(x)                                                     ((x) + 0xcc)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_PHYS(x)                                                     ((x) + 0xcc)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_OFFS                                                        (0xcc)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_ADDR(x)                                                     ((x) + 0xd4)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_PHYS(x)                                                     ((x) + 0xd4)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_OFFS                                                        (0xd4)
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_RMSK                                                          0xffffff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_POR                                                         0x00000000
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_POR_RMSK                                                    0xffffffff
@@ -1011,9 +1058,29 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK                                              0xff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT                                                 0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_ADDR(x)                                              ((x) + 0xd0)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_PHYS(x)                                              ((x) + 0xd0)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_OFFS                                                 (0xd0)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x)                                                ((x) + 0xd8)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_PHYS(x)                                                ((x) + 0xd8)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_OFFS                                                   (0xd8)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RMSK                                                   0xffffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR                                                    0x00000000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR_RMSK                                               0xffffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ATTR                                                                0x1
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_BMSK                                 0xff000000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_SHFT                                         24
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_BMSK                                   0xff0000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_SHFT                                         16
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_BMSK                                     0xff00
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_SHFT                                          8
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_BMSK                                       0xff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_SHFT                                          0
+
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_ADDR(x)                                              ((x) + 0xdc)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_PHYS(x)                                              ((x) + 0xdc)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_OFFS                                                 (0xdc)
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_RMSK                                                  0x1010101
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_POR                                                  0x00000000
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_POR_RMSK                                             0xffffffff
@@ -1031,9 +1098,9 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_GXI_PCIE_L0_RD_TIMEOUT_BMSK                                 0x1
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_GXI_PCIE_L0_RD_TIMEOUT_SHFT                                   0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_ADDR(x)                                             ((x) + 0xd4)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_PHYS(x)                                             ((x) + 0xd4)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_OFFS                                                (0xd4)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_ADDR(x)                                             ((x) + 0xe0)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_PHYS(x)                                             ((x) + 0xe0)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_OFFS                                                (0xe0)
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_RMSK                                                    0xffff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_POR                                                 0x00000000
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_POR_RMSK                                            0xffffffff
@@ -1047,9 +1114,9 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_AXI_RD_PCIE_L0_ACC_ERR_PORT_BMSK                          0xff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_AXI_RD_PCIE_L0_ACC_ERR_PORT_SHFT                             0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_ADDR(x)                                               ((x) + 0xd8)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_PHYS(x)                                               ((x) + 0xd8)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_OFFS                                                  (0xd8)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_ADDR(x)                                               ((x) + 0xe4)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_PHYS(x)                                               ((x) + 0xe4)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_OFFS                                                  (0xe4)
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_RMSK                                                  0xffff3f3f
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_POR                                                   0x00000000
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_POR_RMSK                                              0xffffffff
@@ -1071,9 +1138,9 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK                         0x3f
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT                            0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_ADDR(x)                                               ((x) + 0xdc)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_PHYS(x)                                               ((x) + 0xdc)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_OFFS                                                  (0xdc)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_ADDR(x)                                               ((x) + 0xe8)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_PHYS(x)                                               ((x) + 0xe8)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_OFFS                                                  (0xe8)
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_RMSK                                                  0xffff3f3f
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_POR                                                   0x00000000
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_POR_RMSK                                              0xffffffff
@@ -1095,9 +1162,9 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK                         0x3f
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT                            0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_ADDR(x)                                             ((x) + 0xe0)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_PHYS(x)                                             ((x) + 0xe0)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_OFFS                                                (0xe0)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_ADDR(x)                                             ((x) + 0xec)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_PHYS(x)                                             ((x) + 0xec)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_OFFS                                                (0xec)
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_RMSK                                                0xefffffff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_POR                                                 0x46000000
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_POR_RMSK                                            0xffffffff
@@ -1121,9 +1188,9 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_GXI_CLEAR_STATS_BMSK                                       0x1
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_GXI_CLEAR_STATS_SHFT                                         0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_ADDR(x)                                             ((x) + 0xe4)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_PHYS(x)                                             ((x) + 0xe4)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_OFFS                                                (0xe4)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_ADDR(x)                                             ((x) + 0xf0)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_PHYS(x)                                             ((x) + 0xf0)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_OFFS                                                (0xf0)
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_RMSK                                                0xc00007ff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_POR                                                 0x00000013
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_POR_RMSK                                            0xffffffff
@@ -1155,9 +1222,9 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_WRITE_BURST_SIZE_EXT_BMSK                              0x7
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_WRITE_BURST_SIZE_EXT_SHFT                                0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_ADDR(x)                                             ((x) + 0xe8)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_PHYS(x)                                             ((x) + 0xe8)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_OFFS                                                (0xe8)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_ADDR(x)                                             ((x) + 0xf4)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_PHYS(x)                                             ((x) + 0xf4)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_OFFS                                                (0xf4)
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_RMSK                                                0xffff0001
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_POR                                                 0x00ff0000
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_POR_RMSK                                            0xffffffff
@@ -1175,9 +1242,9 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_GXI_WDOG_WARN_DISABLE_BMSK                                 0x1
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_GXI_WDOG_WARN_DISABLE_SHFT                                   0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_ADDR(x)                                              ((x) + 0xec)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_PHYS(x)                                              ((x) + 0xec)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_OFFS                                                 (0xec)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_ADDR(x)                                              ((x) + 0xf8)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_PHYS(x)                                              ((x) + 0xf8)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_OFFS                                                 (0xf8)
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_RMSK                                                     0xffff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_POR                                                  0x00000000
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_POR_RMSK                                             0xffffffff
@@ -1189,9 +1256,9 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_GXI_WDOG_WARN_STATUS_BMSK                                0xffff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_GXI_WDOG_WARN_STATUS_SHFT                                     0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_ADDR(x)                                                 ((x) + 0xf0)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_PHYS(x)                                                 ((x) + 0xf0)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_OFFS                                                    (0xf0)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_ADDR(x)                                                 ((x) + 0xfc)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_PHYS(x)                                                 ((x) + 0xfc)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_OFFS                                                    (0xfc)
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_RMSK                                                    0xffffffff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_POR                                                     0x00000000
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_POR_RMSK                                                0xffffffff
@@ -1205,9 +1272,9 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK                                     0xffff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT                                          0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_ADDR(x)                                           ((x) + 0xf4)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_PHYS(x)                                           ((x) + 0xf4)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_OFFS                                              (0xf4)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_ADDR(x)                                           ((x) + 0x100)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_PHYS(x)                                           ((x) + 0x100)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_OFFS                                              (0x100)
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_RMSK                                              0xffff0001
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_POR                                               0x00ff0000
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_POR_RMSK                                          0xffffffff
@@ -1225,9 +1292,9 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_GXI_WDOG_HW_ERR_DISABLE_BMSK                             0x1
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_GXI_WDOG_HW_ERR_DISABLE_SHFT                               0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_ADDR(x)                                            ((x) + 0xf8)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_PHYS(x)                                            ((x) + 0xf8)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_OFFS                                               (0xf8)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_ADDR(x)                                            ((x) + 0x104)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_PHYS(x)                                            ((x) + 0x104)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_OFFS                                               (0x104)
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_RMSK                                                   0xffff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_POR                                                0x00000000
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_POR_RMSK                                           0xffffffff
@@ -1239,9 +1306,9 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_GXI_WDOG_HW_ERR_STATUS_BMSK                            0xffff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_GXI_WDOG_HW_ERR_STATUS_SHFT                                 0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_ADDR(x)                                               ((x) + 0xfc)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_PHYS(x)                                               ((x) + 0xfc)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_OFFS                                                  (0xfc)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_ADDR(x)                                               ((x) + 0x108)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_PHYS(x)                                               ((x) + 0x108)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_OFFS                                                  (0x108)
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_RMSK                                                     0xfffff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_POR                                                   0x00000000
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_POR_RMSK                                              0xffffffff
@@ -1261,9 +1328,9 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK                                      0xffff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT                                           0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_ADDR(x)                                               ((x) + 0x100)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_PHYS(x)                                               ((x) + 0x100)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_OFFS                                                  (0x100)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_ADDR(x)                                               ((x) + 0x10c)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_PHYS(x)                                               ((x) + 0x10c)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_OFFS                                                  (0x10c)
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_RMSK                                                     0xfffff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_POR                                                   0x00000000
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_POR_RMSK                                              0xffffffff
@@ -1283,9 +1350,9 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK                                      0xffff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT                                           0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x)                                     ((x) + 0x104)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x)                                     ((x) + 0x104)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OFFS                                        (0x104)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x)                                     ((x) + 0x110)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x)                                     ((x) + 0x110)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OFFS                                        (0x110)
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK                                        0xffffffff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_POR                                         0x00000000
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_POR_RMSK                                    0xffffffff
@@ -1301,9 +1368,9 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK                                  0xffffffff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT                                           0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x)                                     ((x) + 0x108)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x)                                     ((x) + 0x108)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OFFS                                        (0x108)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x)                                     ((x) + 0x114)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x)                                     ((x) + 0x114)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OFFS                                        (0x114)
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK                                        0xffffffff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_POR                                         0x00000000
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_POR_RMSK                                    0xffffffff
@@ -1319,9 +1386,9 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK                                  0xffffffff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT                                           0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x)                                     ((x) + 0x10c)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x)                                     ((x) + 0x10c)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OFFS                                        (0x10c)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x)                                     ((x) + 0x118)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x)                                     ((x) + 0x118)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OFFS                                        (0x118)
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK                                        0xffffffff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_POR                                         0x00000000
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_POR_RMSK                                    0xffffffff
@@ -1337,9 +1404,9 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK                                  0xffffffff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT                                           0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x)                                     ((x) + 0x110)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x)                                     ((x) + 0x110)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OFFS                                        (0x110)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x)                                     ((x) + 0x11c)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x)                                     ((x) + 0x11c)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OFFS                                        (0x11c)
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK                                        0xffffffff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_POR                                         0x00000000
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_POR_RMSK                                    0xffffffff
@@ -1355,9 +1422,9 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK                                  0xffffffff
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT                                           0
 
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x)                                            ((x) + 0x114)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_PHYS(x)                                            ((x) + 0x114)
-#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_OFFS                                               (0x114)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x)                                            ((x) + 0x120)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_PHYS(x)                                            ((x) + 0x120)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_OFFS                                               (0x120)
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_RMSK                                                   0xbfbf
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_POR                                                0x00000000
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_POR_RMSK                                           0xffffffff
@@ -1379,9 +1446,9 @@
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_BMSK                                          0x3f
 #define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_SHFT                                             0
 
-#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_ADDR(x)                                                       ((x) + 0x118)
-#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_PHYS(x)                                                       ((x) + 0x118)
-#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_OFFS                                                          (0x118)
+#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_ADDR(x)                                                       ((x) + 0x124)
+#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_PHYS(x)                                                       ((x) + 0x124)
+#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_OFFS                                                          (0x124)
 #define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_RMSK                                                              0xbfbf
 #define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_POR                                                           0x00000000
 #define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_POR_RMSK                                                      0xffffffff
@@ -1403,9 +1470,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_RD_CMD_FIFO_ADDR_BMSK                                               0x3f
 #define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_RD_CMD_FIFO_ADDR_SHFT                                                  0
 
-#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_ADDR(x)                                                       ((x) + 0x11c)
-#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_PHYS(x)                                                       ((x) + 0x11c)
-#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_OFFS                                                          (0x11c)
+#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_ADDR(x)                                                       ((x) + 0x128)
+#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_PHYS(x)                                                       ((x) + 0x128)
+#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_OFFS                                                          (0x128)
 #define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_RMSK                                                          0x3f3f3f3f
 #define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_POR                                                           0x00000000
 #define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_POR_RMSK                                                      0xffffffff
@@ -1423,9 +1490,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_RD_CMD_FIFO_RD_PTR_BMSK                                             0x3f
 #define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_RD_CMD_FIFO_RD_PTR_SHFT                                                0
 
-#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_ADDR(x)                                                      ((x) + 0x120)
-#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_PHYS(x)                                                      ((x) + 0x120)
-#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_OFFS                                                         (0x120)
+#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_ADDR(x)                                                      ((x) + 0x12c)
+#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_PHYS(x)                                                      ((x) + 0x12c)
+#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_OFFS                                                         (0x12c)
 #define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_RMSK                                                         0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_POR                                                          0x00000000
 #define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_POR_RMSK                                                     0xffffffff
@@ -1437,9 +1504,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_VALUE_BMSK                                                   0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_VALUE_SHFT                                                            0
 
-#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_ADDR(x)                                                      ((x) + 0x124)
-#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_PHYS(x)                                                      ((x) + 0x124)
-#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_OFFS                                                         (0x124)
+#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_ADDR(x)                                                      ((x) + 0x130)
+#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_PHYS(x)                                                      ((x) + 0x130)
+#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_OFFS                                                         (0x130)
 #define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_RMSK                                                         0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_POR                                                          0x00000000
 #define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_POR_RMSK                                                     0xffffffff
@@ -1451,9 +1518,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_VALUE_BMSK                                                   0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_VALUE_SHFT                                                            0
 
-#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_ADDR(x)                                                      ((x) + 0x128)
-#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_PHYS(x)                                                      ((x) + 0x128)
-#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_OFFS                                                         (0x128)
+#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_ADDR(x)                                                      ((x) + 0x134)
+#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_PHYS(x)                                                      ((x) + 0x134)
+#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_OFFS                                                         (0x134)
 #define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_RMSK                                                         0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_POR                                                          0x00000000
 #define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_POR_RMSK                                                     0xffffffff
@@ -1465,9 +1532,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_VALUE_BMSK                                                   0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_VALUE_SHFT                                                            0
 
-#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_ADDR(x)                                                      ((x) + 0x12c)
-#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_PHYS(x)                                                      ((x) + 0x12c)
-#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_OFFS                                                         (0x12c)
+#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_ADDR(x)                                                      ((x) + 0x138)
+#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_PHYS(x)                                                      ((x) + 0x138)
+#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_OFFS                                                         (0x138)
 #define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_RMSK                                                         0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_POR                                                          0x00000000
 #define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_POR_RMSK                                                     0xffffffff
@@ -1479,9 +1546,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_VALUE_BMSK                                                   0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_VALUE_SHFT                                                            0
 
-#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_LSB_ADDR(x)                                                       ((x) + 0x130)
-#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_LSB_PHYS(x)                                                       ((x) + 0x130)
-#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_LSB_OFFS                                                          (0x130)
+#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_LSB_ADDR(x)                                                       ((x) + 0x13c)
+#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_LSB_PHYS(x)                                                       ((x) + 0x13c)
+#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_LSB_OFFS                                                          (0x13c)
 #define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_LSB_RMSK                                                          0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_LSB_POR                                                           0xff000000
 #define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_LSB_POR_RMSK                                                      0xffffffff
@@ -1497,9 +1564,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_LSB_REG_SS_ADDR_MASK_LSB_BMSK                                     0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_LSB_REG_SS_ADDR_MASK_LSB_SHFT                                              0
 
-#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_MSB_ADDR(x)                                                       ((x) + 0x134)
-#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_MSB_PHYS(x)                                                       ((x) + 0x134)
-#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_MSB_OFFS                                                          (0x134)
+#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_MSB_ADDR(x)                                                       ((x) + 0x140)
+#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_MSB_PHYS(x)                                                       ((x) + 0x140)
+#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_MSB_OFFS                                                          (0x140)
 #define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_MSB_RMSK                                                                0xff
 #define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_MSB_POR                                                           0x0000007f
 #define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_MSB_POR_RMSK                                                      0xffffffff
@@ -1515,9 +1582,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_MSB_REG_SS_ADDR_MASK_MSB_BMSK                                           0xff
 #define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_MSB_REG_SS_ADDR_MASK_MSB_SHFT                                              0
 
-#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_ADDR(x)                                                   ((x) + 0x138)
-#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_PHYS(x)                                                   ((x) + 0x138)
-#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_OFFS                                                      (0x138)
+#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_ADDR(x)                                                   ((x) + 0x144)
+#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_PHYS(x)                                                   ((x) + 0x144)
+#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_OFFS                                                      (0x144)
 #define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_RMSK                                                      0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_POR                                                       0x00000000
 #define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_POR_RMSK                                                  0xffffffff
@@ -1533,9 +1600,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_REG_INT_ADDR_MASK_LSB_BMSK                                0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_REG_INT_ADDR_MASK_LSB_SHFT                                         0
 
-#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_ADDR(x)                                                   ((x) + 0x13c)
-#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_PHYS(x)                                                   ((x) + 0x13c)
-#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_OFFS                                                      (0x13c)
+#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_ADDR(x)                                                   ((x) + 0x148)
+#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_PHYS(x)                                                   ((x) + 0x148)
+#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_OFFS                                                      (0x148)
 #define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_RMSK                                                            0xff
 #define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_POR                                                       0x00000010
 #define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_POR_RMSK                                                  0xffffffff
@@ -1551,9 +1618,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_REG_INT_ADDR_MASK_MSB_BMSK                                      0xff
 #define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_REG_INT_ADDR_MASK_MSB_SHFT                                         0
 
-#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_ADDR(x)                                                      ((x) + 0x140)
-#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_PHYS(x)                                                      ((x) + 0x140)
-#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_OFFS                                                         (0x140)
+#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_ADDR(x)                                                      ((x) + 0x14c)
+#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_PHYS(x)                                                      ((x) + 0x14c)
+#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_OFFS                                                         (0x14c)
 #define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_RMSK                                                         0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_POR                                                          0x00b80000
 #define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_POR_RMSK                                                     0xffffffff
@@ -1569,9 +1636,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_REG_SS_ADDR_RANGE_LSB_BMSK                                   0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_REG_SS_ADDR_RANGE_LSB_SHFT                                            0
 
-#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_ADDR(x)                                                      ((x) + 0x144)
-#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_PHYS(x)                                                      ((x) + 0x144)
-#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_OFFS                                                         (0x144)
+#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_ADDR(x)                                                      ((x) + 0x150)
+#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_PHYS(x)                                                      ((x) + 0x150)
+#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_OFFS                                                         (0x150)
 #define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_RMSK                                                               0xff
 #define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_POR                                                          0x00000010
 #define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_POR_RMSK                                                     0xffffffff
@@ -1587,9 +1654,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_REG_SS_ADDR_RANGE_MSB_BMSK                                         0xff
 #define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_REG_SS_ADDR_RANGE_MSB_SHFT                                            0
 
-#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR(x)                                                         ((x) + 0x148)
-#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_PHYS(x)                                                         ((x) + 0x148)
-#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_OFFS                                                            (0x148)
+#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR(x)                                                         ((x) + 0x154)
+#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_PHYS(x)                                                         ((x) + 0x154)
+#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_OFFS                                                            (0x154)
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_RMSK                                                            0xff13ff13
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_POR                                                             0x00000000
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_POR_RMSK                                                        0xffffffff
@@ -1619,9 +1686,9 @@
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR_INJ_ENABLE_BMSK                                                   0x1
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR_INJ_ENABLE_SHFT                                                     0
 
-#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR(x)                                                         ((x) + 0x14c)
-#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_PHYS(x)                                                         ((x) + 0x14c)
-#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_OFFS                                                            (0x14c)
+#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR(x)                                                         ((x) + 0x158)
+#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_PHYS(x)                                                         ((x) + 0x158)
+#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_OFFS                                                            (0x158)
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_RMSK                                                            0xff07ff07
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_POR                                                             0x00000000
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_POR_RMSK                                                        0xffffffff
@@ -1651,9 +1718,9 @@
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR_INJ_ENABLE_BMSK                                                   0x1
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR_INJ_ENABLE_SHFT                                                     0
 
-#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_ADDR(x)                                                   ((x) + 0x150)
-#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_PHYS(x)                                                   ((x) + 0x150)
-#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_OFFS                                                      (0x150)
+#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_ADDR(x)                                                   ((x) + 0x15c)
+#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_PHYS(x)                                                   ((x) + 0x15c)
+#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_OFFS                                                      (0x15c)
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_RMSK                                                      0xffffffff
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_POR                                                       0x00000000
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_POR_RMSK                                                  0xffffffff
@@ -1669,9 +1736,9 @@
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_ERR_ADDR_LSB_BMSK                                         0xffffffff
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_ERR_ADDR_LSB_SHFT                                                  0
 
-#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_ADDR(x)                                                   ((x) + 0x154)
-#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_PHYS(x)                                                   ((x) + 0x154)
-#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_OFFS                                                      (0x154)
+#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_ADDR(x)                                                   ((x) + 0x160)
+#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_PHYS(x)                                                   ((x) + 0x160)
+#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_OFFS                                                      (0x160)
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_RMSK                                                            0xff
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_POR                                                       0x00000000
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_POR_RMSK                                                  0xffffffff
@@ -1687,9 +1754,9 @@
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_ERR_ADDR_MSB_BMSK                                               0xff
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_ERR_ADDR_MSB_SHFT                                                  0
 
-#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_ADDR(x)                                                   ((x) + 0x158)
-#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_PHYS(x)                                                   ((x) + 0x158)
-#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_OFFS                                                      (0x158)
+#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_ADDR(x)                                                   ((x) + 0x164)
+#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_PHYS(x)                                                   ((x) + 0x164)
+#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_OFFS                                                      (0x164)
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_RMSK                                                      0xffffffff
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_POR                                                       0x00000000
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_POR_RMSK                                                  0xffffffff
@@ -1705,9 +1772,9 @@
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_ERR_DATA_LSB_BMSK                                         0xffffffff
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_ERR_DATA_LSB_SHFT                                                  0
 
-#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_ADDR(x)                                                   ((x) + 0x15c)
-#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_PHYS(x)                                                   ((x) + 0x15c)
-#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_OFFS                                                      (0x15c)
+#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_ADDR(x)                                                   ((x) + 0x168)
+#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_PHYS(x)                                                   ((x) + 0x168)
+#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_OFFS                                                      (0x168)
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_RMSK                                                      0xffffffff
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_POR                                                       0x00000000
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_POR_RMSK                                                  0xffffffff
@@ -1723,9 +1790,9 @@
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_ERR_DATA_MSB_BMSK                                         0xffffffff
 #define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_ERR_DATA_MSB_SHFT                                                  0
 
-#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_ADDR(x)                                                   ((x) + 0x160)
-#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_PHYS(x)                                                   ((x) + 0x160)
-#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_OFFS                                                      (0x160)
+#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_ADDR(x)                                                   ((x) + 0x16c)
+#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_PHYS(x)                                                   ((x) + 0x16c)
+#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_OFFS                                                      (0x16c)
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_RMSK                                                      0xffffffff
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_POR                                                       0x00000000
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_POR_RMSK                                                  0xffffffff
@@ -1741,9 +1808,9 @@
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_ERR_ADDR_LSB_BMSK                                         0xffffffff
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_ERR_ADDR_LSB_SHFT                                                  0
 
-#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_ADDR(x)                                                   ((x) + 0x164)
-#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_PHYS(x)                                                   ((x) + 0x164)
-#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_OFFS                                                      (0x164)
+#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_ADDR(x)                                                   ((x) + 0x170)
+#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_PHYS(x)                                                   ((x) + 0x170)
+#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_OFFS                                                      (0x170)
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_RMSK                                                            0xff
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_POR                                                       0x00000000
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_POR_RMSK                                                  0xffffffff
@@ -1759,9 +1826,9 @@
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_ERR_ADDR_MSB_BMSK                                               0xff
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_ERR_ADDR_MSB_SHFT                                                  0
 
-#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_ADDR(x)                                                   ((x) + 0x168)
-#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_PHYS(x)                                                   ((x) + 0x168)
-#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_OFFS                                                      (0x168)
+#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_ADDR(x)                                                   ((x) + 0x174)
+#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_PHYS(x)                                                   ((x) + 0x174)
+#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_OFFS                                                      (0x174)
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_RMSK                                                      0xffffffff
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_POR                                                       0x00000000
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_POR_RMSK                                                  0xffffffff
@@ -1777,9 +1844,9 @@
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_ERR_DATA_LSB_BMSK                                         0xffffffff
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_ERR_DATA_LSB_SHFT                                                  0
 
-#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_ADDR(x)                                                   ((x) + 0x16c)
-#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_PHYS(x)                                                   ((x) + 0x16c)
-#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_OFFS                                                      (0x16c)
+#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_ADDR(x)                                                   ((x) + 0x178)
+#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_PHYS(x)                                                   ((x) + 0x178)
+#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_OFFS                                                      (0x178)
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_RMSK                                                      0xffffffff
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_POR                                                       0x00000000
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_POR_RMSK                                                  0xffffffff
@@ -1795,9 +1862,9 @@
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_ERR_DATA_MSB_BMSK                                         0xffffffff
 #define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_ERR_DATA_MSB_SHFT                                                  0
 
-#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ADDR(x)                                              ((x) + 0x170)
-#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_PHYS(x)                                              ((x) + 0x170)
-#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_OFFS                                                 (0x170)
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ADDR(x)                                              ((x) + 0x17c)
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_PHYS(x)                                              ((x) + 0x17c)
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_OFFS                                                 (0x17c)
 #define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_RMSK                                                 0x3fffffff
 #define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_POR                                                  0x08000000
 #define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_POR_RMSK                                             0xffffffff
@@ -1823,9 +1890,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_BMSK                                        0x1ffffff
 #define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_SHFT                                                0
 
-#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_ADDR(x)                               ((x) + 0x174)
-#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_PHYS(x)                               ((x) + 0x174)
-#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_OFFS                                  (0x174)
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_ADDR(x)                               ((x) + 0x180)
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_PHYS(x)                               ((x) + 0x180)
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_OFFS                                  (0x180)
 #define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_RMSK                                  0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_POR                                   0x00000000
 #define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_POR_RMSK                              0xffffffff
@@ -1841,9 +1908,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_ID_BITMAP_BMSK                        0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_ID_BITMAP_SHFT                                 0
 
-#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_ADDR(x)                               ((x) + 0x178)
-#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_PHYS(x)                               ((x) + 0x178)
-#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_OFFS                                  (0x178)
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_ADDR(x)                               ((x) + 0x184)
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_PHYS(x)                               ((x) + 0x184)
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_OFFS                                  (0x184)
 #define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_RMSK                                  0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_POR                                   0x00000000
 #define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_POR_RMSK                              0xffffffff
@@ -1859,9 +1926,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_ID_BITMAP_BMSK                        0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_ID_BITMAP_SHFT                                 0
 
-#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_ADDR(x)                                            ((x) + 0x17c)
-#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_PHYS(x)                                            ((x) + 0x17c)
-#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_OFFS                                               (0x17c)
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_ADDR(x)                                            ((x) + 0x188)
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_PHYS(x)                                            ((x) + 0x188)
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_OFFS                                               (0x188)
 #define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_RMSK                                                      0xf
 #define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_POR                                                0x00000000
 #define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_POR_RMSK                                           0xffffffff
@@ -1877,9 +1944,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_AXI_ERROR_STATUS_BMSK                                     0x1
 #define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_AXI_ERROR_STATUS_SHFT                                       0
 
-#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_ADDR(base,n)                                       ((base) + 0X180 + (0x4*(n)))
-#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_PHYS(base,n)                                       ((base) + 0X180 + (0x4*(n)))
-#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_OFFS(n)                                            (0X180 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_ADDR(base,n)                                       ((base) + 0X18C + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_PHYS(base,n)                                       ((base) + 0X18C + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_OFFS(n)                                            (0X18C + (0x4*(n)))
 #define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_RMSK                                               0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_MAXn                                                        3
 #define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_POR                                                0x00000000
@@ -1892,9 +1959,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_ADDR_LOW_BMSK                                      0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_ADDR_LOW_SHFT                                               0
 
-#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_ADDR(base,n)                                       ((base) + 0X190 + (0x4*(n)))
-#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_PHYS(base,n)                                       ((base) + 0X190 + (0x4*(n)))
-#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_OFFS(n)                                            (0X190 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_ADDR(base,n)                                       ((base) + 0X19C + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_PHYS(base,n)                                       ((base) + 0X19C + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_OFFS(n)                                            (0X19C + (0x4*(n)))
 #define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_RMSK                                               0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_MAXn                                                        3
 #define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_POR                                                0x00000000
@@ -1919,9 +1986,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_ADDR_HIGH_BMSK                                           0xff
 #define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_ADDR_HIGH_SHFT                                              0
 
-#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_ADDR(x)                                                 ((x) + 0x1a0)
-#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_PHYS(x)                                                 ((x) + 0x1a0)
-#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_OFFS                                                    (0x1a0)
+#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_ADDR(x)                                                 ((x) + 0x1ac)
+#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_PHYS(x)                                                 ((x) + 0x1ac)
+#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_OFFS                                                    (0x1ac)
 #define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_RMSK                                                    0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_POR                                                     0x00000000
 #define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_POR_RMSK                                                0xffffffff
@@ -1933,9 +2000,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_TIMESTAMP_BMSK                                          0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_TIMESTAMP_SHFT                                                   0
 
-#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_ADDR(x)                                                 ((x) + 0x1a4)
-#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_PHYS(x)                                                 ((x) + 0x1a4)
-#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_OFFS                                                    (0x1a4)
+#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_ADDR(x)                                                 ((x) + 0x1b0)
+#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_PHYS(x)                                                 ((x) + 0x1b0)
+#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_OFFS                                                    (0x1b0)
 #define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_RMSK                                                    0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_POR                                                     0x00000000
 #define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_POR_RMSK                                                0xffffffff
@@ -1947,9 +2014,9 @@
 #define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_TIMESTAMP_BMSK                                          0xffffffff
 #define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_TIMESTAMP_SHFT                                                   0
 
-#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_ADDR(x)                                                  ((x) + 0x1a8)
-#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_PHYS(x)                                                  ((x) + 0x1a8)
-#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_OFFS                                                     (0x1a8)
+#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_ADDR(x)                                                  ((x) + 0x1b4)
+#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_PHYS(x)                                                  ((x) + 0x1b4)
+#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_OFFS                                                     (0x1b4)
 #define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_RMSK                                                          0xfff
 #define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_POR                                                      0x00000049
 #define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_POR_RMSK                                                 0xffffffff
@@ -1979,9 +2046,9 @@
 #define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_TCL_SEC_BIT_OVERRIDE_EN_BMSK                                    0x1
 #define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_TCL_SEC_BIT_OVERRIDE_EN_SHFT                                      0
 
-#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_ADDR(x)                                                        ((x) + 0x1ac)
-#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_PHYS(x)                                                        ((x) + 0x1ac)
-#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_OFFS                                                           (0x1ac)
+#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_ADDR(x)                                                        ((x) + 0x1b8)
+#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_PHYS(x)                                                        ((x) + 0x1b8)
+#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_OFFS                                                           (0x1b8)
 #define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_RMSK                                                            0x1ff01ff
 #define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_POR                                                            0x00000000
 #define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_POR_RMSK                                                       0xffffffff
@@ -15747,7 +15814,7 @@
 #define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_PHYS(x)                                                       ((x) + 0x18)
 #define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OFFS                                                          (0x18)
 #define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_RMSK                                                          0xffffffff
-#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR                                                           0x6666ba98
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR                                                           0x66666668
 #define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR_RMSK                                                      0xffffffff
 #define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ATTR                                                                       0x3
 #define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x)            \
@@ -35084,7 +35151,7 @@
 #define HWIO_UMCMN_R0_ISR_S16_ADDR(x)                                                           ((x) + 0x74)
 #define HWIO_UMCMN_R0_ISR_S16_PHYS(x)                                                           ((x) + 0x74)
 #define HWIO_UMCMN_R0_ISR_S16_OFFS                                                              (0x74)
-#define HWIO_UMCMN_R0_ISR_S16_RMSK                                                                    0x1f
+#define HWIO_UMCMN_R0_ISR_S16_RMSK                                                                   0x1ff
 #define HWIO_UMCMN_R0_ISR_S16_POR                                                               0x00000000
 #define HWIO_UMCMN_R0_ISR_S16_POR_RMSK                                                          0xffffffff
 #define HWIO_UMCMN_R0_ISR_S16_ATTR                                                                           0x0
@@ -35096,6 +35163,14 @@
                 out_dword(HWIO_UMCMN_R0_ISR_S16_ADDR(x),v)
 #define HWIO_UMCMN_R0_ISR_S16_OUTM(x,m,v) \
                 out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S16_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S16_IN(x))
+#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK                                              0x100
+#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT                                                  8
+#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK                                               0x80
+#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT                                                  7
+#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK                                               0x40
+#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT                                                  6
+#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK                                               0x20
+#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT                                                  5
 #define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_WDTO_ERR_BMSK                                                   0x10
 #define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_WDTO_ERR_SHFT                                                      4
 #define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_AXI_WR_ERR_BMSK                                                  0x8
@@ -36054,7 +36129,7 @@
 #define HWIO_UMCMN_R0_IMR_S16_ADDR(x)                                                           ((x) + 0xbc)
 #define HWIO_UMCMN_R0_IMR_S16_PHYS(x)                                                           ((x) + 0xbc)
 #define HWIO_UMCMN_R0_IMR_S16_OFFS                                                              (0xbc)
-#define HWIO_UMCMN_R0_IMR_S16_RMSK                                                                    0x1f
+#define HWIO_UMCMN_R0_IMR_S16_RMSK                                                                   0x1ff
 #define HWIO_UMCMN_R0_IMR_S16_POR                                                               0x00000000
 #define HWIO_UMCMN_R0_IMR_S16_POR_RMSK                                                          0xffffffff
 #define HWIO_UMCMN_R0_IMR_S16_ATTR                                                                           0x3
@@ -36066,6 +36141,14 @@
                 out_dword(HWIO_UMCMN_R0_IMR_S16_ADDR(x),v)
 #define HWIO_UMCMN_R0_IMR_S16_OUTM(x,m,v) \
                 out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S16_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S16_IN(x))
+#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK                                              0x100
+#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT                                                  8
+#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK                                               0x80
+#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT                                                  7
+#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK                                               0x40
+#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT                                                  6
+#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK                                               0x20
+#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT                                                  5
 #define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_WDTO_ERR_BMSK                                                   0x10
 #define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_WDTO_ERR_SHFT                                                      4
 #define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_AXI_WR_ERR_BMSK                                                  0x8
@@ -36820,8 +36903,36 @@
 #define HWIO_UMCMN_R0_TRC_CTRL_2_UMAC_MISC_TRC_EVENT_SEL_SHFT                                           19
 #define HWIO_UMCMN_R0_TRC_CTRL_2_TRC_BUS_MUX_SEL_BMSK                                              0x78000
 #define HWIO_UMCMN_R0_TRC_CTRL_2_TRC_BUS_MUX_SEL_SHFT                                                   15
-#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_BIT_2_BMSK                                          0x7fff
-#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_BIT_2_SHFT                                               0
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_BMSK                                           0x4000
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_SHFT                                               14
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_BMSK                                       0x2000
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_SHFT                                           13
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_BMSK                                           0x1000
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_SHFT                                               12
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_BMSK                                            0x800
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_SHFT                                               11
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_BMSK                                            0x400
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_SHFT                                               10
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_BMSK                                            0x200
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_SHFT                                                9
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_BMSK                                            0x100
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_SHFT                                                8
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_BMSK                                              0x80
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_SHFT                                                 7
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_BMSK                                              0x40
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_SHFT                                                 6
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_BMSK                                              0x20
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_SHFT                                                 5
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_BMSK                                              0x10
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_SHFT                                                 4
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_BMSK                                                0x8
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_SHFT                                                  3
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_BMSK                                               0x4
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_SHFT                                                 2
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_BMSK                                                0x2
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_SHFT                                                  1
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_BMSK                                               0x1
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_SHFT                                                 0
 
 #define HWIO_UMCMN_R0_EVENTMASK_IX0_ADDR(x)                                                     ((x) + 0x17c)
 #define HWIO_UMCMN_R0_EVENTMASK_IX0_PHYS(x)                                                     ((x) + 0x17c)
diff --git a/hw/qca5332/wcss_version.h b/hw/qca5332/wcss_version.h
index 2d67d4ee15a6..799d4a4630dd 100644
--- a/hw/qca5332/wcss_version.h
+++ b/hw/qca5332/wcss_version.h
@@ -13,5 +13,5 @@
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
- 
-#define WCSS_VERSION 2327
+
+#define WCSS_VERSION 2357

From f172403eb2ed638be1db4f60854a2c655f287b0e Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 27 Oct 2022 12:00:55 -0700
Subject: [PATCH 19/21] fw-api: CL 20099899 - update fw common interface files

HTT stats: add fields to ast_entry TLV

Change-Id: Icf2dfce41b9704a3e8affe4d36d635ea3e725c81
CRs-Fixed: 2262693
---
 fw/htt_stats.h | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 1c237bede021..2139678f69a8 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -1602,7 +1602,11 @@ typedef struct {
         intra_bss      : 1,
         chip_id        : 2,
         ml_peer_id     : 13,
-        reserved       : 1;
+        on_chip        : 1;
+    A_UINT32
+        tx_monitor_override_sta : 1,
+        rx_monitor_override_sta : 1,
+        reserved1               : 30;
 } htt_ast_entry_tlv;
 
 typedef enum {

From c1b7a12847c402ab7b15886dcec68c730c695ea7 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 28 Oct 2022 06:01:00 -0700
Subject: [PATCH 20/21] fw-api: CL 20102421 - update fw common interface files

Change-Id: I19b148dc94108b62c5925606c7d7c8eab55dfc51
HTT: add RXPCU filter enable flag in RX_RING_SELECTION_CFG msg
CRs-Fixed: 2262693
---
 fw/htt.h | 86 ++++++++++++++++++++++++++++++++++++--------------------
 1 file changed, 56 insertions(+), 30 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index f94aad50ab84..ab46e7499a52 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -235,9 +235,10 @@
  * 3.108 Add HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP def.
  * 3.109 Add HTT_T2H RX_ADDBA_EXTN,RX_DELBA_EXTN defs.
  * 3.110 Add more word_mask fields in htt_tx_monitor_cfg_t.
+ * 3.111 Add RXPCU filter enable flag in RX_RING_SELECTION_CFG msg.
  */
 #define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 110
+#define HTT_CURRENT_VERSION_MINOR 111
 
 #define HTT_NUM_TX_FRAG_DESC  1024
 
@@ -5535,38 +5536,43 @@ enum htt_srng_ring_id {
  *
  *    The message would appear as follows:
  *
- *    |31 28|27|26|25|24|23            16|15  | 11| 10|9 8|7             0|
- *    |-----+--+--+--+--+----------------+----+---+---+---+---------------|
- *    |rsvd1|DT|OV|PS|SS|     ring_id    |     pdev_id    |    msg_type   |
- *    |-------------------------------------------------------------------|
- *    |              rsvd2               |           ring_buffer_size     |
- *    |-------------------------------------------------------------------|
- *    |                        packet_type_enable_flags_0                 |
- *    |-------------------------------------------------------------------|
- *    |                        packet_type_enable_flags_1                 |
- *    |-------------------------------------------------------------------|
- *    |                        packet_type_enable_flags_2                 |
- *    |-------------------------------------------------------------------|
- *    |                        packet_type_enable_flags_3                 |
- *    |-------------------------------------------------------------------|
- *    |                         tlv_filter_in_flags                       |
- *    |-------------------------------------------------------------------|
- *    |         rx_header_offset         |       rx_packet_offset         |
- *    |-------------------------------------------------------------------|
- *    |       rx_mpdu_start_offset       |      rx_mpdu_end_offset        |
- *    |-------------------------------------------------------------------|
- *    |       rx_msdu_start_offset       |      rx_msdu_end_offset        |
- *    |-------------------------------------------------------------------|
- *    |              rsvd3               |      rx_attention_offset       |
- *    |-------------------------------------------------------------------|
- *    |              rsvd4                    | mo| fp| rx_drop_threshold |
- *    |                                       |ndp|ndp|                   |
- *    |-------------------------------------------------------------------|
+ *    |31 28|27|26|25|24|23|22|21 19|18 16|15  | 11| 10|9 8|7             0|
+ *    |-----+--+--+--+--+-----------------+----+---+---+---+---------------|
+ *    |rsvd1|DT|OV|PS|SS|      ring_id    |     pdev_id    |    msg_type   |
+ *    |-----------------------+-----+-----+--------------------------------|
+ *    |rsvd2|RX|RXHDL|   CLD  | CLC | CLM |           ring_buffer_size     |
+ *    |--------------------------------------------------------------------|
+ *    |                         packet_type_enable_flags_0                 |
+ *    |--------------------------------------------------------------------|
+ *    |                         packet_type_enable_flags_1                 |
+ *    |--------------------------------------------------------------------|
+ *    |                         packet_type_enable_flags_2                 |
+ *    |--------------------------------------------------------------------|
+ *    |                         packet_type_enable_flags_3                 |
+ *    |--------------------------------------------------------------------|
+ *    |                          tlv_filter_in_flags                       |
+ *    |-----------------------------------+--------------------------------|
+ *    |          rx_header_offset         |       rx_packet_offset         |
+ *    |-----------------------------------+--------------------------------|
+ *    |        rx_mpdu_start_offset       |      rx_mpdu_end_offset        |
+ *    |-----------------------------------+--------------------------------|
+ *    |        rx_msdu_start_offset       |      rx_msdu_end_offset        |
+ *    |-----------------------------------+--------------------------------|
+ *    |               rsvd3               |      rx_attention_offset       |
+ *    |--------------------------------------------------------------------|
+ *    |               rsvd4                    | mo| fp| rx_drop_threshold |
+ *    |                                        |ndp|ndp|                   |
+ *    |--------------------------------------------------------------------|
  * Where:
  *     PS = pkt_swap
  *     SS = status_swap
  *     OV = rx_offsets_valid
  *     DT = drop_thresh_valid
+ *     CLM = config_length_mgmt
+ *     CLC = config_length_ctrl
+ *     CLD = config_length_data
+ *     RXHDL = rx_hdr_len
+ *     RX = rxpcu_filter_enable_flag
  * The message is interpreted as follows:
  * dword0 - b'0:7   - msg_type: This will be set to
  *                    0xc (HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG)
@@ -5620,7 +5626,15 @@ enum htt_srng_ring_id {
  *                    10 - 128bytes
  *                    11 - 256bytes
  *                    default - 128 bytes
- *          b'27:31 - rsvd2: Reserved for future use
+ *          b'27    - rxpcu_filter_enable_flag
+ *                    For Scan Radio Host CPU utilization is very high.
+ *                    In order to reduce CPU utilization we need to filter out
+ *                    certain configured MAC frames.
+ *                    To filter out configured MAC address frames, RxPCU should
+ *                    be zero which means allow all frames for MD at RxOLE
+ *                    host wil fiter out frames.
+ *                    RxPCU (Filter IN) -> RxOLE (Filter In/Filter Out)
+ *          b'28:31 - rsvd2: Reserved for future use
  * dword2 - b'0:31  - packet_type_enable_flags_0:
  *                    Enable MGMT packet from 0b0000 to 0b1001
  *                    bits from low to high: FP, MD, MO - 3 bits
@@ -5759,7 +5773,8 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
              config_length_ctrl:3,
              config_length_data:3,
              rx_hdr_len:        2,
-             rsvd2:             5;
+             rxpcu_filter_enable_flag:1,
+             rsvd2:             4;
     A_UINT32 packet_type_enable_flags_0;
     A_UINT32 packet_type_enable_flags_1;
     A_UINT32 packet_type_enable_flags_2;
@@ -5933,6 +5948,17 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
                 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S));\
             } while(0)
 
+#define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_M               0x08000000
+#define HTT_RX_RING_SELECTION_CFG_RXPXU_FILTER_S               27
+#define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_GET(_var) \
+    (((_var) & HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_M) >> \
+        HTT_RX_RING_SELECTION_CFG_RXPXU_FILTER_S)
+#define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL( HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER, _val); \
+        ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXPXU_FILTER_S));\
+    } while(0)
+
 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_M     0xffffffff
 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_S     0
 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_GET(_var) \

From 14e1479280085806a0e89b0a7716622b150c69e2 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 29 Oct 2022 06:00:53 -0700
Subject: [PATCH 21/21] fw-api: CL 20115927 - update fw common interface files

Change-Id: I489c2e09289f603b7e7dd8bbfa87da01edabbabe
HTT: add logical_link_id field in rx_peer_metadata_v1
CRs-Fixed: 2262693
---
 fw/htt.h | 24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index ab46e7499a52..e277103f6557 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -236,9 +236,10 @@
  * 3.109 Add HTT_T2H RX_ADDBA_EXTN,RX_DELBA_EXTN defs.
  * 3.110 Add more word_mask fields in htt_tx_monitor_cfg_t.
  * 3.111 Add RXPCU filter enable flag in RX_RING_SELECTION_CFG msg.
+ * 3.112 Add logical_link_id field in rx_peer_metadata_v1.
  */
 #define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 111
+#define HTT_CURRENT_VERSION_MINOR 112
 
 #define HTT_NUM_TX_FRAG_DESC  1024
 
@@ -18225,16 +18226,16 @@ PREPACK struct htt_rx_peer_metadata_v0 {
  *
  * The following diagram shows the format of the RX PEER METADATA V1 format.
  *
- * |31 29|28   26|25   24|23        16|15 14|   13  |12                   0|
- * |-----------------------------------------------------------------------|
- * |Rsvd2|CHIP ID|LMAC ID|  VDEV ID   |Rsvd1|ML PEER| SW PEER ID/ML PEER ID|
- * |-----------------------------------------------------------------------|
+ * |31 29|28   26|25   24|23   16|15           14|   13  |12                  0|
+ * |---------------------------------------------------------------------------|
+ * |Rsvd2|CHIP ID|LMAC ID|VDEV ID|logical_link_id|ML PEER|SW PEER ID/ML PEER ID|
+ * |---------------------------------------------------------------------------|
  */
 PREPACK struct htt_rx_peer_metadata_v1 {
     A_UINT32
         peer_id:         13,
         ml_peer_valid:   1,
-        reserved1:       2,
+        logical_link_id: 2,
         vdev_id:         8,
         lmac_id:         2,
         chip_id:         3,
@@ -18268,6 +18269,17 @@ PREPACK struct htt_rx_peer_metadata_v1 {
 #define HTT_RX_PEER_META_DATA_V1_VDEV_ID_GET(_var) \
     (((_var) & HTT_RX_PEER_META_DATA_V1_VDEV_ID_M) >> HTT_RX_PEER_META_DATA_V1_VDEV_ID_S)
 
+#define HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_S    14
+#define HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_M    0x0000c000
+#define HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_GET(_var) \
+    (((_var) & HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_M) >> HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_S)
+
+#define HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_SET(_var, _val) \
+    do {                                             \
+        HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID, _val);  \
+        ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_S)); \
+    } while (0)
+
 #define HTT_RX_PEER_META_DATA_V1_VDEV_ID_SET(_var, _val) \
     do {                                             \
         HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_VDEV_ID, _val);  \