mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-08 21:22:09 -04:00
Merge "net: stmmac: SDx55 EMAC HW configuration changes"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
9bef368bcd
4 changed files with 288 additions and 79 deletions
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@ -18,6 +18,7 @@ obj-$(CONFIG_DWMAC_LPC18XX) += dwmac-lpc18xx.o
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obj-$(CONFIG_DWMAC_MEDIATEK) += dwmac-mediatek.o
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obj-$(CONFIG_DWMAC_MESON) += dwmac-meson.o dwmac-meson8b.o
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obj-$(CONFIG_DWMAC_OXNAS) += dwmac-oxnas.o
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obj-$(CONFIG_DWMAC_QCOM_ETHQOS) += dwmac-qcom-gpio.o
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obj-$(CONFIG_DWMAC_QCOM_ETHQOS) += dwmac-qcom-ethqos.o
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obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o
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obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o
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@ -6,16 +6,12 @@
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/phy.h>
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#include <linux/regulator/consumer.h>
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#include "stmmac.h"
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#include "stmmac_platform.h"
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#include "dwmac-qcom-ethqos.h"
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#define RGMII_IO_MACRO_CONFIG 0x0
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#define SDCC_HC_REG_DLL_CONFIG 0x4
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#define SDCC_HC_REG_DDR_CONFIG 0xC
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#define SDCC_HC_REG_DLL_CONFIG2 0x10
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#define SDC4_STATUS 0x14
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#define SDCC_USR_CTL 0x18
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#define RGMII_IO_MACRO_CONFIG2 0x1C
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#define RGMII_IO_MACRO_DEBUG1 0x20
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#define EMAC_SYSTEM_LOW_POWER_DEBUG 0x28
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@ -70,27 +66,8 @@
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#define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6)
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#define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5)
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struct ethqos_emac_por {
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unsigned int offset;
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unsigned int value;
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};
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struct ethqos_emac_driver_data {
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const struct ethqos_emac_por *por;
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unsigned int num_por;
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};
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struct qcom_ethqos {
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struct platform_device *pdev;
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void __iomem *rgmii_base;
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unsigned int rgmii_clk_rate;
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struct clk *rgmii_clk;
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unsigned int speed;
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const struct ethqos_emac_por *por;
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unsigned int num_por;
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};
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#define EMAC_I0_EMAC_CORE_HW_VERSION_RGOFFADDR 0x00000070
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#define EMAC_HW_v2_3_2_RG 0x20030002
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static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)
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{
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@ -167,28 +144,18 @@ static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos)
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RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG);
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}
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static const struct ethqos_emac_por emac_v2_3_0_por[] = {
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{ .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 },
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{ .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C },
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{ .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 },
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{ .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
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{ .offset = SDCC_USR_CTL, .value = 0x00010800 },
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{ .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
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};
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static const struct ethqos_emac_driver_data emac_v2_3_0_data = {
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.por = emac_v2_3_0_por,
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.num_por = ARRAY_SIZE(emac_v2_3_0_por),
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};
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static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
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{
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unsigned int val;
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int retry = 1000;
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/* Set CDR_EN */
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN,
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SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG);
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if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG)
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN,
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0, SDCC_HC_REG_DLL_CONFIG);
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else
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN,
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SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG);
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/* Set CDR_EXT_EN */
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN,
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@ -202,12 +169,13 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
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SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
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rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,
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0, SDCC_HC_REG_DLL_CONFIG);
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rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE,
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0, SDCC_HC_REG_DLL_CONFIG);
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if (ethqos->emac_ver != EMAC_HW_v2_3_2_RG) {
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rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,
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0, SDCC_HC_REG_DLL_CONFIG);
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rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE,
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0, SDCC_HC_REG_DLL_CONFIG);
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}
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/* Wait for CK_OUT_EN clear */
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do {
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val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
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@ -241,18 +209,20 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,
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SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2);
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,
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0, SDCC_HC_REG_DLL_CONFIG2);
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if (ethqos->emac_ver != EMAC_HW_v2_3_2_RG) {
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,
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0, SDCC_HC_REG_DLL_CONFIG2);
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC,
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0x1A << 10, SDCC_HC_REG_DLL_CONFIG2);
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC,
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0x1A << 10, SDCC_HC_REG_DLL_CONFIG2);
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL,
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BIT(2), SDCC_HC_REG_DLL_CONFIG2);
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL,
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BIT(2), SDCC_HC_REG_DLL_CONFIG2);
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
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SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
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SDCC_HC_REG_DLL_CONFIG2);
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
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SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
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SDCC_HC_REG_DLL_CONFIG2);
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}
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return 0;
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}
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@ -290,13 +260,22 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
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RGMII_IO_MACRO_CONFIG2);
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/* Set PRG_RCLK_DLY to 57 for 1.8 ns delay */
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rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
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57, SDCC_HC_REG_DDR_CONFIG);
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if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG)
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rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
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69, SDCC_HC_REG_DDR_CONFIG);
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else
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rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
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57, SDCC_HC_REG_DDR_CONFIG);
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rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,
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SDCC_DDR_CONFIG_PRG_DLY_EN,
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SDCC_HC_REG_DDR_CONFIG);
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rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
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RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG);
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if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG)
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rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
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0, RGMII_IO_MACRO_CONFIG);
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else
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rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
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RGMII_CONFIG_LOOPBACK_EN,
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RGMII_IO_MACRO_CONFIG);
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break;
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case SPEED_100:
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@ -318,8 +297,13 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
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BIT(6), RGMII_IO_MACRO_CONFIG);
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rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
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0, RGMII_IO_MACRO_CONFIG2);
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rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
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0, RGMII_IO_MACRO_CONFIG2);
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if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG)
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rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
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RGMII_CONFIG2_RX_PROG_SWAP,
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RGMII_IO_MACRO_CONFIG2);
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else
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rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
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0, RGMII_IO_MACRO_CONFIG2);
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/* Write 0x5 to PRG_RCLK_DLY_CODE */
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rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
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(BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
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@ -329,8 +313,13 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
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rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
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SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
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SDCC_HC_REG_DDR_CONFIG);
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rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
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RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG);
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if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG)
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rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
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0, RGMII_IO_MACRO_CONFIG);
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else
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rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
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RGMII_CONFIG_LOOPBACK_EN,
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RGMII_IO_MACRO_CONFIG);
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break;
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case SPEED_10:
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@ -345,15 +334,27 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
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0, RGMII_IO_MACRO_CONFIG);
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rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
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0, RGMII_IO_MACRO_CONFIG2);
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rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
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0, RGMII_IO_MACRO_CONFIG2);
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if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG)
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rgmii_updatel(ethqos,
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RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
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RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
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RGMII_IO_MACRO_CONFIG2);
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else
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rgmii_updatel(ethqos,
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RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
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0, RGMII_IO_MACRO_CONFIG2);
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rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9,
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BIT(12) | GENMASK(9, 8),
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RGMII_IO_MACRO_CONFIG);
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rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
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0, RGMII_IO_MACRO_CONFIG2);
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rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
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0, RGMII_IO_MACRO_CONFIG2);
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if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG)
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rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
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RGMII_CONFIG2_RX_PROG_SWAP,
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RGMII_IO_MACRO_CONFIG2);
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else
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rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
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0, RGMII_IO_MACRO_CONFIG2);
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/* Write 0x5 to PRG_RCLK_DLY_CODE */
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rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
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(BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
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@ -363,8 +364,13 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
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rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
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SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
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SDCC_HC_REG_DDR_CONFIG);
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rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
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RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG);
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if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG)
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rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
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0, RGMII_IO_MACRO_CONFIG);
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else
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rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
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RGMII_CONFIG_LOOPBACK_EN,
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RGMII_IO_MACRO_CONFIG);
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break;
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default:
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dev_err(ðqos->pdev->dev,
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@ -461,19 +467,21 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
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if (ret)
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return ret;
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ethqos = devm_kzalloc(&pdev->dev, sizeof(*ethqos), GFP_KERNEL);
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if (!ethqos) {
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ret = -ENOMEM;
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goto err_mem;
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}
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ethqos->pdev = pdev;
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ethqos_init_reqgulators(ethqos);
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plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
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if (IS_ERR(plat_dat)) {
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dev_err(&pdev->dev, "dt configuration failed\n");
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return PTR_ERR(plat_dat);
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}
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ethqos = devm_kzalloc(&pdev->dev, sizeof(*ethqos), GFP_KERNEL);
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if (!ethqos) {
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ret = -ENOMEM;
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goto err_mem;
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}
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ethqos->pdev = pdev;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rgmii");
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ethqos->rgmii_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(ethqos->rgmii_base)) {
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@ -510,6 +518,9 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
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if (ret)
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goto err_clk;
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ethqos->emac_ver = rgmii_readl(ethqos,
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EMAC_I0_EMAC_CORE_HW_VERSION_RGOFFADDR);
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rgmii_dump(ethqos);
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return ret;
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@ -534,12 +545,14 @@ static int qcom_ethqos_remove(struct platform_device *pdev)
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ret = stmmac_pltfr_remove(pdev);
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clk_disable_unprepare(ethqos->rgmii_clk);
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ethqos_disable_regulators(ethqos);
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return ret;
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}
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static const struct of_device_id qcom_ethqos_match[] = {
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{ .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data},
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{ .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_por},
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{ .compatible = "qcom,sdxprairie-ethqos", .data = &emac_v2_3_2_por},
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{ }
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};
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MODULE_DEVICE_TABLE(of, qcom_ethqos_match);
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|
|
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66
drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.h
Normal file
66
drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.h
Normal file
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@ -0,0 +1,66 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DWMAC_QCOM_ETHQOS_H
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#define _DWMAC_QCOM_ETHQOS_H
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#define DRV_NAME "qcom-ethqos"
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#define ETHQOSDBG(fmt, args...) \
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pr_debug(DRV_NAME " %s:%d " fmt, __func__, ## args)
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#define ETHQOSERR(fmt, args...) \
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pr_err(DRV_NAME " %s:%d " fmt, __func__, ## args)
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#define ETHQOSINFO(fmt, args...) \
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pr_info(DRV_NAME " %s:%d " fmt, __func__, ## args)
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#define RGMII_IO_MACRO_CONFIG 0x0
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#define SDCC_HC_REG_DLL_CONFIG 0x4
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#define SDCC_HC_REG_DDR_CONFIG 0xC
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#define SDCC_HC_REG_DLL_CONFIG2 0x10
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#define SDC4_STATUS 0x14
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#define SDCC_USR_CTL 0x18
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#define RGMII_IO_MACRO_CONFIG2 0x1C
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struct ethqos_emac_por {
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unsigned int offset;
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unsigned int value;
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};
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static const struct ethqos_emac_por emac_v2_3_0_por[] = {
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{ .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 },
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{ .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C },
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{ .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 },
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{ .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
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{ .offset = SDCC_USR_CTL, .value = 0x00010800 },
|
||||
{ .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
|
||||
};
|
||||
|
||||
static const struct ethqos_emac_por emac_v2_3_2_por[] = {
|
||||
{ .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 },
|
||||
{ .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C },
|
||||
{ .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 },
|
||||
{ .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
|
||||
{ .offset = SDCC_USR_CTL, .value = 0x00010800 },
|
||||
{ .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
|
||||
};
|
||||
|
||||
struct qcom_ethqos {
|
||||
struct platform_device *pdev;
|
||||
void __iomem *rgmii_base;
|
||||
|
||||
unsigned int rgmii_clk_rate;
|
||||
struct clk *rgmii_clk;
|
||||
unsigned int speed;
|
||||
|
||||
const struct ethqos_emac_por *por;
|
||||
unsigned int num_por;
|
||||
unsigned int emac_ver;
|
||||
|
||||
struct regulator *gdsc_emac;
|
||||
struct regulator *reg_rgmii;
|
||||
struct regulator *reg_emac_phy;
|
||||
struct regulator *reg_rgmii_io_pads;
|
||||
};
|
||||
|
||||
int ethqos_init_reqgulators(struct qcom_ethqos *ethqos);
|
||||
void ethqos_disable_regulators(struct qcom_ethqos *ethqos);
|
||||
#endif
|
||||
129
drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-gpio.c
Normal file
129
drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-gpio.c
Normal file
|
|
@ -0,0 +1,129 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/regulator/consumer.h>
|
||||
|
||||
#include "stmmac.h"
|
||||
#include "dwmac-qcom-ethqos.h"
|
||||
|
||||
#define EMAC_GDSC_EMAC_NAME "gdsc_emac"
|
||||
#define EMAC_VREG_RGMII_NAME "vreg_rgmii"
|
||||
#define EMAC_VREG_EMAC_PHY_NAME "vreg_emac_phy"
|
||||
#define EMAC_VREG_RGMII_IO_PADS_NAME "vreg_rgmii_io_pads"
|
||||
|
||||
int ethqos_init_reqgulators(struct qcom_ethqos *ethqos)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (of_property_read_bool(ethqos->pdev->dev.of_node,
|
||||
"gdsc_emac-supply")) {
|
||||
ethqos->gdsc_emac =
|
||||
devm_regulator_get(ðqos->pdev->dev, EMAC_GDSC_EMAC_NAME);
|
||||
if (IS_ERR(ethqos->gdsc_emac)) {
|
||||
ETHQOSERR("Can not get <%s>\n", EMAC_GDSC_EMAC_NAME);
|
||||
return PTR_ERR(ethqos->gdsc_emac);
|
||||
}
|
||||
|
||||
ret = regulator_enable(ethqos->gdsc_emac);
|
||||
if (ret) {
|
||||
ETHQOSERR("Can not enable <%s>\n", EMAC_GDSC_EMAC_NAME);
|
||||
goto reg_error;
|
||||
}
|
||||
|
||||
ETHQOSDBG("Enabled <%s>\n", EMAC_GDSC_EMAC_NAME);
|
||||
}
|
||||
|
||||
if (of_property_read_bool(ethqos->pdev->dev.of_node,
|
||||
"vreg_rgmii-supply")) {
|
||||
ethqos->reg_rgmii =
|
||||
devm_regulator_get(ðqos->pdev->dev, EMAC_VREG_RGMII_NAME);
|
||||
if (IS_ERR(ethqos->reg_rgmii)) {
|
||||
ETHQOSERR("Can not get <%s>\n", EMAC_VREG_RGMII_NAME);
|
||||
return PTR_ERR(ethqos->reg_rgmii);
|
||||
}
|
||||
|
||||
ret = regulator_enable(ethqos->reg_rgmii);
|
||||
if (ret) {
|
||||
ETHQOSERR("Can not enable <%s>\n",
|
||||
EMAC_VREG_RGMII_NAME);
|
||||
goto reg_error;
|
||||
}
|
||||
|
||||
ETHQOSDBG("Enabled <%s>\n", EMAC_VREG_RGMII_NAME);
|
||||
}
|
||||
|
||||
if (of_property_read_bool(ethqos->pdev->dev.of_node,
|
||||
"vreg_emac_phy-supply")) {
|
||||
ethqos->reg_emac_phy =
|
||||
devm_regulator_get(ðqos->pdev->dev, EMAC_VREG_EMAC_PHY_NAME);
|
||||
if (IS_ERR(ethqos->reg_emac_phy)) {
|
||||
ETHQOSERR("Can not get <%s>\n",
|
||||
EMAC_VREG_EMAC_PHY_NAME);
|
||||
return PTR_ERR(ethqos->reg_emac_phy);
|
||||
}
|
||||
|
||||
ret = regulator_enable(ethqos->reg_emac_phy);
|
||||
if (ret) {
|
||||
ETHQOSERR("Can not enable <%s>\n",
|
||||
EMAC_VREG_EMAC_PHY_NAME);
|
||||
goto reg_error;
|
||||
}
|
||||
|
||||
ETHQOSDBG("Enabled <%s>\n", EMAC_VREG_EMAC_PHY_NAME);
|
||||
}
|
||||
|
||||
if (of_property_read_bool(ethqos->pdev->dev.of_node,
|
||||
"vreg_rgmii_io_pads-supply")) {
|
||||
ethqos->reg_rgmii_io_pads = devm_regulator_get
|
||||
(ðqos->pdev->dev, EMAC_VREG_RGMII_IO_PADS_NAME);
|
||||
if (IS_ERR(ethqos->reg_rgmii_io_pads)) {
|
||||
ETHQOSERR("Can not get <%s>\n",
|
||||
EMAC_VREG_RGMII_IO_PADS_NAME);
|
||||
return PTR_ERR(ethqos->reg_rgmii_io_pads);
|
||||
}
|
||||
|
||||
ret = regulator_enable(ethqos->reg_rgmii_io_pads);
|
||||
if (ret) {
|
||||
ETHQOSERR("Can not enable <%s>\n",
|
||||
EMAC_VREG_RGMII_IO_PADS_NAME);
|
||||
goto reg_error;
|
||||
}
|
||||
|
||||
ETHQOSDBG("Enabled <%s>\n", EMAC_VREG_RGMII_IO_PADS_NAME);
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
||||
reg_error:
|
||||
ETHQOSERR("%s failed\n", __func__);
|
||||
ethqos_disable_regulators(ethqos);
|
||||
return ret;
|
||||
}
|
||||
|
||||
void ethqos_disable_regulators(struct qcom_ethqos *ethqos)
|
||||
{
|
||||
if (ethqos->reg_rgmii) {
|
||||
regulator_disable(ethqos->reg_rgmii);
|
||||
ethqos->reg_rgmii = NULL;
|
||||
}
|
||||
|
||||
if (ethqos->reg_emac_phy) {
|
||||
regulator_disable(ethqos->reg_emac_phy);
|
||||
ethqos->reg_emac_phy = NULL;
|
||||
}
|
||||
|
||||
if (ethqos->reg_rgmii_io_pads) {
|
||||
regulator_disable(ethqos->reg_rgmii_io_pads);
|
||||
ethqos->reg_rgmii_io_pads = NULL;
|
||||
}
|
||||
|
||||
if (ethqos->gdsc_emac) {
|
||||
regulator_disable(ethqos->gdsc_emac);
|
||||
ethqos->gdsc_emac = NULL;
|
||||
}
|
||||
}
|
||||
Loading…
Reference in a new issue