From 9c0e5c70543034f5041486914114fa5455557bbc Mon Sep 17 00:00:00 2001 From: Jeevan Shriram Date: Thu, 28 Feb 2019 14:30:12 -0800 Subject: [PATCH] drivers: pinctrl: Add support for read/write of QUP registers Add support to read and write QUP mode registers in TLMM block. Change-Id: I9878af50f6920c577fa74047e01e9b37c0542dd1 Signed-off-by: Rishabh Bhatnagar Signed-off-by: Jeevan Shriram [eberman@codeaurora.org: reintroduce msm_pinctrl_data] Signed-off-by: Elliot Berman --- drivers/pinctrl/qcom/pinctrl-msm.c | 43 +++++++++++++++++++++++++++- drivers/pinctrl/qcom/pinctrl-msm.h | 14 +++++++++ include/linux/pinctrl/qcom-pinctrl.h | 14 +++++++++ 3 files changed, 70 insertions(+), 1 deletion(-) create mode 100644 include/linux/pinctrl/qcom-pinctrl.h diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index e7edd341d025..46b1bd28cb70 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "../core.h" #include "../pinconf.h" @@ -31,6 +32,7 @@ #define MAX_NR_GPIO 300 #define MAX_NR_TILES 4 #define PS_HOLD_OFFSET 0x820 +#define QUP_MASK GENMASK(5, 0) /** * struct msm_pinctrl - state for a pinctrl-msm device @@ -66,6 +68,8 @@ struct msm_pinctrl { void __iomem *regs[MAX_NR_TILES]; }; +static struct msm_pinctrl *msm_pinctrl_data; + #define MSM_ACCESSOR(name) \ static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \ const struct msm_pingroup *g) \ @@ -1128,6 +1132,42 @@ SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend, EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops); +int msm_qup_write(u32 mode, u32 val) +{ + int i; + struct pinctrl_qup *regs = msm_pinctrl_data->soc->qup_regs; + int num_regs = msm_pinctrl_data->soc->nqup_regs; + + /*Iterate over modes*/ + for (i = 0; i < num_regs; i++) { + if (regs[i].mode == mode) { + writel_relaxed(val & QUP_MASK, + msm_pinctrl_data->regs[0] + regs[i].offset); + return 0; + } + } + + return -ENOENT; +} + +int msm_qup_read(unsigned int mode) +{ + int i, val; + struct pinctrl_qup *regs = msm_pinctrl_data->soc->qup_regs; + int num_regs = msm_pinctrl_data->soc->nqup_regs; + + /*Iterate over modes*/ + for (i = 0; i < num_regs; i++) { + if (regs[i].mode == mode) { + val = readl_relaxed(msm_pinctrl_data->regs[0] + + regs[i].offset); + return val & QUP_MASK; + } + } + + return -ENOENT; +} + int msm_pinctrl_probe(struct platform_device *pdev, const struct msm_pinctrl_soc_data *soc_data) { @@ -1136,7 +1176,8 @@ int msm_pinctrl_probe(struct platform_device *pdev, int ret; int i; - pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); + msm_pinctrl_data = pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), + GFP_KERNEL); if (!pctrl) return -ENOMEM; diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index e629a971a07b..3eaabe3f23f0 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -5,6 +5,8 @@ #ifndef __PINCTRL_MSM_H__ #define __PINCTRL_MSM_H__ +#include + struct pinctrl_pin_desc; /** @@ -93,6 +95,16 @@ struct msm_pingroup { unsigned intr_detection_width:5; }; +/* + * struct pinctrl_qup - Qup mode configuration + * @mode: Qup i3c mode + * @offset: Offset of the register + */ +struct pinctrl_qup { + u32 mode; + u32 offset; +}; + /** * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration * @pins: An array describing all pins the pin controller affects. @@ -116,6 +128,8 @@ struct msm_pinctrl_soc_data { const char *const *tiles; unsigned int ntiles; const int *reserved_gpios; + struct pinctrl_qup *qup_regs; + unsigned int nqup_regs; }; extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops; diff --git a/include/linux/pinctrl/qcom-pinctrl.h b/include/linux/pinctrl/qcom-pinctrl.h new file mode 100644 index 000000000000..1ea9a870514a --- /dev/null +++ b/include/linux/pinctrl/qcom-pinctrl.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef __LINUX_PINCTRL_MSM_H__ +#define __LINUX_PINCTRL_MSM_H__ + +/* APIS to access qup_i3c registers */ +int msm_qup_write(u32 mode, u32 val); +int msm_qup_read(u32 mode); + + +#endif /* __LINUX_PINCTRL_MSM_H__ */