mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 11:11:45 -04:00
ddr: add LPDDR2 data from JESD209-2
add LPDDR2 data from the JEDEC spec JESD209-2. The data includes: 1. Addressing information for LPDDR2 memories of different densities and types(S2/S4) 2. AC timing data. This data will useful for memory controller device drivers. Right now this is used by the TI EMIF SDRAM controller driver. Signed-off-by: Aneesh V <[email protected]> Reviewed-by: Santosh Shilimkar <[email protected]> Reviewed-by: Benoit Cousson <[email protected]> [[email protected]: Moved to drivers/memory from drivers/misc] Signed-off-by: Santosh Shilimkar <[email protected]> Tested-by: Lokesh Vutla <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
This commit is contained in:
Aneesh V
Greg Kroah-Hartman
parent
516cf1be07
commit
9c1c21a053
4 changed files with 320 additions and 0 deletions
|
|
@ -353,6 +353,14 @@ config CORDIC
|
|||
This option provides an implementation of the CORDIC algorithm;
|
||||
calculations are in fixed point. Module will be called cordic.
|
||||
|
||||
config DDR
|
||||
bool "JEDEC DDR data"
|
||||
help
|
||||
Data from JEDEC specs for DDR SDRAM memories,
|
||||
particularly the AC timing parameters and addressing
|
||||
information. This data is useful for drivers handling
|
||||
DDR SDRAM controllers.
|
||||
|
||||
config MPILIB
|
||||
tristate
|
||||
select CLZ_TAB
|
||||
|
|
|
|||
|
|
@ -123,6 +123,8 @@ obj-$(CONFIG_SIGNATURE) += digsig.o
|
|||
|
||||
obj-$(CONFIG_CLZ_TAB) += clz_tab.o
|
||||
|
||||
obj-$(CONFIG_DDR) += jedec_ddr_data.o
|
||||
|
||||
hostprogs-y := gen_crc32table
|
||||
clean-files := crc32table.h
|
||||
|
||||
|
|
|
|||
135
lib/jedec_ddr_data.c
Normal file
135
lib/jedec_ddr_data.c
Normal file
|
|
@ -0,0 +1,135 @@
|
|||
/*
|
||||
* DDR addressing details and AC timing parameters from JEDEC specs
|
||||
*
|
||||
* Copyright (C) 2012 Texas Instruments, Inc.
|
||||
*
|
||||
* Aneesh V <aneesh@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <memory/jedec_ddr.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
/* LPDDR2 addressing details from JESD209-2 section 2.4 */
|
||||
const struct lpddr2_addressing
|
||||
lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES] = {
|
||||
{B4, T_REFI_15_6, T_RFC_90}, /* 64M */
|
||||
{B4, T_REFI_15_6, T_RFC_90}, /* 128M */
|
||||
{B4, T_REFI_7_8, T_RFC_90}, /* 256M */
|
||||
{B4, T_REFI_7_8, T_RFC_90}, /* 512M */
|
||||
{B8, T_REFI_7_8, T_RFC_130}, /* 1GS4 */
|
||||
{B8, T_REFI_3_9, T_RFC_130}, /* 2GS4 */
|
||||
{B8, T_REFI_3_9, T_RFC_130}, /* 4G */
|
||||
{B8, T_REFI_3_9, T_RFC_210}, /* 8G */
|
||||
{B4, T_REFI_7_8, T_RFC_130}, /* 1GS2 */
|
||||
{B4, T_REFI_3_9, T_RFC_130}, /* 2GS2 */
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(lpddr2_jedec_addressing_table);
|
||||
|
||||
/* LPDDR2 AC timing parameters from JESD209-2 section 12 */
|
||||
const struct lpddr2_timings
|
||||
lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES] = {
|
||||
/* Speed bin 400(200 MHz) */
|
||||
[0] = {
|
||||
.max_freq = 200000000,
|
||||
.min_freq = 10000000,
|
||||
.tRPab = 21000,
|
||||
.tRCD = 18000,
|
||||
.tWR = 15000,
|
||||
.tRAS_min = 42000,
|
||||
.tRRD = 10000,
|
||||
.tWTR = 10000,
|
||||
.tXP = 7500,
|
||||
.tRTP = 7500,
|
||||
.tCKESR = 15000,
|
||||
.tDQSCK_max = 5500,
|
||||
.tFAW = 50000,
|
||||
.tZQCS = 90000,
|
||||
.tZQCL = 360000,
|
||||
.tZQinit = 1000000,
|
||||
.tRAS_max_ns = 70000,
|
||||
.tDQSCK_max_derated = 6000,
|
||||
},
|
||||
/* Speed bin 533(266 MHz) */
|
||||
[1] = {
|
||||
.max_freq = 266666666,
|
||||
.min_freq = 10000000,
|
||||
.tRPab = 21000,
|
||||
.tRCD = 18000,
|
||||
.tWR = 15000,
|
||||
.tRAS_min = 42000,
|
||||
.tRRD = 10000,
|
||||
.tWTR = 7500,
|
||||
.tXP = 7500,
|
||||
.tRTP = 7500,
|
||||
.tCKESR = 15000,
|
||||
.tDQSCK_max = 5500,
|
||||
.tFAW = 50000,
|
||||
.tZQCS = 90000,
|
||||
.tZQCL = 360000,
|
||||
.tZQinit = 1000000,
|
||||
.tRAS_max_ns = 70000,
|
||||
.tDQSCK_max_derated = 6000,
|
||||
},
|
||||
/* Speed bin 800(400 MHz) */
|
||||
[2] = {
|
||||
.max_freq = 400000000,
|
||||
.min_freq = 10000000,
|
||||
.tRPab = 21000,
|
||||
.tRCD = 18000,
|
||||
.tWR = 15000,
|
||||
.tRAS_min = 42000,
|
||||
.tRRD = 10000,
|
||||
.tWTR = 7500,
|
||||
.tXP = 7500,
|
||||
.tRTP = 7500,
|
||||
.tCKESR = 15000,
|
||||
.tDQSCK_max = 5500,
|
||||
.tFAW = 50000,
|
||||
.tZQCS = 90000,
|
||||
.tZQCL = 360000,
|
||||
.tZQinit = 1000000,
|
||||
.tRAS_max_ns = 70000,
|
||||
.tDQSCK_max_derated = 6000,
|
||||
},
|
||||
/* Speed bin 1066(533 MHz) */
|
||||
[3] = {
|
||||
.max_freq = 533333333,
|
||||
.min_freq = 10000000,
|
||||
.tRPab = 21000,
|
||||
.tRCD = 18000,
|
||||
.tWR = 15000,
|
||||
.tRAS_min = 42000,
|
||||
.tRRD = 10000,
|
||||
.tWTR = 7500,
|
||||
.tXP = 7500,
|
||||
.tRTP = 7500,
|
||||
.tCKESR = 15000,
|
||||
.tDQSCK_max = 5500,
|
||||
.tFAW = 50000,
|
||||
.tZQCS = 90000,
|
||||
.tZQCL = 360000,
|
||||
.tZQinit = 1000000,
|
||||
.tRAS_max_ns = 70000,
|
||||
.tDQSCK_max_derated = 5620,
|
||||
},
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(lpddr2_jedec_timings);
|
||||
|
||||
const struct lpddr2_min_tck lpddr2_jedec_min_tck = {
|
||||
.tRPab = 3,
|
||||
.tRCD = 3,
|
||||
.tWR = 3,
|
||||
.tRASmin = 3,
|
||||
.tRRD = 2,
|
||||
.tWTR = 2,
|
||||
.tXP = 2,
|
||||
.tRTP = 2,
|
||||
.tCKE = 3,
|
||||
.tCKESR = 3,
|
||||
.tFAW = 8
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(lpddr2_jedec_min_tck);
|
||||
Loading…
Reference in a new issue